]> sigrok.org Git - libsigrok.git/blobdiff - Makefile.am
transform: Add a "scale" transform module.
[libsigrok.git] / Makefile.am
index 1544a017c092aa1079de94186bb5d43f56de628c..c68ceeb3a9e06521df5be6252b7ff3e436200c8b 100644 (file)
@@ -68,6 +68,12 @@ libsigrok_la_SOURCES += \
        src/output/srzip.c \
        src/output/vcd.c
 
+# Transform modules
+libsigrok_la_SOURCES += \
+       src/transform/transform.c \
+       src/transform/nop.c \
+       src/transform/scale.c
+
 # SCPI support
 libsigrok_la_SOURCES += \
        src/scpi/scpi.c \
@@ -111,7 +117,7 @@ libsigrok_la_SOURCES += \
        src/dmm/ut71x.c
 
 # Hardware (LCR chip parsers)
-if HW_DEREE_DE5000
+if NEED_SERIAL
 libsigrok_la_SOURCES += \
        src/lcr/es51919.c
 endif
@@ -458,9 +464,9 @@ bindings/cxx/enums.cpp: bindings/cxx/enums.timestamp
 
 bindings/cxx/include/libsigrokcxx/enums.hpp: bindings/cxx/enums.timestamp
 
-bindings/cxx/enums.timestamp: bindings/cxx/enums.py doxy/xml/index.xml \
+bindings/cxx/enums.timestamp: $(srcdir)/bindings/cxx/enums.py doxy/xml/index.xml \
                bindings/cxx/ConfigKey_methods.cpp bindings/cxx/QuantityFlag_methods.cpp
-       $(AM_V_GEN)$(PYTHON) $< doxy/xml/index.xml
+       $(AM_V_GEN)$(PYTHON) $(srcdir)/bindings/cxx/enums.py doxy/xml/index.xml
        $(AM_V_at)touch $@
 
 bindings/cxx/classes.lo: bindings/cxx/classes.cpp bindings/cxx/enums.cpp \