+/* Derive trigger masks from the session's trigger configuration.
+ */
+static int prepare_trigger_masks(const struct sr_dev_inst *sdi)
+{
+ uint64_t trigger_mask, trigger_values, trigger_edge_mask;
+ uint64_t level_bit, type_bit;
+ struct dev_context *devc;
+ struct sr_trigger *trigger;
+ struct sr_trigger_stage *stage;
+ struct sr_trigger_match *match;
+ const GSList *node;
+ int idx;
+ enum sr_trigger_matches trg;
+
+ devc = sdi->priv;
+
+ trigger = sr_session_trigger_get(sdi->session);
+ if (!trigger || !trigger->stages)
+ return SR_OK;
+
+ if (trigger->stages->next) {
+ sr_err("This device only supports 1 trigger stage.");
+ return SR_ERR_ARG;
+ }
+ stage = trigger->stages->data;
+
+ trigger_mask = 0;
+ trigger_values = 0;
+ trigger_edge_mask = 0;
+
+ for (node = stage->matches; node; node = node->next) {
+ match = node->data;
+
+ if (!match->channel->enabled)
+ continue; /* Ignore disabled channel. */
+
+ idx = match->channel->index;
+ trg = match->match;
+
+ if (idx < 0 || idx >= devc->model->num_channels) {
+ sr_err("Channel index %d out of range.", idx);
+ return SR_ERR_BUG; /* Should not happen. */
+ }
+ if (trg != SR_TRIGGER_ZERO
+ && trg != SR_TRIGGER_ONE
+ && trg != SR_TRIGGER_RISING
+ && trg != SR_TRIGGER_FALLING) {
+ sr_err("Unsupported trigger match for CH%d.", idx + 1);
+ return SR_ERR_ARG;
+ }
+ level_bit = (trg == SR_TRIGGER_ONE
+ || trg == SR_TRIGGER_RISING) ? 1 : 0;
+ type_bit = (trg == SR_TRIGGER_RISING
+ || trg == SR_TRIGGER_FALLING) ? 1 : 0;
+
+ trigger_mask |= UINT64_C(1) << idx;
+ trigger_values |= level_bit << idx;
+ trigger_edge_mask |= type_bit << idx;
+ }
+ devc->trigger_mask = trigger_mask;
+ devc->trigger_values = trigger_values;
+ devc->trigger_edge_mask = trigger_edge_mask;
+
+ return SR_OK;
+}
+
+/* Apply current device configuration to the hardware.
+ */