+ SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET,
+ SR_CONF_EXTERNAL_CLOCK_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+ SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+};
+
+static const uint32_t devopts_fpga_zero[] = {
+ SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+ SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+ SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+ SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
+ SR_CONF_CONN | SR_CONF_GET,
+};
+
+static const uint32_t devopts_cg[] = {
+ SR_CONF_VOLTAGE_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+};
+
+static const char *signal_edges[] = {
+ [H4032L_CLOCK_EDGE_TYPE_RISE] = "rising",
+ [H4032L_CLOCK_EDGE_TYPE_FALL] = "falling",
+ [H4032L_CLOCK_EDGE_TYPE_BOTH] = "both",
+};
+
+static const char *ext_clock_sources[] = {
+ [H4032L_EXT_CLOCK_SOURCE_CHANNEL_A] = "ACLK",
+ [H4032L_EXT_CLOCK_SOURCE_CHANNEL_B] = "BCLK"
+};
+
+static const uint8_t ext_clock_edges[2][3] = {
+ {
+ H4032L_CLOCK_EDGE_TYPE_RISE_A,
+ H4032L_CLOCK_EDGE_TYPE_FALL_A,
+ H4032L_CLOCK_EDGE_TYPE_BOTH_A
+ },
+ {
+ H4032L_CLOCK_EDGE_TYPE_RISE_B,
+ H4032L_CLOCK_EDGE_TYPE_FALL_B,
+ H4032L_CLOCK_EDGE_TYPE_BOTH_B
+ }