+ case SR_CONF_VOLTAGE_THRESHOLD:
+ g_variant_get(data, "(dd)", &low, &high);
+ ret = SR_ERR_ARG;
+ for (i = 0; (unsigned int)i < ARRAY_SIZE(volt_thresholds); i++) {
+ if (fabs(volt_thresholds[i].low - low) < 0.1 &&
+ fabs(volt_thresholds[i].high - high) < 0.1) {
+ devc->dslogic_voltage_threshold = volt_thresholds[i].range;
+ break;
+ }
+ }
+ if (!strcmp(devc->profile->model, "DSLogic")) {
+ if (devc->dslogic_voltage_threshold == DS_VOLTAGE_RANGE_5_V)
+ ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_FPGA_FIRMWARE_5V);
+ else
+ ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_FPGA_FIRMWARE_3V3);
+ } else if (!strcmp(devc->profile->model, "DSLogic Pro")) {
+ ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_PRO_FPGA_FIRMWARE);
+ }
+ break;
+ case SR_CONF_EXTERNAL_CLOCK:
+ devc->dslogic_external_clock = g_variant_get_boolean(data);
+ break;
+ case SR_CONF_CONTINUOUS:
+ devc->dslogic_continuous_mode = g_variant_get_boolean(data);
+ break;
+ case SR_CONF_CLOCK_EDGE:
+ i = lookup_index(data, signal_edge_names,
+ ARRAY_SIZE(signal_edge_names));
+ if (i < 0)
+ return SR_ERR_ARG;
+ devc->dslogic_clock_edge = i;
+ break;