-#define REG_DRAM_WAIT_ACK (0x5 << 4)
-
-/* Bit (1 << 4) can be low or high (double buffer / cache) */
-#define REG_DRAM_BLOCK (0x6 << 4)
-#define REG_DRAM_BLOCK_BEGIN (0x8 << 4)
-#define REG_DRAM_BLOCK_DATA (0xa << 4)
+#define REG_ADDR_ADJUST (1 << 0) /* Auto adjust register address. */
+#define REG_ADDR_DOWN (1 << 1) /* 1 decrement, 0 increment. */
+#define REG_ADDR_INC (REG_ADDR_ADJUST)
+#define REG_ADDR_DEC (REG_ADDR_ADJUST | REG_ADDR_DOWN)
+
+/* Sample memory access. */
+#define REG_DRAM_WAIT_ACK (0x5 << 4) /* Wait for completion. */
+#define REG_DRAM_BLOCK (0x6 << 4) /* DRAM to BRAM, plus bank select. */
+#define REG_DRAM_BLOCK_BEGIN (0x8 << 4) /* Read first BRAM bytes. */
+#define REG_DRAM_BLOCK_DATA (0xa << 4) /* Read full BRAM block. */
+#define REG_DRAM_SEL_N (0x1 << 4) /* Bank select, added to 6/8/a. */
+#define REG_DRAM_SEL_BOOL(b) ((b) ? REG_DRAM_SEL_N : 0)