+ * Determine the position where to open the period of trigger match
+ * checks. Setup an "impossible" location when triggers are not used.
+ * Start from the hardware provided 'trig' position otherwise, and
+ * go back a few clusters, but don't go before the 'start' position.
+ */
+static void rewind_trig_arm_pos(struct dev_context *devc, size_t count)
+{
+ struct sigma_sample_interp *interp;
+
+ if (!devc)
+ return;
+ interp = &devc->interp;
+
+ if (!devc->use_triggers) {
+ interp->trig_arm.raw = ~0;
+ sigma_location_break_down(&interp->trig_arm);
+ return;
+ }
+
+ interp->trig_arm = interp->trig;
+ while (count--) {
+ if (sigma_location_is_eq(&interp->trig_arm, &interp->start, TRUE))
+ break;
+ sigma_location_decrement(&interp->trig_arm, TRUE);
+ }
+}
+
+static int alloc_sample_buffer(struct dev_context *devc,
+ size_t stop_pos, size_t trig_pos, uint8_t mode)
+{
+ struct sigma_sample_interp *interp;
+ gboolean wrapped;
+ size_t alloc_size;
+
+ interp = &devc->interp;
+
+ /*
+ * Either fetch sample memory from absolute start of DRAM to the
+ * current write position. Or from after the current write position
+ * to before the current write position, if the write pointer has
+ * wrapped around at the upper DRAM boundary. Assume that the line
+ * which most recently got written to is of unknown state, ignore
+ * its content in the "wrapped" case.
+ */
+ wrapped = mode & RMR_ROUND;
+ interp->start.raw = 0;
+ interp->stop.raw = stop_pos;
+ if (wrapped) {
+ interp->start.raw = stop_pos;
+ interp->start.raw >>= ROW_SHIFT;
+ interp->start.raw++;
+ interp->start.raw <<= ROW_SHIFT;
+ interp->stop.raw = stop_pos;
+ interp->stop.raw >>= ROW_SHIFT;
+ interp->stop.raw--;
+ interp->stop.raw <<= ROW_SHIFT;
+ }
+ interp->trig.raw = trig_pos;
+ interp->iter.raw = 0;
+
+ /* Break down raw values to line, cluster, event fields. */
+ sigma_location_break_down(&interp->start);
+ sigma_location_break_down(&interp->stop);
+ sigma_location_break_down(&interp->trig);
+ sigma_location_break_down(&interp->iter);
+
+ /*
+ * The hardware provided trigger location "is late" because of
+ * latency in hardware pipelines. It points to after the trigger
+ * condition match. Arrange for a software check of sample data
+ * matches starting just a little before the hardware provided
+ * location. The "4 clusters" distance is an arbitrary choice.
+ */
+ rewind_trig_arm_pos(devc, 4 * EVENTS_PER_CLUSTER);
+ memset(&interp->trig_chk, 0, sizeof(interp->trig_chk));
+
+ /* Determine which DRAM lines to fetch from the device. */
+ memset(&interp->fetch, 0, sizeof(interp->fetch));
+ interp->fetch.lines_total = interp->stop.line + 1;
+ interp->fetch.lines_total -= interp->start.line;
+ interp->fetch.lines_total += ROW_COUNT;
+ interp->fetch.lines_total %= ROW_COUNT;
+ interp->fetch.lines_done = 0;
+
+ /* Arrange for chunked download, N lines per USB request. */
+ interp->fetch.lines_per_read = 32;
+ alloc_size = sizeof(devc->interp.fetch.rcvd_lines[0]);
+ alloc_size *= devc->interp.fetch.lines_per_read;
+ devc->interp.fetch.rcvd_lines = g_try_malloc0(alloc_size);
+ if (!devc->interp.fetch.rcvd_lines)
+ return SR_ERR_MALLOC;
+
+ return SR_OK;
+}
+
+static uint16_t sigma_deinterlace_data_4x4(uint16_t indata, int idx);
+static uint16_t sigma_deinterlace_data_2x8(uint16_t indata, int idx);
+
+static int fetch_sample_buffer(struct dev_context *devc)
+{
+ struct sigma_sample_interp *interp;
+ size_t count;
+ int ret;
+ const uint8_t *rdptr;
+ uint16_t ts, data;
+
+ interp = &devc->interp;
+
+ /* First invocation? Seed the iteration position. */
+ if (!interp->fetch.lines_done) {
+ interp->iter = interp->start;
+ }
+
+ /* Get another set of DRAM lines in one read call. */
+ count = interp->fetch.lines_total - interp->fetch.lines_done;
+ if (count > interp->fetch.lines_per_read)
+ count = interp->fetch.lines_per_read;
+ ret = sigma_read_dram(devc, interp->iter.line, count,
+ (uint8_t *)interp->fetch.rcvd_lines);
+ if (ret != SR_OK)
+ return ret;
+ interp->fetch.lines_rcvd = count;
+ interp->fetch.curr_line = &interp->fetch.rcvd_lines[0];
+
+ /* First invocation? Get initial timestamp and sample data. */
+ if (!interp->fetch.lines_done) {
+ rdptr = (void *)interp->fetch.curr_line;
+ ts = read_u16le_inc(&rdptr);
+ data = read_u16le_inc(&rdptr);
+ if (interp->samples_per_event == 4) {
+ data = sigma_deinterlace_data_4x4(data, 0);
+ } else if (interp->samples_per_event == 2) {
+ data = sigma_deinterlace_data_2x8(data, 0);
+ }
+ interp->last.ts = ts;
+ interp->last.sample = data;
+ }
+
+ return SR_OK;
+}
+
+static void free_sample_buffer(struct dev_context *devc)
+{
+ g_free(devc->interp.fetch.rcvd_lines);
+ devc->interp.fetch.rcvd_lines = NULL;
+ devc->interp.fetch.lines_per_read = 0;
+}
+
+/*
+ * Parse application provided trigger conditions to the driver's internal
+ * presentation. Yields a mask of pins of interest, and their expected
+ * pin levels or edges.
+ *
+ * In 100 and 200 MHz mode, only a single pin's rising/falling edge can be
+ * set as trigger. In 50- MHz modes, two rising/falling edges can be set,
+ * in addition to value/mask specs for any number of channels.
+ *
+ * Hardware implementation detail: When more than one edge is specified,
+ * then the condition is only considered a match when _all_ transitions
+ * are seen in the same 20ns check interval, regardless of the user's
+ * perceived samplerate which can be a fraction of 50MHz. Which reduces
+ * practical use to edges on a single pin in addition to data patterns.
+ * Which still covers a lot of users' typical scenarios. Not an issue,
+ * just something to remain aware of.
+ *
+ * The Sigma hardware also supports complex triggers which involve the
+ * logical combination of several patterns, pulse durations, counts of
+ * condition matches, A-then-B sequences, etc. But this has not been
+ * implemented yet here, and applications may lack means to express
+ * these conditions (present the complex conditions to users for entry
+ * and review, pass application specs to drivers covering the versatile
+ * combinations).
+ *
+ * Implementor's note: This routine currently exclusively accepts input
+ * in the form of sr_trigger stages, which results from "01rf-" choices
+ * on a multitude of individual GUI traces, or the CLI's --trigger spec
+ * which takes one list of <pin>=<value/edge> details.
+ *
+ * TODO Consider the addition of SR_CONF_TRIGGER_PATTERN support, which
+ * accepts a single free form string argument, and could describe a
+ * multi-bit pattern without the tedious trace name/index selection.
+ * Fortunately the number of channels is fixed for this device, we need
+ * not come up with variable length support and counts beyond 64. _When_
+ * --trigger as well as SR_CONF_TRIGGER_PATTERN are supported, then the
+ * implementation needs to come up with priorities for these sources of
+ * input specs, or enforce exclusive use of either form (at one time,
+ * per acquisition / invocation).
+ *
+ * Text forms that may be worth supporting:
+ * - Simple forms, mere numbers, optional base specs. These are easiest
+ * to implement with existing common conversion helpers.
+ * triggerpattern=<value>[/<mask>]
+ * triggerpattern=255
+ * triggerpattern=45054
+ * triggerpattern=0xaffe
+ * triggerpattern=0xa0f0/0xf0f0
+ * triggerpattern=0b1010111111111110/0x7ffe
+ * - Alternative bit pattern form, including wildcards in a single value.
+ * This cannot use common conversion support, needs special handling.
+ * triggerpattern=0b1010xxxx1111xxx0
+ * This is most similar to SR_CONF_TRIGGER_PATTERN as hameg-hmo uses
+ * it. Passes the app's spec via SCPI to the device. See section 2.3.5
+ * "Pattern trigger" and :TRIG:A:PATT:SOUR in the Hameg document.
+ * - Prefixed form to tell the above variants apart, and support both of
+ * them at the same time. Additional optional separator for long digit
+ * runs, and edge support in the form which lists individual bits (not
+ * useful for dec/hex formats).
+ * triggerpattern=value=45054
+ * triggerpattern=value=0b1010111111111110
+ * triggerpattern=value=0xa0f0,mask=0xf0f0
+ * triggerpattern=bits=1010-xxxx-1111-xxxx
+ * triggerpattern=bits=0010-r100