- /*
- * 50 MHz mode, or fraction thereof. The 50MHz reference
- * can get divided by any integer in the range 1 to 256.
- * Divider minus 1 gets written to the hardware.
- * (The driver lists a discrete set of sample rates, but
- * all of them fit the above description.)
- */
- clockselect.fraction = SR_MHZ(50) / devc->samplerate;
+ wrptr = cmd_bytes;
+ /* Select 50MHz base clock, and divider. */
+ async = 0;
+ div = SR_MHZ(50) / devc->clock.samplerate - 1;
+ if (devc->clock.use_ext_clock) {
+ async = CLKSEL_CLKSEL8;
+ div = devc->clock.clock_pin + 1;
+ switch (devc->clock.clock_edge) {
+ case SIGMA_CLOCK_EDGE_RISING:
+ div |= CLKSEL_RISING;
+ break;
+ case SIGMA_CLOCK_EDGE_FALLING:
+ div |= CLKSEL_FALLING;
+ break;
+ case SIGMA_CLOCK_EDGE_EITHER:
+ div |= CLKSEL_RISING;
+ div |= CLKSEL_FALLING;
+ break;
+ }
+ }
+ write_u8_inc(&wrptr, async);
+ write_u8_inc(&wrptr, div);
+ write_u16be_inc(&wrptr, pindis_mask);
+ ret = sigma_write_register(devc, WRITE_CLOCK_SELECT,
+ cmd_bytes, wrptr - cmd_bytes);