Add captures specific to PD coverage testing.

[sigrok-dumps.git] / spi / mx25l1605d / README

diff --git a/spi/mx25l1605d/README b/spi/mx25l1605d/README
index 79d7b2a6e15de617b63078f9b0aa5f3d1619aa15..920ae313a1643f9909e937fe8d18572296a82604 100644 (file)
--- a/spi/mx25l1605d/README
+++ b/spi/mx25l1605d/README
@@ -18,20 +18,16 @@ The software used for programming it is flashrom, see
 Logic analyzer setup
 --------------------
 
 Logic analyzer setup
 --------------------
 

-The logic analyzer used for capturing is a ChronoVu LA8 at a sample rate
-of 25MHz.
+The logic analyzer used was a ChronoVu LA8 (at 25MHz):

 
 

-The ChronoVu LA8 probes were connected to the MX25L1605D chip like this:
-
-  Probe       SPI chip pin
-  ------------------------
+  Probe       MX25L1605D pin
+  --------------------------

   0 (green)   CS#
   1 (orange)  SO/SIO1 (a.k.a MISO)
   2 (white)   SCLK
   3 (red)     SI/SIO0 (a.k.a MOSI)
   4 (gray)    WP#/ACC
   5 (brown)   HOLD#
   0 (green)   CS#
   1 (orange)  SO/SIO1 (a.k.a MISO)
   2 (white)   SCLK
   3 (red)     SI/SIO0 (a.k.a MOSI)
   4 (gray)    WP#/ACC
   5 (brown)   HOLD#

-  GND         GND

 
 
 Probing
 
 
 Probing


@@ -46,7 +42,7 @@ The sigrok command line used was:
   sigrok-cli -d 0:samplerate=25mhz --samples 8388608 \
              -p '1=CS#,2=MISO,3=SCLK,4=MOSI,5=WP#,6=HOLD#' \
              --wait-trigger --triggers 3=1 \
   sigrok-cli -d 0:samplerate=25mhz --samples 8388608 \
              -p '1=CS#,2=MISO,3=SCLK,4=MOSI,5=WP#,6=HOLD#' \
              --wait-trigger --triggers 3=1 \

-             -o mx25l1605d_probe.sigrok
+             -o mx25l1605d_probe.sr

 
 The capturing starts when the SCLK signal is high for the first time
 (it's low per default). We capture as many samples as fit into the 8MByte
 
 The capturing starts when the SCLK signal is high for the first time
 (it's low per default). We capture as many samples as fit into the 8MByte


@@ -69,7 +65,7 @@ The sigrok command line used was:
 
   sigrok-cli -d 0:samplerate=25mhz --samples 8388608 \
              -p '1=CS#,2=MISO,3=SCLK,4=MOSI,5=WP#,6=HOLD#' \
 
   sigrok-cli -d 0:samplerate=25mhz --samples 8388608 \
              -p '1=CS#,2=MISO,3=SCLK,4=MOSI,5=WP#,6=HOLD#' \

-             -o mx25l1605d_write.sigrok
+             -o mx25l1605d_write.sr

 
 The capture is only partial, it contains a small part of the write process
 (it does not contain the chip identification, chip erase, etc. which comes
 
 The capture is only partial, it contains a small part of the write process
 (it does not contain the chip identification, chip erase, etc. which comes


@@ -88,7 +84,7 @@ The sigrok command line used was:
 
   sigrok-cli -d 0:samplerate=25mhz --samples 8388608 \
              -p '1=CS#,2=MISO,3=SCLK,4=MOSI,5=WP#,6=HOLD#' \
 
   sigrok-cli -d 0:samplerate=25mhz --samples 8388608 \
              -p '1=CS#,2=MISO,3=SCLK,4=MOSI,5=WP#,6=HOLD#' \

-             -o mx25l1605d_read.sigrok
+             -o mx25l1605d_read.sr

 
 The capture only contains a small part of the read procedure. The data in
 the chip consists of consecutive "HelloWorld" ASCII strings.
 
 The capture only contains a small part of the read procedure. The data in
 the chip consists of consecutive "HelloWorld" ASCII strings.


@@ -105,7 +101,7 @@ The sigrok command line used was:
 
   sigrok-cli -d 0:samplerate=25mhz --samples 8388608 \
              -p '1=CS#,2=MISO,3=SCLK,4=MOSI,5=WP#,6=HOLD#' \
 
   sigrok-cli -d 0:samplerate=25mhz --samples 8388608 \
              -p '1=CS#,2=MISO,3=SCLK,4=MOSI,5=WP#,6=HOLD#' \

-             -o mx25l1605d_erase.sigrok
+             -o mx25l1605d_erase.sr

 
 The capture does not contain the full erase process, only a small part of it.
 
 
 The capture does not contain the full erase process, only a small part of it.