+ struct freq_factor {
+ int freq;
+ int scale;
+ int sel;
+ int div;
+ int mul;
+ };
+
+ static const struct freq_factor f[] = {
+ { 200, FREQ_SCALE_MHZ, 0, 1, 20 },
+ { 150, FREQ_SCALE_MHZ, 0, 1, 15 },
+ { 100, FREQ_SCALE_MHZ, 0, 1, 10 },
+ { 80, FREQ_SCALE_MHZ, 0, 2, 16 },
+ { 50, FREQ_SCALE_MHZ, 0, 2, 10 },
+ { 25, FREQ_SCALE_MHZ, 1, 5, 25 },
+ { 10, FREQ_SCALE_MHZ, 1, 5, 10 },
+ { 1, FREQ_SCALE_MHZ, 16, 5, 5 },
+ { 800, FREQ_SCALE_KHZ, 17, 5, 8 },
+ { 400, FREQ_SCALE_KHZ, 32, 5, 20 },
+ { 200, FREQ_SCALE_KHZ, 32, 5, 10 },
+ { 100, FREQ_SCALE_KHZ, 32, 5, 5 },
+ { 50, FREQ_SCALE_KHZ, 33, 5, 5 },
+ { 25, FREQ_SCALE_KHZ, 49, 5, 25 },
+ { 5, FREQ_SCALE_KHZ, 50, 5, 10 },
+ { 1, FREQ_SCALE_KHZ, 64, 5, 5 },
+ { 500, FREQ_SCALE_HZ, 64, 10, 5 },
+ { 100, FREQ_SCALE_HZ, 68, 5, 8 },
+ { 0, 0, 0, 0, 0 }
+ };
+
+ int i;
+
+ for (i = 0; f[i].freq; i++) {
+ if (scale == f[i].scale && freq == f[i].freq)
+ break;
+ }
+ if (!f[i].freq)
+ return -1;
+
+ sr_dbg("Setting samplerate regs (freq=%d, scale=%d): "
+ "reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
+ freq, scale, f[i].div, f[i].mul, 0x02, f[i].sel);
+
+ if (gl_reg_write(devh, FREQUENCY_REG0, f[i].div) < 0)
+ return -1;
+
+ if (gl_reg_write(devh, FREQUENCY_REG1, f[i].mul) < 0)
+ return -1;
+
+ if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
+ return -1;
+
+ if (gl_reg_write(devh, FREQUENCY_REG4, f[i].sel) < 0)
+ return -1;
+
+ return 0;
+}
+
+static void __analyzer_set_ramsize_trigger_address(libusb_device_handle *devh,
+ unsigned int address)
+{
+ gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
+ gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);