+ switch (id) {
+ case SR_CONF_LIMIT_FRAMES:
+ devc->limit_frames = *(const uint64_t *)value;
+ break;
+ case SR_CONF_TRIGGER_SLOPE:
+ tmp_u64 = *(const int *)value;
+ rigol_ds1xx2_send_data(devc->fd, ":TRIG:EDGE:SLOP %s\n",
+ tmp_u64 ? "POS" : "NEG");
+ break;
+ case SR_CONF_HORIZ_TRIGGERPOS:
+ tmp_float = *(const float *)value;
+ rigol_ds1xx2_send_data(devc->fd, ":TIM:OFFS %.9f\n", tmp_float);
+ break;
+ case SR_CONF_TIMEBASE:
+ tmp_rat = *(const struct sr_rational *)value;
+ rigol_ds1xx2_send_data(devc->fd, ":TIM:SCAL %.9f\n",
+ (float)tmp_rat.p / tmp_rat.q);
+ break;
+ case SR_CONF_TRIGGER_SOURCE:
+ if (!strcmp(value, "CH1"))
+ channel = "CHAN1";
+ else if (!strcmp(value, "CH2"))
+ channel = "CHAN2";
+ else if (!strcmp(value, "EXT"))
+ channel = "EXT";
+ else if (!strcmp(value, "AC Line"))
+ channel = "ACL";
+ else {
+ ret = SR_ERR_ARG;
+ break;
+ }
+ rigol_ds1xx2_send_data(devc->fd, ":TRIG:EDGE:SOUR %s\n", channel);
+ break;
+ case SR_CONF_VDIV:
+ /* TODO: Not supporting vdiv per channel yet. */
+ tmp_rat = *(const struct sr_rational *)value;
+ for (i = 0; vdivs[i].p && vdivs[i].q; i++) {
+ if (vdivs[i].p == tmp_rat.p
+ && vdivs[i].q == tmp_rat.q) {
+ devc->scale = (float)tmp_rat.p / tmp_rat.q;
+ for (j = 0; j < 2; j++)
+ rigol_ds1xx2_send_data(devc->fd,
+ ":CHAN%d:SCAL %.3f\n", j, devc->scale);
+ break;
+ }
+ }
+ if (vdivs[i].p == 0 && vdivs[i].q == 0)
+ ret = SR_ERR_ARG;
+ break;
+ case SR_CONF_COUPLING:
+ /* TODO: Not supporting coupling per channel yet. */
+ for (i = 0; coupling[i]; i++) {
+ if (!strcmp(value, coupling[i])) {
+ for (j = 0; j < 2; j++)
+ rigol_ds1xx2_send_data(devc->fd,
+ ":CHAN%d:COUP %s\n", j, coupling[i]);
+ break;
+ }
+ }
+ if (coupling[i] == 0)
+ ret = SR_ERR_ARG;
+ break;