+}
+
+bool gpif_acquisition_start(const struct cmd_start_acquisition *cmd)
+{
+ int i;
+ volatile BYTE *pSTATE = &GPIF_WAVE_DATA;
+
+ /* Ensure GPIF is idle before reconfiguration. */
+ while (!(GPIFTRIG & 0x80));
+
+ /* Configure the EP2 FIFO. */
+ if (cmd->flags & CMD_START_FLAGS_SAMPLE_16BIT)
+ EP2FIFOCFG = bmAUTOIN | bmWORDWIDE;
+ else
+ EP2FIFOCFG = bmAUTOIN;
+ SYNCDELAY();
+
+ /* Set IFCONFIG to the correct clock source. */
+ if (cmd->flags & CMD_START_FLAGS_CLK_48MHZ) {
+ IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmASYNC |
+ bmGSTATE | bmIFGPIF;
+ } else {
+ IFCONFIG = bmIFCLKSRC | bmIFCLKOE | bmASYNC |
+ bmGSTATE | bmIFGPIF;
+ }
+
+ /* Populate delay states. */
+ if ((cmd->sample_delay_h == 0 && cmd->sample_delay_l == 0) ||
+ cmd->sample_delay_h >= 6)
+ return false;
+
+ if (cmd->flags & CMD_START_FLAGS_CLK_CTL2) {
+ uint8_t delay_1, delay_2 = cmd->sample_delay_l;
+
+ /* We need a pulse where the CTL1/2 pins alternate states. */
+ if (cmd->sample_delay_h) {
+ for (i = 0; i < cmd->sample_delay_h; i++)
+ gpif_make_delay_state(pSTATE++, 0, 0x06);
+ } else {
+ delay_1 = delay_2 / 2;
+ delay_2 -= delay_1;
+ gpif_make_delay_state(pSTATE++, delay_1, 0x06);
+ }
+
+ /* sample_delay_l is always != 0 for the supported rates. */
+ gpif_make_delay_state(pSTATE++, delay_2, 0x00);
+ } else {
+ for (i = 0; i < cmd->sample_delay_h; i++)
+ gpif_make_delay_state(pSTATE++, 0, 0x00);
+
+ if (cmd->sample_delay_l != 0)
+ gpif_make_delay_state(pSTATE++, cmd->sample_delay_l, 0x00);
+ }
+
+ /* Populate S1 - the decision point. */
+ gpif_make_data_dp_state(pSTATE++);