2 * This file is part of the libsigrok project.
4 * Copyright (C) 2010 Sven Peter <sven@fail0verflow.com>
5 * Copyright (C) 2010 Haxx Enterprises <bushing@gmail.com>
8 * Redistribution and use in source and binary forms, with or
9 * without modification, are permitted provided that the following
12 * * Redistributions of source code must retain the above copyright notice,
13 * this list of conditions and the following disclaimer.
15 * * Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
29 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include "libsigrok.h"
34 #include "libsigrok-internal.h"
40 HARD_DATA_CHECK_SUM = 0x00,
48 FREQUENCY_REG0 = 0x30,
56 TRIGGER_STATUS0 = 0x40,
66 TRIGGER_COUNT0 = 0x50,
69 TRIGGER_LEVEL0 = 0x55,
74 RAMSIZE_TRIGGERBAR_ADDRESS0 = 0x60,
75 RAMSIZE_TRIGGERBAR_ADDRESS1,
76 RAMSIZE_TRIGGERBAR_ADDRESS2,
85 ENABLE_DELAY_TIME0 = 0x7a,
88 ENABLE_INSERT_DATA0 = 0x80,
95 TRIGGER_ADDRESS0 = 0x90,
103 STOP_ADDRESS0 = 0x9b,
107 READ_RAM_STATUS = 0xa0,
110 static int g_trigger_status[9] = { 0 };
111 static int g_trigger_count = 1;
112 static int g_filter_status[8] = { 0 };
113 static int g_filter_enable = 0;
115 static int g_freq_value = 1;
116 static int g_freq_scale = FREQ_SCALE_MHZ;
117 static int g_memory_size = MEMORY_SIZE_8K;
118 static int g_ramsize_triggerbar_addr = 2 * 1024;
119 static int g_triggerbar_addr = 0;
120 static int g_compression = COMPRESSION_NONE;
121 static int g_thresh = 0x31; /* 1.5V */
123 /* Maybe unk specifies an "endpoint" or "register" of sorts. */
124 static int analyzer_write_status(libusb_device_handle *devh, unsigned char unk,
128 return gl_reg_write(devh, START_STATUS, unk << 6 | flags);
132 static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
134 int reg0 = 0, divisor = 0, reg2 = 0;
137 case FREQ_SCALE_MHZ: /* MHz */
138 if (freq >= 100 && freq <= 200) {
144 if (freq >= 50 && freq < 100) {
150 if (freq >= 10 && freq < 50) {
163 if (freq >= 2 && freq < 10) {
179 case FREQ_SCALE_HZ: /* Hz */
180 if (freq >= 500 && freq < 1000) {
186 if (freq >= 300 && freq < 500) {
187 reg0 = freq * 0.005 * 8;
192 if (freq >= 100 && freq < 300) {
193 reg0 = freq * 0.005 * 16;
202 case FREQ_SCALE_KHZ: /* kHz */
203 if (freq >= 500 && freq < 1000) {
209 if (freq >= 100 && freq < 500) {
215 if (freq >= 50 && freq < 100) {
221 if (freq >= 10 && freq < 50) {
233 if (freq >= 2 && freq < 10) {
250 sr_dbg("Setting samplerate regs (freq=%d, scale=%d): "
251 "reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
252 freq, scale, divisor, reg0, 0x02, reg2);
254 if (gl_reg_write(devh, FREQUENCY_REG0, divisor) < 0)
255 return -1; /* Divisor maybe? */
257 if (gl_reg_write(devh, FREQUENCY_REG1, reg0) < 0)
258 return -1; /* 10 / 0.2 */
260 if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
261 return -1; /* Always 2 */
263 if (gl_reg_write(devh, FREQUENCY_REG4, reg2) < 0)
272 * FREQUENCT_REG0 - division factor (?)
273 * FREQUENCT_REG1 - multiplication factor (?)
274 * FREQUENCT_REG4 - clock selection (?)
277 * 0 10MHz 16 1MHz 32 100kHz 48 10kHz 64 1kHz
278 * 1 5MHz 17 500kHz 33 50kHz 49 5kHz 65 500Hz
279 * 2 2.5MHz . . 50 2.5kHz 66 250Hz
283 static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
293 static const struct freq_factor f[] = {
294 { 200, FREQ_SCALE_MHZ, 0, 1, 20 },
295 { 150, FREQ_SCALE_MHZ, 0, 1, 15 },
296 { 100, FREQ_SCALE_MHZ, 0, 1, 10 },
297 { 80, FREQ_SCALE_MHZ, 0, 2, 16 },
298 { 50, FREQ_SCALE_MHZ, 0, 2, 10 },
299 { 25, FREQ_SCALE_MHZ, 1, 5, 25 },
300 { 10, FREQ_SCALE_MHZ, 1, 5, 10 },
301 { 1, FREQ_SCALE_MHZ, 16, 5, 5 },
302 { 800, FREQ_SCALE_KHZ, 17, 5, 8 },
303 { 400, FREQ_SCALE_KHZ, 32, 5, 20 },
304 { 200, FREQ_SCALE_KHZ, 32, 5, 10 },
305 { 100, FREQ_SCALE_KHZ, 32, 5, 5 },
306 { 50, FREQ_SCALE_KHZ, 33, 5, 5 },
307 { 25, FREQ_SCALE_KHZ, 49, 5, 25 },
308 { 5, FREQ_SCALE_KHZ, 50, 5, 10 },
309 { 1, FREQ_SCALE_KHZ, 64, 5, 5 },
310 { 500, FREQ_SCALE_HZ, 64, 10, 5 },
311 { 100, FREQ_SCALE_HZ, 68, 5, 8 },
317 for (i = 0; f[i].freq; i++) {
318 if (scale == f[i].scale && freq == f[i].freq)
324 sr_dbg("Setting samplerate regs (freq=%d, scale=%d): "
325 "reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
326 freq, scale, f[i].div, f[i].mul, 0x02, f[i].sel);
328 if (gl_reg_write(devh, FREQUENCY_REG0, f[i].div) < 0)
331 if (gl_reg_write(devh, FREQUENCY_REG1, f[i].mul) < 0)
334 if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
337 if (gl_reg_write(devh, FREQUENCY_REG4, f[i].sel) < 0)
343 static void __analyzer_set_ramsize_trigger_address(libusb_device_handle *devh,
344 unsigned int address)
346 gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
347 gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
348 gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
351 static void __analyzer_set_triggerbar_address(libusb_device_handle *devh,
352 unsigned int address)
354 gl_reg_write(devh, TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
355 gl_reg_write(devh, TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
356 gl_reg_write(devh, TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
359 static void __analyzer_set_compression(libusb_device_handle *devh,
362 gl_reg_write(devh, COMPRESSION_TYPE0, (type >> 0) & 0xFF);
363 gl_reg_write(devh, COMPRESSION_TYPE1, (type >> 8) & 0xFF);
366 static void __analyzer_set_trigger_count(libusb_device_handle *devh,
369 gl_reg_write(devh, TRIGGER_COUNT0, (count >> 0) & 0xFF);
370 gl_reg_write(devh, TRIGGER_COUNT1, (count >> 8) & 0xFF);
373 static void analyzer_write_enable_insert_data(libusb_device_handle *devh)
375 gl_reg_write(devh, ENABLE_INSERT_DATA0, 0x12);
376 gl_reg_write(devh, ENABLE_INSERT_DATA1, 0x34);
377 gl_reg_write(devh, ENABLE_INSERT_DATA2, 0x56);
378 gl_reg_write(devh, ENABLE_INSERT_DATA3, 0x78);
381 static void analyzer_set_filter(libusb_device_handle *devh)
384 gl_reg_write(devh, FILTER_ENABLE, g_filter_enable);
385 for (i = 0; i < 8; i++)
386 gl_reg_write(devh, FILTER_STATUS + i, g_filter_status[i]);
389 SR_PRIV void analyzer_reset(libusb_device_handle *devh)
391 analyzer_write_status(devh, 3, STATUS_FLAG_NONE); // reset device
392 analyzer_write_status(devh, 3, STATUS_FLAG_RESET); // reset device
395 SR_PRIV void analyzer_initialize(libusb_device_handle *devh)
397 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
398 analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
399 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
402 SR_PRIV void analyzer_wait(libusb_device_handle *devh, int set, int unset)
407 status = gl_reg_read(devh, DEV_STATUS);
408 if ((!set || (status & set)) && ((status & unset) == 0))
413 SR_PRIV void analyzer_read_start(libusb_device_handle *devh)
415 analyzer_write_status(devh, 3, STATUS_FLAG_20 | STATUS_FLAG_READ);
417 /* Prep for bulk reads */
418 gl_reg_read_buf(devh, READ_RAM_STATUS, NULL, 0);
421 SR_PRIV int analyzer_read_data(libusb_device_handle *devh, void *buffer,
424 return gl_read_bulk(devh, buffer, size);
427 SR_PRIV void analyzer_read_stop(libusb_device_handle *devh)
429 analyzer_write_status(devh, 3, STATUS_FLAG_20);
430 analyzer_write_status(devh, 3, STATUS_FLAG_NONE);
433 SR_PRIV void analyzer_start(libusb_device_handle *devh)
435 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
436 analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
437 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
438 analyzer_write_status(devh, 1, STATUS_FLAG_GO);
441 SR_PRIV void analyzer_configure(libusb_device_handle *devh)
445 /* Write_Start_Status */
446 analyzer_write_status(devh, 1, STATUS_FLAG_RESET);
447 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
449 /* Start_Config_Outside_Device ? */
450 analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
451 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
453 /* SetData_To_Frequence_Reg */
454 __analyzer_set_freq(devh, g_freq_value, g_freq_scale);
456 /* SetMemory_Length */
457 gl_reg_write(devh, MEMORY_LENGTH, g_memory_size);
459 /* Sele_Inside_Outside_Clock */
460 gl_reg_write(devh, CLOCK_SOURCE, 0x03);
462 /* Set_Trigger_Status */
463 for (i = 0; i < 9; i++)
464 gl_reg_write(devh, TRIGGER_STATUS0 + i, g_trigger_status[i]);
466 __analyzer_set_trigger_count(devh, g_trigger_count);
468 /* Set_Trigger_Level */
469 gl_reg_write(devh, TRIGGER_LEVEL0, g_thresh);
470 gl_reg_write(devh, TRIGGER_LEVEL1, g_thresh);
471 gl_reg_write(devh, TRIGGER_LEVEL2, g_thresh);
472 gl_reg_write(devh, TRIGGER_LEVEL3, g_thresh);
474 /* Size of actual memory >> 2 */
475 __analyzer_set_ramsize_trigger_address(devh, g_ramsize_triggerbar_addr);
476 __analyzer_set_triggerbar_address(devh, g_triggerbar_addr);
478 /* Set_Dont_Care_TriggerBar */
479 gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x01);
482 analyzer_set_filter(devh);
484 /* Set_Enable_Delay_Time */
485 gl_reg_write(devh, 0x7a, 0x00);
486 gl_reg_write(devh, 0x7b, 0x00);
487 analyzer_write_enable_insert_data(devh);
488 __analyzer_set_compression(devh, g_compression);
491 SR_PRIV int analyzer_add_triggers(const struct sr_dev_inst *sdi)
493 struct dev_context *devc;
494 struct sr_trigger *trigger;
495 struct sr_trigger_stage *stage;
496 struct sr_trigger_match *match;
502 if (!(trigger = sr_session_trigger_get(sdi->session)))
505 for (l = trigger->stages; l; l = l->next) {
507 for (m = stage->matches; m; m = m->next) {
510 if (!match->channel->enabled)
511 /* Ignore disabled channels with a trigger. */
513 channel = match->channel->index;
514 switch (match->match) {
515 case SR_TRIGGER_ZERO:
516 g_trigger_status[channel / 4] |= 2 << (channel % 4 * 2);
518 g_trigger_status[channel / 4] |= 1 << (channel % 4 * 2);
521 sr_err("Unsupported match %d", match->match);
530 SR_PRIV void analyzer_add_filter(int channel, int type)
534 if (type != FILTER_HIGH && type != FILTER_LOW)
536 if ((channel & 0xf) >= 8)
539 if (channel & CHANNEL_A)
541 else if (channel & CHANNEL_B)
543 else if (channel & CHANNEL_C)
545 else if (channel & CHANNEL_D)
550 if ((channel & 0xf) >= 4) {
555 g_filter_status[i] |=
556 1 << ((2 * channel) + (type == FILTER_LOW ? 1 : 0));
561 SR_PRIV void analyzer_set_trigger_count(int count)
563 g_trigger_count = count;
566 SR_PRIV void analyzer_set_freq(int freq, int scale)
569 g_freq_scale = scale;
572 SR_PRIV void analyzer_set_memory_size(unsigned int size)
574 g_memory_size = size;
577 SR_PRIV void analyzer_set_ramsize_trigger_address(unsigned int address)
579 g_ramsize_triggerbar_addr = address;
582 SR_PRIV unsigned int analyzer_get_ramsize_trigger_address(void)
584 return g_ramsize_triggerbar_addr;
587 SR_PRIV void analyzer_set_triggerbar_address(unsigned int address)
589 g_triggerbar_addr = address;
592 SR_PRIV unsigned int analyzer_get_triggerbar_address(void)
594 return g_triggerbar_addr;
597 SR_PRIV unsigned int analyzer_read_status(libusb_device_handle *devh)
599 return gl_reg_read(devh, DEV_STATUS);
602 SR_PRIV unsigned int analyzer_read_id(libusb_device_handle *devh)
604 return gl_reg_read(devh, DEV_ID1) << 8 | gl_reg_read(devh, DEV_ID0);
607 SR_PRIV unsigned int analyzer_get_stop_address(libusb_device_handle *devh)
609 return gl_reg_read(devh, STOP_ADDRESS2) << 16 | gl_reg_read(devh,
610 STOP_ADDRESS1) << 8 | gl_reg_read(devh, STOP_ADDRESS0);
613 SR_PRIV unsigned int analyzer_get_now_address(libusb_device_handle *devh)
615 return gl_reg_read(devh, NOW_ADDRESS2) << 16 | gl_reg_read(devh,
616 NOW_ADDRESS1) << 8 | gl_reg_read(devh, NOW_ADDRESS0);
619 SR_PRIV unsigned int analyzer_get_trigger_address(libusb_device_handle *devh)
621 return gl_reg_read(devh, TRIGGER_ADDRESS2) << 16 | gl_reg_read(devh,
622 TRIGGER_ADDRESS1) << 8 | gl_reg_read(devh, TRIGGER_ADDRESS0);
625 SR_PRIV void analyzer_set_compression(unsigned int type)
627 g_compression = type;
630 SR_PRIV void analyzer_set_voltage_threshold(int thresh)
635 SR_PRIV void analyzer_wait_button(libusb_device_handle *devh)
637 analyzer_wait(devh, STATUS_BUTTON_PRESSED, 0);
640 SR_PRIV void analyzer_wait_data(libusb_device_handle *devh)
642 analyzer_wait(devh, 0, STATUS_BUSY);
645 SR_PRIV int analyzer_decompress(void *input, unsigned int input_len,
646 void *output, unsigned int output_len)
648 unsigned char *in = input;
649 unsigned char *out = output;
650 unsigned int A, B, C, count;
651 unsigned int written = 0;
653 while (input_len > 0) {
659 if (count > output_len)
668 *out++ = 0; /* Channel D */