2 * This file is part of the libsigrok project.
4 * Copyright (C) 2010 Sven Peter <sven@fail0verflow.com>
5 * Copyright (C) 2010 Haxx Enterprises <bushing@gmail.com>
8 * Redistribution and use in source and binary forms, with or
9 * without modification, are permitted provided that the following
12 * * Redistributions of source code must retain the above copyright notice,
13 * this list of conditions and the following disclaimer.
15 * * Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
29 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <libsigrok/libsigrok.h>
35 #include "libsigrok-internal.h"
41 HARD_DATA_CHECK_SUM = 0x00,
49 FREQUENCY_REG0 = 0x30,
57 TRIGGER_STATUS0 = 0x40,
67 TRIGGER_COUNT0 = 0x50,
70 TRIGGER_LEVEL0 = 0x55,
75 RAMSIZE_TRIGGERBAR_ADDRESS0 = 0x60,
76 RAMSIZE_TRIGGERBAR_ADDRESS1,
77 RAMSIZE_TRIGGERBAR_ADDRESS2,
86 ENABLE_DELAY_TIME0 = 0x7a,
89 ENABLE_INSERT_DATA0 = 0x80,
96 TRIGGER_ADDRESS0 = 0x90,
104 STOP_ADDRESS0 = 0x9b,
108 READ_RAM_STATUS = 0xa0,
111 static int g_trigger_status[8] = { 0 };
112 static int g_trigger_edge = 0;
113 static int g_trigger_count = 1;
114 static int g_filter_status[8] = { 0 };
115 static int g_filter_enable = 0;
117 static int g_freq_value = 1;
118 static int g_freq_scale = FREQ_SCALE_MHZ;
119 static int g_memory_size = MEMORY_SIZE_8K;
120 static int g_ramsize_triggerbar_addr = 2 * 1024;
121 static int g_triggerbar_addr = 0;
122 static int g_compression = COMPRESSION_NONE;
123 static int g_thresh = 0x31; /* 1.5V */
125 /* Maybe unk specifies an "endpoint" or "register" of sorts. */
126 static int analyzer_write_status(libusb_device_handle *devh, unsigned char unk,
130 return gl_reg_write(devh, START_STATUS, unk << 6 | flags);
134 static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
136 int reg0 = 0, divisor = 0, reg2 = 0;
139 case FREQ_SCALE_MHZ: /* MHz */
140 if (freq >= 100 && freq <= 200) {
146 if (freq >= 50 && freq < 100) {
152 if (freq >= 10 && freq < 50) {
165 if (freq >= 2 && freq < 10) {
181 case FREQ_SCALE_HZ: /* Hz */
182 if (freq >= 500 && freq < 1000) {
188 if (freq >= 300 && freq < 500) {
189 reg0 = freq * 0.005 * 8;
194 if (freq >= 100 && freq < 300) {
195 reg0 = freq * 0.005 * 16;
204 case FREQ_SCALE_KHZ: /* kHz */
205 if (freq >= 500 && freq < 1000) {
211 if (freq >= 100 && freq < 500) {
217 if (freq >= 50 && freq < 100) {
223 if (freq >= 10 && freq < 50) {
235 if (freq >= 2 && freq < 10) {
252 sr_dbg("Setting samplerate regs (freq=%d, scale=%d): "
253 "reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
254 freq, scale, divisor, reg0, 0x02, reg2);
256 if (gl_reg_write(devh, FREQUENCY_REG0, divisor) < 0)
257 return -1; /* Divisor maybe? */
259 if (gl_reg_write(devh, FREQUENCY_REG1, reg0) < 0)
260 return -1; /* 10 / 0.2 */
262 if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
263 return -1; /* Always 2 */
265 if (gl_reg_write(devh, FREQUENCY_REG4, reg2) < 0)
274 * FREQUENCT_REG0 - division factor (?)
275 * FREQUENCT_REG1 - multiplication factor (?)
276 * FREQUENCT_REG4 - clock selection (?)
279 * 0 10MHz 16 1MHz 32 100kHz 48 10kHz 64 1kHz
280 * 1 5MHz 17 500kHz 33 50kHz 49 5kHz 65 500Hz
281 * 2 2.5MHz . . 50 2.5kHz 66 250Hz
285 static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
295 static const struct freq_factor f[] = {
296 { 200, FREQ_SCALE_MHZ, 0, 1, 20 },
297 { 150, FREQ_SCALE_MHZ, 0, 1, 15 },
298 { 100, FREQ_SCALE_MHZ, 0, 1, 10 },
299 { 80, FREQ_SCALE_MHZ, 0, 2, 16 },
300 { 50, FREQ_SCALE_MHZ, 0, 2, 10 },
301 { 25, FREQ_SCALE_MHZ, 1, 5, 25 },
302 { 10, FREQ_SCALE_MHZ, 1, 5, 10 },
303 { 1, FREQ_SCALE_MHZ, 16, 5, 5 },
304 { 800, FREQ_SCALE_KHZ, 17, 5, 8 },
305 { 400, FREQ_SCALE_KHZ, 32, 5, 20 },
306 { 200, FREQ_SCALE_KHZ, 32, 5, 10 },
307 { 100, FREQ_SCALE_KHZ, 32, 5, 5 },
308 { 50, FREQ_SCALE_KHZ, 33, 5, 5 },
309 { 25, FREQ_SCALE_KHZ, 49, 5, 25 },
310 { 5, FREQ_SCALE_KHZ, 50, 5, 10 },
311 { 1, FREQ_SCALE_KHZ, 64, 5, 5 },
312 { 500, FREQ_SCALE_HZ, 64, 10, 5 },
313 { 100, FREQ_SCALE_HZ, 68, 5, 8 },
319 for (i = 0; f[i].freq; i++) {
320 if (scale == f[i].scale && freq == f[i].freq)
326 sr_dbg("Setting samplerate regs (freq=%d, scale=%d): "
327 "reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
328 freq, scale, f[i].div, f[i].mul, 0x02, f[i].sel);
330 if (gl_reg_write(devh, FREQUENCY_REG0, f[i].div) < 0)
333 if (gl_reg_write(devh, FREQUENCY_REG1, f[i].mul) < 0)
336 if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
339 if (gl_reg_write(devh, FREQUENCY_REG4, f[i].sel) < 0)
345 static void __analyzer_set_ramsize_trigger_address(libusb_device_handle *devh,
346 unsigned int address)
348 gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
349 gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
350 gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
353 static void __analyzer_set_triggerbar_address(libusb_device_handle *devh,
354 unsigned int address)
356 gl_reg_write(devh, TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
357 gl_reg_write(devh, TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
358 gl_reg_write(devh, TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
361 static void __analyzer_set_compression(libusb_device_handle *devh,
364 gl_reg_write(devh, COMPRESSION_TYPE0, (type >> 0) & 0xFF);
365 gl_reg_write(devh, COMPRESSION_TYPE1, (type >> 8) & 0xFF);
368 static void __analyzer_set_trigger_count(libusb_device_handle *devh,
371 gl_reg_write(devh, TRIGGER_COUNT0, (count >> 0) & 0xFF);
372 gl_reg_write(devh, TRIGGER_COUNT1, (count >> 8) & 0xFF);
375 static void analyzer_write_enable_insert_data(libusb_device_handle *devh)
377 gl_reg_write(devh, ENABLE_INSERT_DATA0, 0x12);
378 gl_reg_write(devh, ENABLE_INSERT_DATA1, 0x34);
379 gl_reg_write(devh, ENABLE_INSERT_DATA2, 0x56);
380 gl_reg_write(devh, ENABLE_INSERT_DATA3, 0x78);
383 static void analyzer_set_filter(libusb_device_handle *devh)
386 gl_reg_write(devh, FILTER_ENABLE, g_filter_enable);
387 for (i = 0; i < 8; i++)
388 gl_reg_write(devh, FILTER_STATUS + i, g_filter_status[i]);
391 SR_PRIV void analyzer_reset(libusb_device_handle *devh)
393 analyzer_write_status(devh, 3, STATUS_FLAG_NONE); // reset device
394 analyzer_write_status(devh, 3, STATUS_FLAG_RESET); // reset device
397 SR_PRIV void analyzer_initialize(libusb_device_handle *devh)
399 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
400 analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
401 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
404 SR_PRIV void analyzer_wait(libusb_device_handle *devh, int set, int unset)
409 status = gl_reg_read(devh, DEV_STATUS);
410 if ((!set || (status & set)) && ((status & unset) == 0))
415 SR_PRIV void analyzer_read_start(libusb_device_handle *devh)
417 analyzer_write_status(devh, 3, STATUS_FLAG_20 | STATUS_FLAG_READ);
419 /* Prep for bulk reads */
420 gl_reg_read_buf(devh, READ_RAM_STATUS, NULL, 0);
423 SR_PRIV int analyzer_read_data(libusb_device_handle *devh, void *buffer,
426 return gl_read_bulk(devh, buffer, size);
429 SR_PRIV void analyzer_read_stop(libusb_device_handle *devh)
431 analyzer_write_status(devh, 3, STATUS_FLAG_20);
432 analyzer_write_status(devh, 3, STATUS_FLAG_NONE);
435 SR_PRIV void analyzer_start(libusb_device_handle *devh)
437 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
438 analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
439 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
440 analyzer_write_status(devh, 1, STATUS_FLAG_GO);
443 SR_PRIV void analyzer_configure(libusb_device_handle *devh)
447 /* Write_Start_Status */
448 analyzer_write_status(devh, 1, STATUS_FLAG_RESET);
449 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
451 /* Start_Config_Outside_Device ? */
452 analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
453 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
455 /* SetData_To_Frequence_Reg */
456 __analyzer_set_freq(devh, g_freq_value, g_freq_scale);
458 /* SetMemory_Length */
459 gl_reg_write(devh, MEMORY_LENGTH, g_memory_size);
461 /* Sele_Inside_Outside_Clock */
462 gl_reg_write(devh, CLOCK_SOURCE, 0x03);
464 /* Set_Trigger_Status */
465 for (i = 0; i < 8; i++)
466 gl_reg_write(devh, TRIGGER_STATUS0 + i, g_trigger_status[i]);
467 gl_reg_write(devh, TRIGGER_EDGE, g_trigger_edge);
469 __analyzer_set_trigger_count(devh, g_trigger_count);
471 /* Set_Trigger_Level */
472 gl_reg_write(devh, TRIGGER_LEVEL0, g_thresh);
473 gl_reg_write(devh, TRIGGER_LEVEL1, g_thresh);
474 gl_reg_write(devh, TRIGGER_LEVEL2, g_thresh);
475 gl_reg_write(devh, TRIGGER_LEVEL3, g_thresh);
477 /* Size of actual memory >> 2 */
478 __analyzer_set_ramsize_trigger_address(devh, g_ramsize_triggerbar_addr);
479 __analyzer_set_triggerbar_address(devh, g_triggerbar_addr);
481 /* Set_Dont_Care_TriggerBar */
482 gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x01);
485 analyzer_set_filter(devh);
487 /* Set_Enable_Delay_Time */
488 gl_reg_write(devh, 0x7a, 0x00);
489 gl_reg_write(devh, 0x7b, 0x00);
490 analyzer_write_enable_insert_data(devh);
491 __analyzer_set_compression(devh, g_compression);
494 SR_PRIV int analyzer_add_triggers(const struct sr_dev_inst *sdi)
496 struct dev_context *devc;
497 struct sr_trigger *trigger;
498 struct sr_trigger_stage *stage;
499 struct sr_trigger_match *match;
505 if (!(trigger = sr_session_trigger_get(sdi->session)))
508 memset(g_trigger_status, 0, sizeof(g_trigger_status));
511 for (l = trigger->stages; l; l = l->next) {
513 for (m = stage->matches; m; m = m->next) {
516 if (!match->channel->enabled)
517 /* Ignore disabled channels with a trigger. */
519 channel = match->channel->index;
520 switch (match->match) {
521 case SR_TRIGGER_ZERO:
522 g_trigger_status[channel / 4] |= 2 << (channel % 4 * 2);
525 g_trigger_status[channel / 4] |= 1 << (channel % 4 * 2);
527 case SR_TRIGGER_RISING:
528 g_trigger_edge = 0x40 | (channel & 0x1F);
530 case SR_TRIGGER_FALLING:
531 g_trigger_edge = 0x80 | (channel & 0x1F);
533 case SR_TRIGGER_EDGE:
534 g_trigger_edge = 0xc0 | (channel & 0x1F);
537 sr_err("Unsupported match %d", match->match);
546 SR_PRIV void analyzer_add_filter(int channel, int type)
550 if (type != FILTER_HIGH && type != FILTER_LOW)
552 if ((channel & 0xf) >= 8)
555 if (channel & CHANNEL_A)
557 else if (channel & CHANNEL_B)
559 else if (channel & CHANNEL_C)
561 else if (channel & CHANNEL_D)
566 if ((channel & 0xf) >= 4) {
571 g_filter_status[i] |=
572 1 << ((2 * channel) + (type == FILTER_LOW ? 1 : 0));
577 SR_PRIV void analyzer_set_trigger_count(int count)
579 g_trigger_count = count;
582 SR_PRIV void analyzer_set_freq(int freq, int scale)
585 g_freq_scale = scale;
588 SR_PRIV void analyzer_set_memory_size(unsigned int size)
590 g_memory_size = size;
593 SR_PRIV void analyzer_set_ramsize_trigger_address(unsigned int address)
595 g_ramsize_triggerbar_addr = address;
598 SR_PRIV unsigned int analyzer_get_ramsize_trigger_address(void)
600 return g_ramsize_triggerbar_addr;
603 SR_PRIV void analyzer_set_triggerbar_address(unsigned int address)
605 g_triggerbar_addr = address;
608 SR_PRIV unsigned int analyzer_get_triggerbar_address(void)
610 return g_triggerbar_addr;
613 SR_PRIV unsigned int analyzer_read_status(libusb_device_handle *devh)
615 return gl_reg_read(devh, DEV_STATUS);
618 SR_PRIV unsigned int analyzer_read_id(libusb_device_handle *devh)
620 return gl_reg_read(devh, DEV_ID1) << 8 | gl_reg_read(devh, DEV_ID0);
623 SR_PRIV unsigned int analyzer_get_stop_address(libusb_device_handle *devh)
625 return gl_reg_read(devh, STOP_ADDRESS2) << 16 | gl_reg_read(devh,
626 STOP_ADDRESS1) << 8 | gl_reg_read(devh, STOP_ADDRESS0);
629 SR_PRIV unsigned int analyzer_get_now_address(libusb_device_handle *devh)
631 return gl_reg_read(devh, NOW_ADDRESS2) << 16 | gl_reg_read(devh,
632 NOW_ADDRESS1) << 8 | gl_reg_read(devh, NOW_ADDRESS0);
635 SR_PRIV unsigned int analyzer_get_trigger_address(libusb_device_handle *devh)
637 return gl_reg_read(devh, TRIGGER_ADDRESS2) << 16 | gl_reg_read(devh,
638 TRIGGER_ADDRESS1) << 8 | gl_reg_read(devh, TRIGGER_ADDRESS0);
641 SR_PRIV void analyzer_set_compression(unsigned int type)
643 g_compression = type;
646 SR_PRIV void analyzer_set_voltage_threshold(int thresh)
651 SR_PRIV void analyzer_wait_button(libusb_device_handle *devh)
653 analyzer_wait(devh, STATUS_BUTTON_PRESSED, 0);
656 SR_PRIV void analyzer_wait_data(libusb_device_handle *devh)
658 analyzer_wait(devh, 0, STATUS_BUSY);
661 SR_PRIV int analyzer_decompress(void *input, unsigned int input_len,
662 void *output, unsigned int output_len)
664 unsigned char *in = input;
665 unsigned char *out = output;
666 unsigned int A, B, C, count;
667 unsigned int written = 0;
669 while (input_len > 0) {
675 if (count > output_len)
684 *out++ = 0; /* Channel D */