2 * This file is part of the libsigrok project.
4 * Copyright (C) 2019 Vitaliy Vorobyov
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
25 * Register description (all registers are 32bit):
27 * Rx - means register with index x (register address is x*4)
29 * R0(wr): trigger sel0 (low/high)
30 * R0(rd): n*256 samples (post trigger) captured
32 * R1(wr): trigger sel1 (level/edge)
33 * R1(rd): current sampled value
35 * R2(wr): trigger enable mask
37 * R2(rd): (status register)
38 * b0: 1 - keys entered
40 * b3: 1 - capture done
42 * not configured: B6FF9C97, 12FF9C97, 92FF9C97, 16FF9C97, ...
43 * configured: A5A5A5A0, after enter keys A5A5A5A1
45 * sel1 (one bit per channel):
49 * sel0 (one bit per channel):
50 * 0 - (low level trigger, sel1=0), (falling edge, sel1=1)
51 * 1 - (high level trigger, sel1=0), (raising edge, sel1=1)
53 * mask (one bit per channel):
54 * 0 - disable trigger on channel n
55 * 1 - enable trigger on channel n
57 * R3: upload base address or num samples (0x300000)
60 * 0 - div 1 (no division)
67 * b0: 1 - enable pll mul 2, 0 - disable pll mul 2
72 * b5: ->0->1 upload next data chunk (to pc)
74 * b7: 0 - enable pll mul 1.25, 1 - disable pll mul 1.25
77 * R6: post trigger depth, value x means (x+1)*256 (samples), min value is 1
78 * R7: pre trigger depth, value y means (y+1)*256 (samples), min value is 1
79 * (x+1)*256 + (y+1)*256 <= 64M
81 * R9: PWM1 HI (1 width-1)
82 * R10: PWM1 LO (0 width-1)
84 * R11: PWM2 HI (1 width-1)
85 * R12: PWM2 LO (0 width-1)
117 #define BITSTREAM_NAME "sysclk-sla5032.bit"
118 #define BITSTREAM_MAX_SIZE (512 * 1024) /* Bitstream size limit for safety */
119 #define BITSTREAM_HEADER_SIZE 0x69
120 #define FW_CHUNK_SIZE 250
121 #define XILINX_SYNC_WORD 0xAA995566
123 static int la_write_cmd_buf(const struct sr_usb_dev_inst *usb, uint8_t cmd,
124 unsigned int addr, unsigned int len, const void *data)
130 cmd_pkt = g_try_malloc(len + 10);
141 case CMD_INIT_FW_UPLOAD: /* init firmware upload */
143 case CMD_UPLOAD_FW_CHUNK:
146 memcpy(&cmd_pkt[2], data, len);
148 case CMD_READ_REG: /* read register */
153 case CMD_WRITE_REG: /* write register */
157 memcpy(&cmd_pkt[3], data, len);
159 case CMD_READ_MEM: /* read mem */
160 cmd_pkt[1] = (addr >> 8) & 0xFF;
161 cmd_pkt[2] = addr & 0xFF;
165 case CMD_READ_DATA: /* read samples */
171 ret = libusb_bulk_transfer(usb->devhdl, EP_COMMAND, cmd_pkt, cmd_len,
172 &xfer_len, USB_CMD_TIMEOUT_MS);
174 sr_dbg("Failed to send command %d: %s.",
175 cmd, libusb_error_name(ret));
179 if (xfer_len != cmd_len) {
180 sr_dbg("Invalid send command response of length %d.", xfer_len);
189 static int la_read_reg(const struct sr_usb_dev_inst *usb, unsigned int reg, uint32_t *val)
194 ret = la_write_cmd_buf(usb, CMD_READ_REG, reg * sizeof(uint32_t),
195 sizeof(reply), NULL); /* rd reg */
199 ret = libusb_bulk_transfer(usb->devhdl, EP_REPLY, (uint8_t *)&reply,
200 sizeof(reply), &xfer_len, USB_REPLY_TIMEOUT_MS);
204 if (xfer_len != sizeof(uint32_t)) {
205 sr_dbg("Invalid register read response of length %d.", xfer_len);
209 *val = GUINT32_FROM_BE(reply);
214 static int la_write_reg(const struct sr_usb_dev_inst *usb, unsigned int reg, uint32_t val)
218 val_be = GUINT32_TO_BE(val);
220 return la_write_cmd_buf(usb, CMD_WRITE_REG, reg * sizeof(uint32_t),
221 sizeof(val_be), &val_be); /* wr reg */
224 static int la_read_mem(const struct sr_usb_dev_inst *usb, unsigned int addr, unsigned int len, void *data)
228 ret = la_write_cmd_buf(usb, CMD_READ_MEM, addr, len, NULL); /* rd mem */
233 ret = libusb_bulk_transfer(usb->devhdl, EP_REPLY, (uint8_t *)data,
234 len, &xfer_len, USB_REPLY_TIMEOUT_MS);
235 if (xfer_len != (int)len) {
236 sr_dbg("Invalid memory read response of length %d.", xfer_len);
243 static int la_read_samples(const struct sr_usb_dev_inst *usb, unsigned int addr)
245 return la_write_cmd_buf(usb, CMD_READ_DATA, addr, 0, NULL); /* rd samples */
248 SR_PRIV int sla5032_set_depth(const struct sr_usb_dev_inst *usb, uint32_t pre, uint32_t post)
252 /* (pre + 1)*256 + (post + 1)*256 <= 64*1024*1024 */
253 ret = la_write_reg(usb, 7, pre);
257 return la_write_reg(usb, 6, post);
260 SR_PRIV int sla5032_set_triggers(const struct sr_usb_dev_inst *usb,
261 uint32_t trg_value, uint32_t trg_edge_mask, uint32_t trg_mask)
265 sr_dbg("set trigger: val: %08X, e_mask: %08X, mask: %08X.", trg_value,
266 trg_edge_mask, trg_mask);
268 ret = la_write_reg(usb, 0, trg_value);
272 ret = la_write_reg(usb, 1, trg_edge_mask);
276 return la_write_reg(usb, 2, trg_mask);
279 static int la_set_res_reg_bit(const struct sr_usb_dev_inst *usb,
280 unsigned int reg, unsigned int bit, unsigned int set_bit)
286 ret = la_read_reg(usb, reg, &v);
295 return la_write_reg(usb, reg, v);
298 struct pll_tbl_entry_t
301 uint32_t pll_div_minus_1;
302 unsigned int pll_mul_flags;
306 PLL_MUL2 = 1, /* x2 */
307 PLL_MUL1_25 = 2, /* x1.25 */
310 static const struct pll_tbl_entry_t pll_tbl[] = {
311 { 500000000, 0, PLL_MUL2 | PLL_MUL1_25 }, /* 500M = f*2*1.25/1 */
312 { 400000000, 0, PLL_MUL2 }, /* 400M = f*2/1 */
313 { 250000000, 0, PLL_MUL1_25 }, /* 250M = f*1.25/1 */
314 { 200000000, 0, 0 }, /* 200M = f/1 */
315 { 100000000, 1, 0 }, /* 100M = f/2 */
316 { 50000000, 3, 0 }, /* 50M = f/4 */
317 { 25000000, 7, 0 }, /* 25M = f/8 */
318 { 20000000, 9, 0 }, /* 20M = f/10 */
319 { 10000000, 19, 0 }, /* 10M = f/20 */
320 { 5000000, 39, 0 }, /* 5M = f/40 */
321 { 2000000, 99, 0 }, /* 2M = f/100 */
322 { 1000000, 199, 0 }, /* 1M = f/200 */
323 { 500000, 399, 0 }, /* 500k = f/400 */
324 { 200000, 999, 0 }, /* 200k = f/1000 */
325 { 100000, 1999, 0 }, /* 100k = f/2000 */
326 { 50000, 3999, 0 }, /* 50k = f/4000 */
327 { 20000, 9999, 0 }, /* 20k = f/10000 */
328 { 10000, 19999, 0 }, /* 10k = f/20000 */
329 { 5000, 39999, 0 }, /* 5k = f/40000 */
330 { 2000, 99999, 0 }, /* 2k = f/100000 */
333 SR_PRIV int sla5032_set_samplerate(const struct sr_usb_dev_inst *usb, unsigned int sr)
336 const struct pll_tbl_entry_t *e;
339 for (i = 0; i < (int)ARRAY_SIZE(pll_tbl); i++) {
340 if (sr == pll_tbl[i].sr) {
347 return SR_ERR_SAMPLERATE;
349 sr_dbg("set sample rate: %u.", e->sr);
351 ret = la_write_reg(usb, 4, e->pll_div_minus_1);
355 ret = la_set_res_reg_bit(usb, 5, 0,
356 (e->pll_mul_flags & PLL_MUL2) ? 1 : 0); /* bit0 (1=en_mul2) */
360 return la_set_res_reg_bit(usb, 5, 7,
361 (e->pll_mul_flags & PLL_MUL1_25) ? 0 : 1); /* bit7 (0=en_mul_1.25) */
364 SR_PRIV int sla5032_start_sample(const struct sr_usb_dev_inst *usb)
367 const unsigned int bits[10][2] = {
368 {2, 0}, {3, 0}, {5, 0}, {6, 1}, {1, 1},
369 {1, 0}, {8, 1}, {8, 0}, {6, 1}, {2, 1},
372 ret = la_write_reg(usb, 14, 1);
376 for (size_t i = 0; i < ARRAY_SIZE(bits); i++) {
377 ret = la_set_res_reg_bit(usb, 5, bits[i][0], bits[i][1]);
385 SR_PRIV int sla5032_get_status(const struct sr_usb_dev_inst *usb, uint32_t status[3])
390 ret = la_read_reg(usb, 1, &status[0]);
394 status[1] = 1; /* wait trigger */
396 ret = la_read_reg(usb, 0, &status[2]);
401 ret = la_read_reg(usb, 2, &v);
406 status[1] = 3; /* sample done */
407 sr_dbg("get status, reg2: %08X.", v);
409 status[1] = 2; /* triggered */
415 static int la_read_samples_data(const struct sr_usb_dev_inst *usb, void *buf,
416 unsigned int len, int *xfer_len)
418 return libusb_bulk_transfer(usb->devhdl, EP_DATA, (uint8_t *)buf, len,
419 xfer_len, USB_DATA_TIMEOUT_MS);
422 SR_PRIV int sla5032_read_data_chunk(const struct sr_usb_dev_inst *usb,
423 void *buf, unsigned int len, int *xfer_len)
427 ret = la_read_samples(usb, 3);
431 ret = la_write_reg(usb, 3, 0x300000);
435 ret = la_set_res_reg_bit(usb, 5, 4, 0);
439 ret = la_set_res_reg_bit(usb, 5, 4, 1);
443 return la_read_samples_data(usb, buf, len, xfer_len);
446 SR_PRIV int sla5032_set_read_back(const struct sr_usb_dev_inst *usb)
450 ret = la_write_reg(usb, 5, 0x08);
454 return la_write_reg(usb, 5, 0x28);
457 SR_PRIV int sla5032_set_pwm1(const struct sr_usb_dev_inst* usb, uint32_t hi, uint32_t lo)
461 ret = la_write_reg(usb, 9, hi);
465 return la_write_reg(usb, 10, lo);
468 SR_PRIV int sla5032_set_pwm2(const struct sr_usb_dev_inst* usb, uint32_t hi, uint32_t lo)
472 ret = la_write_reg(usb, 11, hi);
476 return la_write_reg(usb, 12, lo);
479 SR_PRIV int sla5032_write_reg14_zero(const struct sr_usb_dev_inst* usb)
481 return la_write_reg(usb, 14, 0);
484 static int la_cfg_fpga_done(const struct sr_usb_dev_inst *usb, unsigned int addr)
491 memset(done_key, 0, sizeof(done_key));
493 ret = la_read_mem(usb, addr, sizeof(done_key), done_key); /* read key from eeprom */
497 k0 = RL32(done_key); /* 0x641381F6 */
498 k1 = RL32(done_key + 4); /* 0x00000000 */
500 sr_dbg("cfg fpga done, k0: %08X, k1: %08X.", k0, k1);
502 ret = la_write_reg(usb, 16, k0);
506 ret = la_write_reg(usb, 17, k1);
511 ret = la_read_reg(usb, 2, ®2);
513 sr_dbg("cfg fpga done, reg2: %08X.", reg2);
519 * Load a bitstream file into memory. Returns a newly allocated array
520 * consisting of a 32-bit length field followed by the bitstream data.
522 static unsigned char *load_bitstream(struct sr_context *ctx,
523 const char *name, int *length_p)
525 struct sr_resource fw;
526 unsigned char *stream, *fw_data;
527 ssize_t length, count;
529 if (sr_resource_open(ctx, &fw, SR_RESOURCE_FIRMWARE, name) != SR_OK)
532 if (fw.size <= BITSTREAM_HEADER_SIZE || fw.size > BITSTREAM_MAX_SIZE) {
533 sr_err("Refusing to load bitstream of unreasonable size "
534 "(%" PRIu64 " bytes).", fw.size);
535 sr_resource_close(ctx, &fw);
539 stream = g_try_malloc(fw.size);
541 sr_err("Failed to allocate bitstream buffer.");
542 sr_resource_close(ctx, &fw);
546 count = sr_resource_read(ctx, &fw, stream, fw.size);
547 sr_resource_close(ctx, &fw);
549 if (count != (ssize_t)fw.size) {
550 sr_err("Failed to read bitstream '%s'.", name);
555 if (RB32(stream + BITSTREAM_HEADER_SIZE) != XILINX_SYNC_WORD) {
556 sr_err("Invalid bitstream signature.");
561 length = fw.size - BITSTREAM_HEADER_SIZE + 0x100;
562 fw_data = g_try_malloc(length);
564 sr_err("Failed to allocate bitstream aligned buffer.");
568 memset(fw_data, 0xFF, 0x100);
569 memcpy(fw_data + 0x100, stream + BITSTREAM_HEADER_SIZE,
570 fw.size - BITSTREAM_HEADER_SIZE);
578 static int sla5032_is_configured(const struct sr_usb_dev_inst* usb, gboolean *is_configured)
584 ret = la_read_reg(usb, 2, ®2);
586 *is_configured = (reg2 & 0xFFFFFFF1) == 0xA5A5A5A1 ? TRUE : FALSE;
591 /* Load a Binary File from the firmware directory, transfer it to the device. */
592 static int sla5032_send_bitstream(struct sr_context *ctx,
593 const struct sr_usb_dev_inst *usb, const char *name)
595 unsigned char *stream;
596 int ret, length, i, n, m;
599 if (!ctx || !usb || !name)
602 stream = load_bitstream(ctx, name, &length);
606 sr_dbg("Downloading FPGA bitstream '%s'.", name);
609 ret = la_read_reg(usb, 2, ®2);
610 sr_dbg("send bitstream, reg2: %08X.", reg2);
612 /* Transfer the entire bitstream in one URB. */
613 ret = la_write_cmd_buf(usb, CMD_INIT_FW_UPLOAD, 0, 0, NULL); /* init firmware upload */
619 n = length / FW_CHUNK_SIZE;
620 m = length % FW_CHUNK_SIZE;
622 for (i = 0; i < n; i++) {
623 /* upload firmware chunk */
624 ret = la_write_cmd_buf(usb, CMD_UPLOAD_FW_CHUNK, 0,
625 FW_CHUNK_SIZE, &stream[i * FW_CHUNK_SIZE]);
634 /* upload firmware last chunk */
635 ret = la_write_cmd_buf(usb, CMD_UPLOAD_FW_CHUNK, 0, m,
636 &stream[n * FW_CHUNK_SIZE]);
646 la_cfg_fpga_done(usb, 4000);
648 sla5032_write_reg14_zero(usb);
650 sr_dbg("FPGA bitstream download of %d bytes done.", length);
655 /* Select and transfer FPGA bitstream for the current configuration. */
656 SR_PRIV int sla5032_apply_fpga_config(const struct sr_dev_inst *sdi)
658 struct dev_context *devc;
659 struct drv_context *drvc;
661 gboolean is_configured;
664 drvc = sdi->driver->context;
666 if (FPGA_NOCONF != devc->active_fpga_config)
667 return SR_OK; /* No change. */
669 is_configured = FALSE;
670 ret = sla5032_is_configured(sdi->conn, &is_configured);
675 devc->active_fpga_config = FPGA_CONF;
679 sr_dbg("FPGA not configured, send bitstream.");
680 ret = sla5032_send_bitstream(drvc->sr_ctx, sdi->conn, BITSTREAM_NAME);
681 devc->active_fpga_config = (ret == SR_OK) ? FPGA_CONF : FPGA_NOCONF;