2 * This file is part of the libsigrok project.
4 * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
5 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
6 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
27 #include <glib/gstdio.h>
31 #include "libsigrok.h"
32 #include "libsigrok-internal.h"
34 #define FPGA_FIRMWARE_18 FIRMWARE_DIR"/saleae-logic16-fpga-18.bitstream"
35 #define FPGA_FIRMWARE_33 FIRMWARE_DIR"/saleae-logic16-fpga-33.bitstream"
37 #define MAX_SAMPLE_RATE SR_MHZ(100)
38 #define MAX_4CH_SAMPLE_RATE SR_MHZ(50)
39 #define MAX_7CH_SAMPLE_RATE SR_MHZ(40)
40 #define MAX_8CH_SAMPLE_RATE SR_MHZ(32)
41 #define MAX_10CH_SAMPLE_RATE SR_MHZ(25)
42 #define MAX_13CH_SAMPLE_RATE SR_MHZ(16)
44 #define BASE_CLOCK_0_FREQ SR_MHZ(100)
45 #define BASE_CLOCK_1_FREQ SR_MHZ(160)
47 #define COMMAND_START_ACQUISITION 1
48 #define COMMAND_ABORT_ACQUISITION_ASYNC 2
49 #define COMMAND_WRITE_EEPROM 6
50 #define COMMAND_READ_EEPROM 7
51 #define COMMAND_WRITE_LED_TABLE 0x7a
52 #define COMMAND_SET_LED_MODE 0x7b
53 #define COMMAND_RETURN_TO_BOOTLOADER 0x7c
54 #define COMMAND_ABORT_ACQUISITION_SYNC 0x7d
55 #define COMMAND_FPGA_UPLOAD_INIT 0x7e
56 #define COMMAND_FPGA_UPLOAD_SEND_DATA 0x7f
57 #define COMMAND_FPGA_WRITE_REGISTER 0x80
58 #define COMMAND_FPGA_READ_REGISTER 0x81
59 #define COMMAND_GET_REVID 0x82
61 #define WRITE_EEPROM_COOKIE1 0x42
62 #define WRITE_EEPROM_COOKIE2 0x55
63 #define READ_EEPROM_COOKIE1 0x33
64 #define READ_EEPROM_COOKIE2 0x81
65 #define ABORT_ACQUISITION_SYNC_PATTERN 0x55
67 #define MAX_EMPTY_TRANSFERS 64
69 static void encrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt)
71 uint8_t state1 = 0x9b, state2 = 0x54;
75 for (i = 0; i < cnt; i++) {
77 t = (((v ^ state2 ^ 0x2b) - 0x05) ^ 0x35) - 0x39;
78 t = (((t ^ state1 ^ 0x5a) - 0xb0) ^ 0x38) - 0x45;
84 static void decrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt)
86 uint8_t state1 = 0x9b, state2 = 0x54;
90 for (i = 0; i < cnt; i++) {
92 t = (((v + 0x45) ^ 0x38) + 0xb0) ^ 0x5a ^ state1;
93 t = (((t + 0x39) ^ 0x35) + 0x05) ^ 0x2b ^ state2;
99 static int do_ep1_command(const struct sr_dev_inst *sdi,
100 const uint8_t *command, uint8_t cmd_len,
101 uint8_t *reply, uint8_t reply_len)
104 struct sr_usb_dev_inst *usb;
109 if (cmd_len < 1 || cmd_len > 64 || reply_len > 64 ||
110 command == NULL || (reply_len > 0 && reply == NULL))
113 encrypt(buf, command, cmd_len);
115 ret = libusb_bulk_transfer(usb->devhdl, 1, buf, cmd_len, &xfer, 1000);
117 sr_dbg("Failed to send EP1 command 0x%02x: %s.",
118 command[0], libusb_error_name(ret));
121 if (xfer != cmd_len) {
122 sr_dbg("Failed to send EP1 command 0x%02x: incorrect length "
123 "%d != %d.", xfer, cmd_len);
130 ret = libusb_bulk_transfer(usb->devhdl, 0x80 | 1, buf, reply_len,
133 sr_dbg("Failed to receive reply to EP1 command 0x%02x: %s.",
134 command[0], libusb_error_name(ret));
137 if (xfer != reply_len) {
138 sr_dbg("Failed to receive reply to EP1 command 0x%02x: "
139 "incorrect length %d != %d.", xfer, reply_len);
143 decrypt(reply, buf, reply_len);
148 static int read_eeprom(const struct sr_dev_inst *sdi,
149 uint8_t address, uint8_t length, uint8_t *buf)
151 uint8_t command[5] = {
159 return do_ep1_command(sdi, command, 5, buf, length);
162 static int upload_led_table(const struct sr_dev_inst *sdi,
163 const uint8_t *table, uint8_t offset, uint8_t cnt)
165 uint8_t chunk, command[64];
168 if (cnt < 1 || cnt + offset > 64 || table == NULL)
172 chunk = (cnt > 32 ? 32 : cnt);
174 command[0] = COMMAND_WRITE_LED_TABLE;
177 memcpy(command + 3, table, chunk);
179 ret = do_ep1_command(sdi, command, 3 + chunk, NULL, 0);
191 static int set_led_mode(const struct sr_dev_inst *sdi,
192 uint8_t animate, uint16_t t2reload, uint8_t div,
195 uint8_t command[6] = {
196 COMMAND_SET_LED_MODE,
204 return do_ep1_command(sdi, command, 6, NULL, 0);
207 static int read_fpga_register(const struct sr_dev_inst *sdi,
208 uint8_t address, uint8_t *value)
210 uint8_t command[3] = {
211 COMMAND_FPGA_READ_REGISTER,
216 return do_ep1_command(sdi, command, 3, value, 1);
219 static int write_fpga_registers(const struct sr_dev_inst *sdi,
220 uint8_t (*regs)[2], uint8_t cnt)
225 if (cnt < 1 || cnt > 31)
228 command[0] = COMMAND_FPGA_WRITE_REGISTER;
230 for (i = 0; i < cnt; i++) {
231 command[2 + 2 * i] = regs[i][0];
232 command[3 + 2 * i] = regs[i][1];
235 return do_ep1_command(sdi, command, 2 * (cnt + 1), NULL, 0);
238 static int write_fpga_register(const struct sr_dev_inst *sdi,
239 uint8_t address, uint8_t value)
241 uint8_t regs[2] = { address, value };
243 return write_fpga_registers(sdi, ®s, 1);
246 static uint8_t map_eeprom_data(uint8_t v)
248 return (((v ^ 0x80) + 0x44) ^ 0xd5) + 0x69;
251 static int prime_fpga(const struct sr_dev_inst *sdi)
253 uint8_t eeprom_data[16];
254 uint8_t old_reg_10, version;
255 uint8_t regs[8][2] = {
267 if ((ret = read_eeprom(sdi, 16, 16, eeprom_data)) != SR_OK)
270 if ((ret = read_fpga_register(sdi, 10, &old_reg_10)) != SR_OK)
273 regs[0][1] = (old_reg_10 &= 0x7f);
274 regs[1][1] |= old_reg_10;
275 regs[3][1] |= old_reg_10;
276 regs[4][1] |= old_reg_10;
278 for (i = 0; i < 16; i++) {
279 regs[2][1] = eeprom_data[i];
280 regs[5][1] = map_eeprom_data(eeprom_data[i]);
282 ret = write_fpga_registers(sdi, ®s[2], 6);
284 ret = write_fpga_registers(sdi, ®s[0], 8);
289 if ((ret = write_fpga_register(sdi, 10, old_reg_10)) != SR_OK)
292 if ((ret = read_fpga_register(sdi, 0, &version)) != SR_OK)
295 if (version != 0x10) {
296 sr_err("Invalid FPGA bitstream version: 0x%02x != 0x10.", version);
303 static void make_heartbeat(uint8_t *table, int len)
307 memset(table, 0, len);
309 for (i = 0; i < 2; i++)
310 for (j = 0; j < len; j++)
311 *table++ = sin(j * M_PI / len) * 255;
314 static int configure_led(const struct sr_dev_inst *sdi)
319 make_heartbeat(table, 64);
320 if ((ret = upload_led_table(sdi, table, 0, 64)) != SR_OK)
323 return set_led_mode(sdi, 1, 6250, 0, 1);
326 static int upload_fpga_bitstream(const struct sr_dev_inst *sdi,
327 enum voltage_range vrange)
329 struct dev_context *devc;
330 int offset, chunksize, ret;
331 const char *filename;
332 uint8_t len, buf[256 * 62], command[64];
337 if (devc->cur_voltage_range == vrange)
341 case VOLTAGE_RANGE_18_33_V:
342 filename = FPGA_FIRMWARE_18;
344 case VOLTAGE_RANGE_5_V:
345 filename = FPGA_FIRMWARE_33;
348 sr_err("Unsupported voltage range.");
352 sr_info("Uploading FPGA bitstream at %s.", filename);
353 if ((fw = g_fopen(filename, "rb")) == NULL) {
354 sr_err("Unable to open bitstream file %s for reading: %s.",
355 filename, strerror(errno));
359 buf[0] = COMMAND_FPGA_UPLOAD_INIT;
360 if ((ret = do_ep1_command(sdi, buf, 1, NULL, 0)) != SR_OK) {
366 chunksize = fread(buf, 1, sizeof(buf), fw);
370 for (offset = 0; offset < chunksize; offset += 62) {
371 len = (offset + 62 > chunksize ?
372 chunksize - offset : 62);
373 command[0] = COMMAND_FPGA_UPLOAD_SEND_DATA;
375 memcpy(command + 2, buf + offset, len);
376 ret = do_ep1_command(sdi, command, len + 2, NULL, 0);
383 sr_info("Uploaded %d bytes.", chunksize);
386 sr_info("FPGA bitstream upload done.");
388 if ((ret = prime_fpga(sdi)) != SR_OK)
391 if ((ret = configure_led(sdi)) != SR_OK)
394 devc->cur_voltage_range = vrange;
398 static int abort_acquisition_sync(const struct sr_dev_inst *sdi)
400 static const uint8_t command[2] = {
401 COMMAND_ABORT_ACQUISITION_SYNC,
402 ABORT_ACQUISITION_SYNC_PATTERN,
404 uint8_t reply, expected_reply;
407 if ((ret = do_ep1_command(sdi, command, 2, &reply, 1)) != SR_OK)
410 expected_reply = ~command[1];
411 if (reply != expected_reply) {
412 sr_err("Invalid response for abort acquisition command: "
413 "0x%02x != 0x%02x.", reply, expected_reply);
420 SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
421 uint64_t samplerate, uint16_t channels)
423 uint8_t clock_select, reg1, reg10;
425 int i, ret, nchan = 0;
426 struct dev_context *devc;
430 if (samplerate == 0 || samplerate > MAX_SAMPLE_RATE) {
431 sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate);
435 if (BASE_CLOCK_0_FREQ % samplerate == 0 &&
436 (div = BASE_CLOCK_0_FREQ / samplerate) <= 256) {
438 } else if (BASE_CLOCK_1_FREQ % samplerate == 0 &&
439 (div = BASE_CLOCK_1_FREQ / samplerate) <= 256) {
442 sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate);
446 for (i = 0; i < 16; i++)
447 if (channels & (1U << i))
450 if ((nchan >= 13 && samplerate > MAX_13CH_SAMPLE_RATE) ||
451 (nchan >= 10 && samplerate > MAX_10CH_SAMPLE_RATE) ||
452 (nchan >= 8 && samplerate > MAX_8CH_SAMPLE_RATE) ||
453 (nchan >= 7 && samplerate > MAX_7CH_SAMPLE_RATE) ||
454 (nchan >= 4 && samplerate > MAX_4CH_SAMPLE_RATE)) {
455 sr_err("Unable to sample at %" PRIu64 "Hz "
456 "with this many channels.", samplerate);
460 ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range);
464 if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK)
467 /* Ignore FIFO overflow on previous capture */
471 sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x08.", reg1);
475 if ((ret = write_fpga_register(sdi, 1, 0x40)) != SR_OK)
478 if ((ret = write_fpga_register(sdi, 10, clock_select)) != SR_OK)
481 if ((ret = write_fpga_register(sdi, 4, (uint8_t)(div - 1))) != SR_OK)
484 if ((ret = write_fpga_register(sdi, 2, (uint8_t)(channels & 0xff))) != SR_OK)
487 if ((ret = write_fpga_register(sdi, 3, (uint8_t)(channels >> 8))) != SR_OK)
490 if ((ret = write_fpga_register(sdi, 1, 0x42)) != SR_OK)
493 if ((ret = write_fpga_register(sdi, 1, 0x40)) != SR_OK)
496 if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK)
500 sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x48.", reg1);
504 if ((ret = read_fpga_register(sdi, 10, ®10)) != SR_OK)
507 if (reg10 != clock_select) {
508 sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x%02x.",
509 reg10, clock_select);
516 SR_PRIV int logic16_start_acquisition(const struct sr_dev_inst *sdi)
518 static const uint8_t command[1] = {
519 COMMAND_START_ACQUISITION,
523 if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK)
526 return write_fpga_register(sdi, 1, 0x41);
529 SR_PRIV int logic16_abort_acquisition(const struct sr_dev_inst *sdi)
531 static const uint8_t command[1] = {
532 COMMAND_ABORT_ACQUISITION_ASYNC,
535 uint8_t reg1, reg8, reg9;
537 if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK)
540 if ((ret = write_fpga_register(sdi, 1, 0x00)) != SR_OK)
543 if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK)
546 if ((reg1 & ~0x20) != 0x08) {
547 sr_dbg("Invalid state at acquisition stop: 0x%02x != 0x08.", reg1 & ~0x20);
551 if ((ret = read_fpga_register(sdi, 8, ®8)) != SR_OK)
554 if ((ret = read_fpga_register(sdi, 9, ®9)) != SR_OK)
558 sr_warn("FIFO overflow, capture data may be truncated.");
565 SR_PRIV int logic16_init_device(const struct sr_dev_inst *sdi)
567 struct dev_context *devc;
572 devc->cur_voltage_range = VOLTAGE_RANGE_UNKNOWN;
574 if ((ret = abort_acquisition_sync(sdi)) != SR_OK)
577 if ((ret = read_eeprom(sdi, 8, 8, devc->eeprom_data)) != SR_OK)
580 ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range);
587 static void finish_acquisition(struct sr_dev_inst *sdi)
589 struct sr_datafeed_packet packet;
590 struct dev_context *devc;
594 /* Terminate session. */
595 packet.type = SR_DF_END;
596 sr_session_send(devc->cb_data, &packet);
598 /* Remove fds from polling. */
599 usb_source_remove(sdi->session, devc->ctx);
601 devc->num_transfers = 0;
602 g_free(devc->transfers);
603 g_free(devc->convbuffer);
605 soft_trigger_logic_free(devc->stl);
610 static void free_transfer(struct libusb_transfer *transfer)
612 struct sr_dev_inst *sdi;
613 struct dev_context *devc;
616 sdi = transfer->user_data;
619 g_free(transfer->buffer);
620 transfer->buffer = NULL;
621 libusb_free_transfer(transfer);
623 for (i = 0; i < devc->num_transfers; i++) {
624 if (devc->transfers[i] == transfer) {
625 devc->transfers[i] = NULL;
630 devc->submitted_transfers--;
631 if (devc->submitted_transfers == 0)
632 finish_acquisition(sdi);
635 static void resubmit_transfer(struct libusb_transfer *transfer)
639 if ((ret = libusb_submit_transfer(transfer)) == LIBUSB_SUCCESS)
642 free_transfer(transfer);
643 /* TODO: Stop session? */
645 sr_err("%s: %s", __func__, libusb_error_name(ret));
648 static size_t convert_sample_data(struct dev_context *devc,
649 uint8_t *dest, size_t destcnt, const uint8_t *src, size_t srccnt)
651 uint16_t *channel_data;
654 uint16_t sample, channel_mask;
658 channel_data = devc->channel_data;
659 cur_channel = devc->cur_channel;
662 sample = src[0] | (src[1] << 8);
665 channel_mask = devc->channel_masks[cur_channel];
667 for (i = 15; i >= 0; --i, sample >>= 1)
669 channel_data[i] |= channel_mask;
671 if (++cur_channel == devc->num_channels) {
673 if (destcnt < 16 * 2) {
674 sr_err("Conversion buffer too small!");
677 memcpy(dest, channel_data, 16 * 2);
678 memset(channel_data, 0, 16 * 2);
685 devc->cur_channel = cur_channel;
690 SR_PRIV void logic16_receive_transfer(struct libusb_transfer *transfer)
692 gboolean packet_has_error = FALSE;
693 struct sr_datafeed_packet packet;
694 struct sr_datafeed_logic logic;
695 struct sr_dev_inst *sdi;
696 struct dev_context *devc;
697 size_t new_samples, num_samples;
700 sdi = transfer->user_data;
704 * If acquisition has already ended, just free any queued up
705 * transfer that come in.
707 if (devc->sent_samples < 0) {
708 free_transfer(transfer);
712 sr_info("receive_transfer(): status %d received %d bytes.",
713 transfer->status, transfer->actual_length);
715 switch (transfer->status) {
716 case LIBUSB_TRANSFER_NO_DEVICE:
717 devc->sent_samples = -2;
718 free_transfer(transfer);
720 case LIBUSB_TRANSFER_COMPLETED:
721 case LIBUSB_TRANSFER_TIMED_OUT: /* We may have received some data though. */
724 packet_has_error = TRUE;
728 if (transfer->actual_length & 1) {
729 sr_err("Got an odd number of bytes from the device. "
730 "This should not happen.");
731 /* Bail out right away. */
732 packet_has_error = TRUE;
733 devc->empty_transfer_count = MAX_EMPTY_TRANSFERS;
736 if (transfer->actual_length == 0 || packet_has_error) {
737 devc->empty_transfer_count++;
738 if (devc->empty_transfer_count > MAX_EMPTY_TRANSFERS) {
740 * The FX2 gave up. End the acquisition, the frontend
741 * will work out that the samplecount is short.
743 devc->sent_samples = -2;
744 free_transfer(transfer);
746 resubmit_transfer(transfer);
750 devc->empty_transfer_count = 0;
753 new_samples = convert_sample_data(devc, devc->convbuffer,
754 devc->convbuffer_size, transfer->buffer, transfer->actual_length);
756 if (new_samples > 0) {
757 if (devc->trigger_fired) {
758 /* Send the incoming transfer to the session bus. */
759 packet.type = SR_DF_LOGIC;
760 packet.payload = &logic;
761 if (devc->limit_samples &&
762 new_samples > devc->limit_samples - devc->sent_samples)
763 new_samples = devc->limit_samples - devc->sent_samples;
764 logic.length = new_samples * 2;
766 logic.data = devc->convbuffer;
767 sr_session_send(devc->cb_data, &packet);
768 devc->sent_samples += new_samples;
770 trigger_offset = soft_trigger_logic_check(devc->stl,
771 devc->convbuffer, new_samples * 2);
772 if (trigger_offset > -1) {
773 packet.type = SR_DF_LOGIC;
774 packet.payload = &logic;
775 num_samples = new_samples - trigger_offset;
776 if (devc->limit_samples &&
777 num_samples > devc->limit_samples - devc->sent_samples)
778 num_samples = devc->limit_samples - devc->sent_samples;
779 logic.length = num_samples * 2;
781 logic.data = devc->convbuffer + trigger_offset * 2;
782 sr_session_send(devc->cb_data, &packet);
783 devc->sent_samples += num_samples;
785 devc->trigger_fired = TRUE;
789 if (devc->limit_samples &&
790 (uint64_t)devc->sent_samples >= devc->limit_samples) {
791 devc->sent_samples = -2;
792 free_transfer(transfer);
797 resubmit_transfer(transfer);