2 * This file is part of the libsigrok project.
4 * Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com>
5 * Copyright (C) 2012 Renato Caldas <rmsc@fe.up.pt>
6 * Copyright (C) 2013 Lior Elazary <lelazary@yahoo.com>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
26 #define mso_trans(a, v) \
27 (((v) & 0x3f) | (((v) & 0xc0) << 6) | (((a) & 0xf) << 8) | \
28 ((~(v) & 0x20) << 1) | ((~(v) & 0x80) << 7))
30 static const char mso_head[] = { 0x40, 0x4c, 0x44, 0x53, 0x7e };
31 static const char mso_foot[] = { 0x7e };
33 extern SR_PRIV struct sr_dev_driver link_mso19_driver_info;
35 SR_PRIV int mso_send_control_message(struct sr_serial_dev_inst *serial,
36 uint16_t payload[], int n)
38 int i, w, ret, s = n * 2 + sizeof(mso_head) + sizeof(mso_foot);
49 memcpy(p, mso_head, sizeof(mso_head));
50 p += sizeof(mso_head);
52 for (i = 0; i < n; i++) {
53 *(uint16_t *) p = g_htons(payload[i]);
56 memcpy(p, mso_foot, sizeof(mso_foot));
60 ret = serial_write(serial, buf + w, s - w);
74 SR_PRIV int mso_configure_trigger(const struct sr_dev_inst *sdi)
76 struct dev_context *devc = sdi->priv;
77 uint16_t threshold_value = mso_calc_raw_from_mv(devc);
79 threshold_value = 0x153C;
80 uint8_t trigger_config = 0;
82 if (devc->trigger_slope)
83 trigger_config |= 0x04; //Trigger on falling edge
85 switch (devc->trigger_outsrc) {
87 trigger_config |= 0x00; //Trigger pulse output
90 trigger_config |= 0x08; //PWM DAC from the pattern generator buffer
93 trigger_config |= 0x18; //White noise
97 switch (devc->trigger_chan) {
99 trigger_config |= 0x00; //DSO level trigger //b00000000
102 trigger_config |= 0x20; //DSO level trigger & width < trigger_width
105 trigger_config |= 0x40; //DSO level trigger & width >= trigger_width
108 trigger_config |= 0x60; //LA combination trigger
112 //Last bit of trigger config reg 4 needs to be 1 for trigger enable,
113 //otherwise the trigger is not enabled
114 if (devc->use_trigger)
115 trigger_config |= 0x80;
118 ops[0] = mso_trans(3, threshold_value & 0xff);
119 //The trigger_config also holds the 2 MSB bits from the threshold value
120 ops[1] = mso_trans(4, trigger_config | ((threshold_value >> 8) & 0x03));
121 ops[2] = mso_trans(5, devc->la_trigger);
122 ops[3] = mso_trans(6, devc->la_trigger_mask);
123 ops[4] = mso_trans(7, devc->trigger_holdoff[0]);
124 ops[5] = mso_trans(8, devc->trigger_holdoff[1]);
126 ops[6] = mso_trans(11,
127 devc->dso_trigger_width /
128 SR_HZ_TO_NS(devc->cur_rate));
130 /* Select the SPI/I2C trigger config bank */
131 ops[7] = mso_trans(REG_CTL2, (devc->ctlbase2 | BITS_CTL2_BANK(2)));
132 /* Configure the SPI/I2C protocol trigger */
133 ops[8] = mso_trans(REG_PT_WORD(0), devc->protocol_trigger.word[0]);
134 ops[9] = mso_trans(REG_PT_WORD(1), devc->protocol_trigger.word[1]);
135 ops[10] = mso_trans(REG_PT_WORD(2), devc->protocol_trigger.word[2]);
136 ops[11] = mso_trans(REG_PT_WORD(3), devc->protocol_trigger.word[3]);
137 ops[12] = mso_trans(REG_PT_MASK(0), devc->protocol_trigger.mask[0]);
138 ops[13] = mso_trans(REG_PT_MASK(1), devc->protocol_trigger.mask[1]);
139 ops[14] = mso_trans(REG_PT_MASK(2), devc->protocol_trigger.mask[2]);
140 ops[15] = mso_trans(REG_PT_MASK(3), devc->protocol_trigger.mask[3]);
141 ops[16] = mso_trans(REG_PT_SPIMODE, devc->protocol_trigger.spimode);
142 /* Select the default config bank */
143 ops[17] = mso_trans(REG_CTL2, devc->ctlbase2);
145 return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
148 SR_PRIV int mso_configure_threshold_level(const struct sr_dev_inst *sdi)
150 struct dev_context *devc = sdi->priv;
152 return mso_dac_out(sdi, la_threshold_map[devc->la_threshold]);
155 SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi)
157 uint16_t ops[] = { mso_trans(REG_BUFFER, 0) };
158 struct dev_context *devc = sdi->priv;
160 sr_dbg("Requesting buffer dump.");
161 return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
164 SR_PRIV int mso_arm(const struct sr_dev_inst *sdi)
166 struct dev_context *devc = sdi->priv;
168 mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETFSM),
169 mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_ARM),
170 mso_trans(REG_CTL1, devc->ctlbase1),
173 sr_dbg("Requesting trigger arm.");
174 return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
177 SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi)
179 struct dev_context *devc = sdi->priv;
181 mso_trans(REG_CTL1, devc->ctlbase1 | 8),
182 mso_trans(REG_CTL1, devc->ctlbase1),
185 sr_dbg("Requesting forced capture.");
186 return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
189 SR_PRIV int mso_dac_out(const struct sr_dev_inst *sdi, uint16_t val)
191 struct dev_context *devc = sdi->priv;
193 mso_trans(REG_DAC1, (val >> 8) & 0xff),
194 mso_trans(REG_DAC2, val & 0xff),
195 mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETADC),
198 sr_dbg("Setting dac word to 0x%x.", val);
199 return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
202 SR_PRIV uint16_t mso_calc_raw_from_mv(struct dev_context *devc)
204 return (uint16_t) (0x200 -
205 ((devc->dso_trigger_voltage / devc->dso_probe_attn) /
209 SR_PRIV int mso_parse_serial(const char *iSerial, const char *iProduct,
210 struct dev_context *devc)
212 unsigned int u1, u2, u3, u4, u5, u6;
216 /* FIXME: This code is in the original app, but I think its
217 * used only for the GUI */
218 /* if (strstr(iProduct, "REV_02") || strstr(iProduct, "REV_03"))
219 devc->num_sample_rates = 0x16;
221 devc->num_sample_rates = 0x10; */
224 if (iSerial[0] != '4' || sscanf(iSerial, "%5u%3u%3u%1u%1u%6u",
225 &u1, &u2, &u3, &u4, &u5, &u6) != 6)
229 devc->vbit = u1 / 10000;
231 devc->vbit = 4.19195;
232 devc->dac_offset = u2;
233 if (devc->dac_offset == 0)
234 devc->dac_offset = 0x1ff;
235 devc->offset_range = u3;
236 if (devc->offset_range == 0)
237 devc->offset_range = 0x17d;
240 * FIXME: There is more code on the original software to handle
241 * bigger iSerial strings, but as I can't test on my device
242 * I will not implement it yet
248 SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi)
250 struct dev_context *devc = sdi->priv;
253 ops[0] = mso_trans(REG_CTL1, (devc->ctlbase1 | BIT_CTL1_RESETADC));
254 ops[1] = mso_trans(REG_CTL1, devc->ctlbase1);
255 devc->ctlbase1 |= BIT_CTL1_ADC_UNKNOWN4;
257 sr_dbg("Requesting ADC reset.");
258 return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
261 SR_PRIV int mso_reset_fsm(struct sr_dev_inst *sdi)
263 struct dev_context *devc = sdi->priv;
266 devc->ctlbase1 |= BIT_CTL1_RESETFSM;
267 ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);
269 sr_dbg("Requesting ADC reset.");
270 return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
273 SR_PRIV int mso_toggle_led(struct sr_dev_inst *sdi, int state)
275 struct dev_context *devc = sdi->priv;
278 devc->ctlbase1 &= ~BIT_CTL1_LED;
280 devc->ctlbase1 |= BIT_CTL1_LED;
281 ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);
283 sr_dbg("Requesting LED toggle.");
284 return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
287 SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi)
289 struct sr_datafeed_packet packet;
290 struct dev_context *devc;
293 serial_source_remove(sdi->session, devc->serial);
295 /* Terminate session */
296 packet.type = SR_DF_END;
297 sr_session_send(sdi, &packet);
300 SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val)
303 mso_trans(REG_CLKRATE1, (val >> 8) & 0xff),
304 mso_trans(REG_CLKRATE2, val & 0xff),
307 sr_dbg("Setting clkrate word to 0x%x.", val);
308 return mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
311 SR_PRIV int mso_configure_rate(const struct sr_dev_inst *sdi, uint32_t rate)
313 struct dev_context *devc = sdi->priv;
317 for (i = 0; i < ARRAY_SIZE(rate_map); i++) {
318 if (rate_map[i].rate == rate) {
319 devc->ctlbase2 = rate_map[i].slowmode;
320 ret = mso_clkrate_out(devc->serial, rate_map[i].val);
322 devc->cur_rate = rate;
328 sr_err("Unsupported rate.");
333 SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst *serial, uint8_t *info)
335 uint16_t ops[] = { mso_trans(REG_TRIGGER, 0) };
338 sr_dbg("Requesting trigger state.");
339 ret = mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
340 if (!info || ret != SR_OK)
344 if (serial_read(serial, &buf, 1) != 1) /* FIXME: Need timeout */
349 sr_dbg("Trigger state is: 0x%x.", *info);
353 SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data)
355 struct sr_datafeed_packet packet;
356 struct sr_datafeed_logic logic;
357 struct sr_dev_inst *sdi;
361 struct drv_context *drvc = di->context;
363 /* Find this device's devc struct by its fd. */
364 struct dev_context *devc = NULL;
365 for (l = drvc->instances; l; l = l->next) {
368 if (devc->serial->fd == fd)
373 /* Shouldn't happen. */
379 size_t s = serial_read(devc->serial, in, sizeof(in));
384 /* Check if we triggered, then send a command that we are ready
385 * to read the data */
386 if (devc->trigger_state != MSO_TRIGGER_DATAREADY) {
387 devc->trigger_state = in[0];
388 if (devc->trigger_state == MSO_TRIGGER_DATAREADY) {
389 mso_read_buffer(sdi);
392 mso_check_trigger(devc->serial, NULL);
397 /* the hardware always dumps 1024 samples, 24bits each */
398 if (devc->buffer_n < 3072) {
399 memcpy(devc->buffer + devc->buffer_n, in, s);
402 if (devc->buffer_n < 3072)
405 /* do the conversion */
406 uint8_t logic_out[1024];
407 double analog_out[1024];
408 for (i = 0; i < 1024; i++) {
409 /* FIXME: Need to do conversion to mV */
410 analog_out[i] = (devc->buffer[i * 3] & 0x3f) |
411 ((devc->buffer[i * 3 + 1] & 0xf) << 6);
413 logic_out[i] = ((devc->buffer[i * 3 + 1] & 0x30) >> 4) |
414 ((devc->buffer[i * 3 + 2] & 0x3f) << 2);
417 packet.type = SR_DF_LOGIC;
418 packet.payload = &logic;
421 logic.data = logic_out;
422 sr_session_send(cb_data, &packet);
424 devc->num_samples += 1024;
426 if (devc->limit_samples && devc->num_samples >= devc->limit_samples) {
427 sr_info("Requested number of samples reached.");
428 sdi->driver->dev_acquisition_stop(sdi, cb_data);
434 SR_PRIV int mso_configure_channels(const struct sr_dev_inst *sdi)
436 struct dev_context *devc;
437 struct sr_channel *ch;
443 devc->la_trigger_mask = 0xFF; //the mask for the LA_TRIGGER (bits set to 0 matter, those set to 1 are ignored).
444 devc->la_trigger = 0x00; //The value of the LA byte that generates a trigger event (in that mode).
445 devc->dso_trigger_voltage = 3;
446 devc->dso_probe_attn = 1;
447 devc->trigger_outsrc = 0;
448 devc->trigger_chan = 3; //LA combination trigger
449 devc->use_trigger = FALSE;
451 for (l = sdi->channels; l; l = l->next) {
452 ch = (struct sr_channel *)l->data;
453 if (ch->enabled == FALSE)
456 int channel_bit = 1 << (ch->index);
460 devc->use_trigger = TRUE;
461 //Configure trigger mask and value.
462 for (tc = ch->trigger; *tc; tc++) {
463 devc->la_trigger_mask &= ~channel_bit;
465 devc->la_trigger |= channel_bit;