2 * This file is part of the libsigrok project.
4 * Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com>
5 * Copyright (C) 2012 Renato Caldas <rmsc@fe.up.pt>
6 * Copyright (C) 2013 Lior Elazary <lelazary@yahoo.com>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
25 #define mso_trans(a, v) \
26 (((v) & 0x3f) | (((v) & 0xc0) << 6) | (((a) & 0xf) << 8) | \
27 ((~(v) & 0x20) << 1) | ((~(v) & 0x80) << 7))
29 static const char mso_head[] = { 0x40, 0x4c, 0x44, 0x53, 0x7e };
30 static const char mso_foot[] = { 0x7e };
32 extern SR_PRIV struct sr_dev_driver link_mso19_driver_info;
34 SR_PRIV int mso_send_control_message(struct sr_serial_dev_inst *serial,
35 uint16_t payload[], int n)
37 int i, w, ret, s = n * 2 + sizeof(mso_head) + sizeof(mso_foot);
48 memcpy(p, mso_head, sizeof(mso_head));
49 p += sizeof(mso_head);
51 for (i = 0; i < n; i++) {
52 *(uint16_t *) p = g_htons(payload[i]);
55 memcpy(p, mso_foot, sizeof(mso_foot));
59 ret = serial_write(serial, buf + w, s - w);
73 SR_PRIV int mso_configure_trigger(const struct sr_dev_inst *sdi)
75 struct dev_context *devc = sdi->priv;
76 uint16_t threshold_value = mso_calc_raw_from_mv(devc);
78 threshold_value = 0x153C;
79 uint8_t trigger_config = 0;
81 if (devc->trigger_slope)
82 trigger_config |= 0x04; //Trigger on falling edge
84 switch (devc->trigger_outsrc) {
86 trigger_config |= 0x00; //Trigger pulse output
89 trigger_config |= 0x08; //PWM DAC from the pattern generator buffer
92 trigger_config |= 0x18; //White noise
96 switch (devc->trigger_chan) {
98 trigger_config |= 0x00; //DSO level trigger //b00000000
101 trigger_config |= 0x20; //DSO level trigger & width < trigger_width
104 trigger_config |= 0x40; //DSO level trigger & width >= trigger_width
107 trigger_config |= 0x60; //LA combination trigger
111 //Last bit of trigger config reg 4 needs to be 1 for trigger enable,
112 //otherwise the trigger is not enabled
113 if (devc->use_trigger)
114 trigger_config |= 0x80;
117 ops[0] = mso_trans(3, threshold_value & 0xff);
118 //The trigger_config also holds the 2 MSB bits from the threshold value
119 ops[1] = mso_trans(4, trigger_config | ((threshold_value >> 8) & 0x03));
120 ops[2] = mso_trans(5, devc->la_trigger);
121 ops[3] = mso_trans(6, devc->la_trigger_mask);
122 ops[4] = mso_trans(7, devc->trigger_holdoff[0]);
123 ops[5] = mso_trans(8, devc->trigger_holdoff[1]);
125 ops[6] = mso_trans(11,
126 devc->dso_trigger_width /
127 SR_HZ_TO_NS(devc->cur_rate));
129 /* Select the SPI/I2C trigger config bank */
130 ops[7] = mso_trans(REG_CTL2, (devc->ctlbase2 | BITS_CTL2_BANK(2)));
131 /* Configure the SPI/I2C protocol trigger */
132 ops[8] = mso_trans(REG_PT_WORD(0), devc->protocol_trigger.word[0]);
133 ops[9] = mso_trans(REG_PT_WORD(1), devc->protocol_trigger.word[1]);
134 ops[10] = mso_trans(REG_PT_WORD(2), devc->protocol_trigger.word[2]);
135 ops[11] = mso_trans(REG_PT_WORD(3), devc->protocol_trigger.word[3]);
136 ops[12] = mso_trans(REG_PT_MASK(0), devc->protocol_trigger.mask[0]);
137 ops[13] = mso_trans(REG_PT_MASK(1), devc->protocol_trigger.mask[1]);
138 ops[14] = mso_trans(REG_PT_MASK(2), devc->protocol_trigger.mask[2]);
139 ops[15] = mso_trans(REG_PT_MASK(3), devc->protocol_trigger.mask[3]);
140 ops[16] = mso_trans(REG_PT_SPIMODE, devc->protocol_trigger.spimode);
141 /* Select the default config bank */
142 ops[17] = mso_trans(REG_CTL2, devc->ctlbase2);
144 return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
147 SR_PRIV int mso_configure_threshold_level(const struct sr_dev_inst *sdi)
149 struct dev_context *devc = sdi->priv;
151 return mso_dac_out(sdi, la_threshold_map[devc->la_threshold]);
154 SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi)
156 uint16_t ops[] = { mso_trans(REG_BUFFER, 0) };
157 struct dev_context *devc = sdi->priv;
159 sr_dbg("Requesting buffer dump.");
160 return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
163 SR_PRIV int mso_arm(const struct sr_dev_inst *sdi)
165 struct dev_context *devc = sdi->priv;
167 mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETFSM),
168 mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_ARM),
169 mso_trans(REG_CTL1, devc->ctlbase1),
172 sr_dbg("Requesting trigger arm.");
173 return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
176 SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi)
178 struct dev_context *devc = sdi->priv;
180 mso_trans(REG_CTL1, devc->ctlbase1 | 8),
181 mso_trans(REG_CTL1, devc->ctlbase1),
184 sr_dbg("Requesting forced capture.");
185 return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
188 SR_PRIV int mso_dac_out(const struct sr_dev_inst *sdi, uint16_t val)
190 struct dev_context *devc = sdi->priv;
192 mso_trans(REG_DAC1, (val >> 8) & 0xff),
193 mso_trans(REG_DAC2, val & 0xff),
194 mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETADC),
197 sr_dbg("Setting dac word to 0x%x.", val);
198 return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
201 SR_PRIV inline uint16_t mso_calc_raw_from_mv(struct dev_context * devc)
203 return (uint16_t) (0x200 -
204 ((devc->dso_trigger_voltage / devc->dso_probe_attn) /
208 SR_PRIV int mso_parse_serial(const char *iSerial, const char *iProduct,
209 struct dev_context *devc)
211 unsigned int u1, u2, u3, u4, u5, u6;
215 /* FIXME: This code is in the original app, but I think its
216 * used only for the GUI */
217 /* if (strstr(iProduct, "REV_02") || strstr(iProduct, "REV_03"))
218 devc->num_sample_rates = 0x16;
220 devc->num_sample_rates = 0x10; */
223 if (iSerial[0] != '4' || sscanf(iSerial, "%5u%3u%3u%1u%1u%6u",
224 &u1, &u2, &u3, &u4, &u5, &u6) != 6)
228 devc->vbit = u1 / 10000;
230 devc->vbit = 4.19195;
231 devc->dac_offset = u2;
232 if (devc->dac_offset == 0)
233 devc->dac_offset = 0x1ff;
234 devc->offset_range = u3;
235 if (devc->offset_range == 0)
236 devc->offset_range = 0x17d;
239 * FIXME: There is more code on the original software to handle
240 * bigger iSerial strings, but as I can't test on my device
241 * I will not implement it yet
247 SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi)
249 struct dev_context *devc = sdi->priv;
252 ops[0] = mso_trans(REG_CTL1, (devc->ctlbase1 | BIT_CTL1_RESETADC));
253 ops[1] = mso_trans(REG_CTL1, devc->ctlbase1);
254 devc->ctlbase1 |= BIT_CTL1_ADC_UNKNOWN4;
256 sr_dbg("Requesting ADC reset.");
257 return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
260 SR_PRIV int mso_reset_fsm(struct sr_dev_inst *sdi)
262 struct dev_context *devc = sdi->priv;
265 devc->ctlbase1 |= BIT_CTL1_RESETFSM;
266 ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);
268 sr_dbg("Requesting ADC reset.");
269 return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
272 SR_PRIV int mso_toggle_led(struct sr_dev_inst *sdi, int state)
274 struct dev_context *devc = sdi->priv;
277 devc->ctlbase1 &= ~BIT_CTL1_LED;
279 devc->ctlbase1 |= BIT_CTL1_LED;
280 ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);
282 sr_dbg("Requesting LED toggle.");
283 return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
286 SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi)
288 struct sr_datafeed_packet packet;
289 struct dev_context *devc;
292 serial_source_remove(sdi->session, devc->serial);
294 /* Terminate session */
295 packet.type = SR_DF_END;
296 sr_session_send(sdi, &packet);
299 SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val)
302 mso_trans(REG_CLKRATE1, (val >> 8) & 0xff),
303 mso_trans(REG_CLKRATE2, val & 0xff),
306 sr_dbg("Setting clkrate word to 0x%x.", val);
307 return mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
310 SR_PRIV int mso_configure_rate(const struct sr_dev_inst *sdi, uint32_t rate)
312 struct dev_context *devc = sdi->priv;
316 for (i = 0; i < ARRAY_SIZE(rate_map); i++) {
317 if (rate_map[i].rate == rate) {
318 devc->ctlbase2 = rate_map[i].slowmode;
319 ret = mso_clkrate_out(devc->serial, rate_map[i].val);
321 devc->cur_rate = rate;
327 sr_err("Unsupported rate.");
332 SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst *serial, uint8_t *info)
334 uint16_t ops[] = { mso_trans(REG_TRIGGER, 0) };
337 sr_dbg("Requesting trigger state.");
338 ret = mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
339 if (info == NULL || ret != SR_OK)
343 if (serial_read(serial, &buf, 1) != 1) /* FIXME: Need timeout */
348 sr_dbg("Trigger state is: 0x%x.", *info);
352 SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data)
354 struct sr_datafeed_packet packet;
355 struct sr_datafeed_logic logic;
356 struct sr_dev_inst *sdi;
360 struct drv_context *drvc = di->priv;
362 /* Find this device's devc struct by its fd. */
363 struct dev_context *devc = NULL;
364 for (l = drvc->instances; l; l = l->next) {
367 if (devc->serial->fd == fd)
372 /* Shouldn't happen. */
378 size_t s = serial_read(devc->serial, in, sizeof(in));
383 /* Check if we triggered, then send a command that we are ready
384 * to read the data */
385 if (devc->trigger_state != MSO_TRIGGER_DATAREADY) {
386 devc->trigger_state = in[0];
387 if (devc->trigger_state == MSO_TRIGGER_DATAREADY) {
388 mso_read_buffer(sdi);
391 mso_check_trigger(devc->serial, NULL);
396 /* the hardware always dumps 1024 samples, 24bits each */
397 if (devc->buffer_n < 3072) {
398 memcpy(devc->buffer + devc->buffer_n, in, s);
401 if (devc->buffer_n < 3072)
404 /* do the conversion */
405 uint8_t logic_out[1024];
406 double analog_out[1024];
407 for (i = 0; i < 1024; i++) {
408 /* FIXME: Need to do conversion to mV */
409 analog_out[i] = (devc->buffer[i * 3] & 0x3f) |
410 ((devc->buffer[i * 3 + 1] & 0xf) << 6);
412 logic_out[i] = ((devc->buffer[i * 3 + 1] & 0x30) >> 4) |
413 ((devc->buffer[i * 3 + 2] & 0x3f) << 2);
416 packet.type = SR_DF_LOGIC;
417 packet.payload = &logic;
420 logic.data = logic_out;
421 sr_session_send(cb_data, &packet);
423 devc->num_samples += 1024;
425 if (devc->limit_samples && devc->num_samples >= devc->limit_samples) {
426 sr_info("Requested number of samples reached.");
427 sdi->driver->dev_acquisition_stop(sdi, cb_data);
433 SR_PRIV int mso_configure_channels(const struct sr_dev_inst *sdi)
435 struct dev_context *devc;
436 struct sr_channel *ch;
442 devc->la_trigger_mask = 0xFF; //the mask for the LA_TRIGGER (bits set to 0 matter, those set to 1 are ignored).
443 devc->la_trigger = 0x00; //The value of the LA byte that generates a trigger event (in that mode).
444 devc->dso_trigger_voltage = 3;
445 devc->dso_probe_attn = 1;
446 devc->trigger_outsrc = 0;
447 devc->trigger_chan = 3; //LA combination trigger
448 devc->use_trigger = FALSE;
450 for (l = sdi->channels; l; l = l->next) {
451 ch = (struct sr_channel *)l->data;
452 if (ch->enabled == FALSE)
455 int channel_bit = 1 << (ch->index);
459 devc->use_trigger = TRUE;
460 //Configure trigger mask and value.
461 for (tc = ch->trigger; *tc; tc++) {
462 devc->la_trigger_mask &= ~channel_bit;
464 devc->la_trigger |= channel_bit;