2 * This file is part of the libsigrok project.
4 * Copyright (C) 2022 Gerhard Sittig <gerhard.sittig@gmx.net>
5 * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de>
6 * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
7 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
8 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
10 * This program is free software: you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation, either version 3 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program. If not, see <http://www.gnu.org/licenses/>.
26 #include <libsigrok/libsigrok.h>
29 #include "libsigrok-internal.h"
32 /* USB PID dependent MCU firmware. Model dependent FPGA bitstream. */
33 #define MCU_FWFILE_FMT "kingst-la-%04x.fw"
34 #define FPGA_FWFILE_FMT "kingst-%s-fpga.bitstream"
37 * List of known devices and their features. See @ref kingst_model
38 * for the fields' type and meaning. Table is sorted by EEPROM magic.
39 * More specific items need to go first (additional byte[2/6]). Not
40 * all devices are covered by this driver implementation, but telling
41 * users what was detected is considered useful.
43 * TODO Verify the identification of models that were not tested before.
45 static const struct kingst_model models[] = {
46 { 2, 1, "LA2016", "la2016a1", SR_MHZ(200), 16, 1, 0, },
47 { 2, 0, "LA2016", "la2016", SR_MHZ(200), 16, 1, 0, },
48 { 3, 1, "LA1016", "la1016a1", SR_MHZ(100), 16, 1, 0, },
49 { 3, 0, "LA1016", "la1016", SR_MHZ(100), 16, 1, 0, },
50 { 4, 0, "LA1010", "la1010a0", SR_MHZ(100), 16, 0, SR_MHZ(800), },
51 { 5, 0, "LA5016", "la5016a1", SR_MHZ(500), 16, 2, 0, },
52 { 6, 0, "LA5032", "la5032a0", SR_MHZ(500), 32, 4, 0, },
53 { 7, 0, "LA1010", "la1010a1", SR_MHZ(100), 16, 0, SR_MHZ(800), },
54 { 8, 0, "LA2016", "la2016a1", SR_MHZ(200), 16, 1, 0, },
55 { 9, 0, "LA1016", "la1016a1", SR_MHZ(100), 16, 1, 0, },
56 { 10, 0, "LA1010", "la1010a2", SR_MHZ(100), 16, 0, SR_MHZ(800), },
57 { 65, 0, "LA5016", "la5016a1", SR_MHZ(500), 16, 2, 0, },
60 /* USB vendor class control requests, executed by the Cypress FX2 MCU. */
61 #define CMD_FPGA_ENABLE 0x10
62 #define CMD_FPGA_SPI 0x20 /* R/W access to FPGA registers via SPI. */
63 #define CMD_BULK_START 0x30 /* Start sample data download via USB EP6 IN. */
64 #define CMD_BULK_RESET 0x38 /* Flush FIFO of FX2 USB EP6 IN. */
65 #define CMD_FPGA_INIT 0x50 /* Used before and after FPGA bitstream upload. */
66 #define CMD_KAUTH 0x60 /* Communicate to auth IC (U10). Not used. */
67 #define CMD_EEPROM 0xa2 /* R/W access to EEPROM content. */
70 * FPGA register addresses (base addresses when registers span multiple
71 * bytes, in that case data is kept in little endian format). Passed to
72 * CMD_FPGA_SPI requests. The FX2 MCU transparently handles the detail
73 * of SPI transfers encoding the read (1) or write (0) direction in the
74 * MSB of the address field. There are some 60 byte-wide FPGA registers.
76 * Unfortunately the FPGA registers change their meaning between the
77 * read and write directions of access, or exclusively provide one of
78 * these directions and not the other. This is an arbitrary vendor's
79 * choice, there is nothing which the sigrok driver could do about it.
80 * Values written to registers typically cannot get read back, neither
81 * verified after writing a configuration, nor queried upon startup for
82 * automatic detection of the current configuration. Neither appear to
83 * be there echo registers for presence and communication checks, nor
84 * version identifying registers, as far as we know.
86 #define REG_RUN 0x00 /* Read capture status, write start capture. */
87 #define REG_PWM_EN 0x02 /* User PWM channels on/off. */
88 #define REG_CAPT_MODE 0x03 /* Write 0x00 capture to SDRAM, 0x01 streaming. */
89 #define REG_PIN_STATE 0x04 /* Read current pin state (real time display). */
90 #define REG_BULK 0x08 /* Write start addr, byte count to download samples. */
91 #define REG_SAMPLING 0x10 /* Write capture config, read capture SDRAM location. */
92 #define REG_TRIGGER 0x20 /* Write level and edge trigger config. */
93 #define REG_UNKNOWN_30 0x30
94 #define REG_THRESHOLD 0x68 /* Write PWM config to setup input threshold DAC. */
95 #define REG_PWM1 0x70 /* Write config for user PWM1. */
96 #define REG_PWM2 0x78 /* Write config for user PWM2. */
98 /* Bit patterns to write to REG_CAPT_MODE. */
99 #define CAPTMODE_TO_RAM 0x00
100 #define CAPTMODE_STREAM 0x01
102 /* Bit patterns to write to REG_RUN, setup run mode. */
103 #define RUNMODE_HALT 0x00
104 #define RUNMODE_RUN 0x03
106 /* Bit patterns when reading from REG_RUN, get run state. */
107 #define RUNSTATE_IDLE_BIT (1UL << 0)
108 #define RUNSTATE_DRAM_BIT (1UL << 1)
109 #define RUNSTATE_TRGD_BIT (1UL << 2)
110 #define RUNSTATE_POST_BIT (1UL << 3)
112 static int ctrl_in(const struct sr_dev_inst *sdi,
113 uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
114 void *data, uint16_t wLength)
116 struct sr_usb_dev_inst *usb;
121 ret = libusb_control_transfer(usb->devhdl,
122 LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN,
123 bRequest, wValue, wIndex, data, wLength,
125 if (ret != wLength) {
126 sr_dbg("USB ctrl in: %d bytes, req %d val %#x idx %d: %s.",
127 wLength, bRequest, wValue, wIndex,
128 libusb_error_name(ret));
129 sr_err("Cannot read %d bytes from USB: %s.",
130 wLength, libusb_error_name(ret));
137 static int ctrl_out(const struct sr_dev_inst *sdi,
138 uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
139 void *data, uint16_t wLength)
141 struct sr_usb_dev_inst *usb;
146 ret = libusb_control_transfer(usb->devhdl,
147 LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT,
148 bRequest, wValue, wIndex, data, wLength,
150 if (ret != wLength) {
151 sr_dbg("USB ctrl out: %d bytes, req %d val %#x idx %d: %s.",
152 wLength, bRequest, wValue, wIndex,
153 libusb_error_name(ret));
154 sr_err("Cannot write %d bytes to USB: %s.",
155 wLength, libusb_error_name(ret));
162 /* HACK Experiment to spot FPGA registers of interest. */
163 static void la2016_dump_fpga_registers(const struct sr_dev_inst *sdi,
164 const char *caption, size_t reg_lower, size_t reg_upper)
166 static const size_t dump_chunk_len = 16;
169 uint8_t rdbuf[0x80 - 0x00]; /* Span all FPGA registers. */
170 const uint8_t *rdptr;
172 size_t dump_addr, indent, dump_len;
175 if (sr_log_loglevel_get() < SR_LOG_SPEW)
178 if (!reg_lower && !reg_upper) {
180 reg_upper = sizeof(rdbuf);
182 if (reg_upper - reg_lower > sizeof(rdbuf))
183 reg_upper = sizeof(rdbuf) - reg_lower;
185 rdlen = reg_upper - reg_lower;
186 ret = ctrl_in(sdi, CMD_FPGA_SPI, reg_lower, 0, rdbuf, rdlen);
188 sr_err("Cannot get registers space.");
193 sr_spew("FPGA registers dump: %s", caption ? : "for fun");
194 dump_addr = reg_lower;
197 indent = dump_addr % dump_chunk_len;
198 if (dump_len > dump_chunk_len)
199 dump_len = dump_chunk_len;
200 if (dump_len + indent > dump_chunk_len)
201 dump_len = dump_chunk_len - indent;
202 txt = sr_hexdump_new(rdptr, dump_len);
203 sr_spew(" %04zx %*s%s",
204 dump_addr, (int)(3 * indent), "", txt->str);
205 sr_hexdump_free(txt);
206 dump_addr += dump_len;
213 * Check the necessity for FPGA bitstream upload, because another upload
214 * would take some 600ms which is undesirable after program startup. Try
215 * to access some FPGA registers and check the values' plausibility. The
216 * check should fail on the safe side, request another upload when in
217 * doubt. A positive response (the request to continue operation with the
218 * currently active bitstream) should be conservative. Accessing multiple
219 * registers is considered cheap compared to the cost of bitstream upload.
221 * It helps though that both the vendor software and the sigrok driver
222 * use the same bundle of MCU firmware and FPGA bitstream for any of the
223 * supported models. We don't expect to successfully communicate to the
224 * device yet disagree on its protocol. Ideally we would access version
225 * identifying registers for improved robustness, but are not aware of
226 * any. A bitstream reload can always be forced by a power cycle.
228 static int check_fpga_bitstream(const struct sr_dev_inst *sdi)
231 uint8_t buff[REG_PWM_EN - REG_RUN]; /* Larger of REG_RUN, REG_PWM_EN. */
236 const uint8_t *rdptr;
238 sr_dbg("Checking operation of the FPGA bitstream.");
239 la2016_dump_fpga_registers(sdi, "bitstream check", 0, 0);
242 ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &init_rsp, sizeof(init_rsp));
243 if (ret != SR_OK || init_rsp != 0) {
244 sr_dbg("FPGA init query failed, or unexpected response.");
248 read_len = sizeof(run_state);
249 ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, read_len);
251 sr_dbg("FPGA register access failed (run state).");
255 run_state = read_u16le_inc(&rdptr);
256 sr_spew("FPGA register: run state 0x%04x.", run_state);
257 if (run_state && (run_state & 0x3) != 0x1) {
258 sr_dbg("Unexpected FPGA register content (run state).");
261 if (run_state && (run_state & ~0xf) != 0x85e0) {
262 sr_dbg("Unexpected FPGA register content (run state).");
266 read_len = sizeof(pwm_en);
267 ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, buff, read_len);
269 sr_dbg("FPGA register access failed (PWM enable).");
273 pwm_en = read_u8_inc(&rdptr);
274 sr_spew("FPGA register: PWM enable 0x%02x.", pwm_en);
275 if ((pwm_en & 0x3) != 0x0) {
276 sr_dbg("Unexpected FPGA register content (PWM enable).");
280 sr_info("Could re-use current FPGA bitstream. No upload required.");
284 static int upload_fpga_bitstream(const struct sr_dev_inst *sdi,
285 const char *bitstream_fname)
287 struct drv_context *drvc;
288 struct sr_usb_dev_inst *usb;
289 struct sr_resource bitstream;
290 uint32_t bitstream_size;
291 uint8_t buffer[sizeof(uint32_t)];
297 unsigned int zero_pad_to;
299 drvc = sdi->driver->context;
302 sr_info("Uploading FPGA bitstream '%s'.", bitstream_fname);
304 ret = sr_resource_open(drvc->sr_ctx, &bitstream,
305 SR_RESOURCE_FIRMWARE, bitstream_fname);
307 sr_err("Cannot find FPGA bitstream %s.", bitstream_fname);
311 bitstream_size = (uint32_t)bitstream.size;
313 write_u32le_inc(&wrptr, bitstream_size);
314 ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer);
316 sr_err("Cannot initiate FPGA bitstream upload.");
317 sr_resource_close(drvc->sr_ctx, &bitstream);
320 zero_pad_to = bitstream_size;
321 zero_pad_to += LA2016_EP2_PADDING - 1;
322 zero_pad_to /= LA2016_EP2_PADDING;
323 zero_pad_to *= LA2016_EP2_PADDING;
327 if (pos < bitstream.size) {
328 len = (int)sr_resource_read(drvc->sr_ctx, &bitstream,
329 block, sizeof(block));
331 sr_err("Cannot read FPGA bitstream.");
332 sr_resource_close(drvc->sr_ctx, &bitstream);
336 /* Zero-pad until 'zero_pad_to'. */
337 len = zero_pad_to - pos;
338 if ((unsigned)len > sizeof(block))
340 memset(&block, 0, len);
345 ret = libusb_bulk_transfer(usb->devhdl, USB_EP_FPGA_BITSTREAM,
346 &block[0], len, &act_len, DEFAULT_TIMEOUT_MS);
348 sr_dbg("Cannot write FPGA bitstream, block %#x len %d: %s.",
349 pos, (int)len, libusb_error_name(ret));
353 if (act_len != len) {
354 sr_dbg("Short write for FPGA bitstream, block %#x len %d: got %d.",
355 pos, (int)len, act_len);
361 sr_resource_close(drvc->sr_ctx, &bitstream);
364 sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.",
370 static int enable_fpga_bitstream(const struct sr_dev_inst *sdi)
375 ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &resp, sizeof(resp));
377 sr_err("Cannot read response after FPGA bitstream upload.");
381 sr_err("Unexpected FPGA bitstream upload response, got 0x%02x, want 0.",
387 ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0);
389 sr_err("Cannot enable FPGA after bitstream upload.");
397 static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage)
400 uint16_t duty_R79, duty_R56;
401 uint8_t buf[REG_PWM1 - REG_THRESHOLD]; /* Width of REG_THRESHOLD. */
404 /* Clamp threshold setting to valid range for LA2016. */
405 if (voltage > LA2016_THR_VOLTAGE_MAX) {
406 voltage = LA2016_THR_VOLTAGE_MAX;
407 } else if (voltage < -LA2016_THR_VOLTAGE_MAX) {
408 voltage = -LA2016_THR_VOLTAGE_MAX;
412 * Two PWM output channels feed one DAC which generates a bias
413 * voltage, which offsets the input probe's voltage level, and
414 * in combination with the FPGA pins' fixed threshold result in
415 * a programmable input threshold from the user's perspective.
416 * The PWM outputs can be seen on R79 and R56 respectively, the
417 * frequency is 100kHz and the duty cycle varies. The R79 PWM
418 * uses three discrete settings. The R56 PWM varies with desired
419 * thresholds and depends on the R79 PWM configuration. See the
420 * schematics comments which discuss the formulae.
422 if (voltage >= 2.9) {
423 duty_R79 = 0; /* PWM off (0V). */
424 duty_R56 = (uint16_t)(302 * voltage - 363);
425 } else if (voltage > -0.4) {
426 duty_R79 = 0x00f2; /* 25% duty cycle. */
427 duty_R56 = (uint16_t)(302 * voltage + 121);
429 duty_R79 = 0x02d7; /* 72% duty cycle. */
430 duty_R56 = (uint16_t)(302 * voltage + 1090);
433 /* Clamp duty register values to sensible limits. */
436 } else if (duty_R56 > 1100) {
440 sr_dbg("Set threshold voltage %.2fV.", voltage);
441 sr_dbg("Duty cycle values: R56 0x%04x, R79 0x%04x.", duty_R56, duty_R79);
444 write_u16le_inc(&wrptr, duty_R56);
445 write_u16le_inc(&wrptr, duty_R79);
447 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_THRESHOLD, 0, buf, wrptr - buf);
449 sr_err("Cannot set threshold voltage %.2fV.", voltage);
457 * Communicates a channel's configuration to the device after the
458 * parameters may have changed. Configuration of one channel may
459 * interfere with other channels since they share FPGA registers.
461 static int set_pwm_config(const struct sr_dev_inst *sdi, size_t idx)
463 static uint8_t reg_bases[] = { REG_PWM1, REG_PWM2, };
465 struct dev_context *devc;
466 struct pwm_setting *params;
470 uint32_t period, duty;
473 uint8_t enable_all, enable_cfg, reg_val;
474 uint8_t buf[REG_PWM2 - REG_PWM1]; /* Width of one REG_PWMx. */
478 if (idx >= ARRAY_SIZE(devc->pwm_setting))
480 params = &devc->pwm_setting[idx];
481 if (idx >= ARRAY_SIZE(reg_bases))
483 reg_base = reg_bases[idx];
486 * Map application's specs to hardware register values. Do math
487 * in floating point initially, but convert to u32 eventually.
489 sr_dbg("PWM config, app spec, ch %zu, en %d, freq %.1f, duty %.1f.",
490 idx, params->enabled ? 1 : 0, params->freq, params->duty);
492 val_f /= params->freq;
496 val_f *= params->duty;
501 sr_dbg("PWM config, reg 0x%04x, freq %u, duty %u.",
502 (unsigned)reg_base, (unsigned)period, (unsigned)duty);
504 /* Get the "enabled" state of all supported PWM channels. */
506 for (ch = 0; ch < ARRAY_SIZE(devc->pwm_setting); ch++) {
507 if (!devc->pwm_setting[ch].enabled)
509 enable_all |= 1U << ch;
511 enable_cfg = 1U << idx;
512 sr_spew("PWM config, enable all 0x%02hhx, cfg 0x%02hhx.",
513 enable_all, enable_cfg);
516 * Disable the to-get-configured channel before its parameters
517 * will change. Or disable and exit when the channel is supposed
520 sr_spew("PWM config, disabling before param change.");
521 reg_val = enable_all & ~enable_cfg;
522 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0,
523 ®_val, sizeof(reg_val));
525 sr_err("Cannot adjust PWM enabled state.");
528 if (!params->enabled)
531 /* Write register values to device. */
532 sr_spew("PWM config, sending new parameters.");
534 write_u32le_inc(&wrptr, period);
535 write_u32le_inc(&wrptr, duty);
536 ret = ctrl_out(sdi, CMD_FPGA_SPI, reg_base, 0, buf, wrptr - buf);
538 sr_err("Cannot change PWM parameters.");
542 /* Enable configured channel after write completion. */
543 sr_spew("PWM config, enabling after param change.");
544 reg_val = enable_all | enable_cfg;
545 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0,
546 ®_val, sizeof(reg_val));
548 sr_err("Cannot adjust PWM enabled state.");
556 * Determine the number of enabled channels as well as their bitmask
557 * representation. Derive data here which later simplifies processing
558 * of raw capture data memory content in streaming mode.
560 static void la2016_prepare_stream(const struct sr_dev_inst *sdi)
562 struct dev_context *devc;
563 struct stream_state_t *stream;
566 struct sr_channel *ch;
569 stream = &devc->stream;
570 memset(stream, 0, sizeof(*stream));
572 stream->enabled_count = 0;
573 for (l = sdi->channels; l; l = l->next) {
575 if (ch->type != SR_CHANNEL_LOGIC)
579 channel_mask = 1UL << ch->index;
580 stream->enabled_mask |= channel_mask;
581 stream->channel_masks[stream->enabled_count++] = channel_mask;
583 stream->channel_index = 0;
587 * This routine configures the set of enabled channels, as well as the
588 * trigger condition (if one was specified). Also prepares the capture
589 * data processing in stream mode, where the memory layout dramatically
590 * differs from normal mode.
592 static int set_trigger_config(const struct sr_dev_inst *sdi)
594 struct dev_context *devc;
595 struct sr_trigger *trigger;
597 uint32_t channels; /* Actually: Enabled channels? */
598 uint32_t enabled; /* Actually: Triggering channels? */
600 uint32_t high_or_falling;
604 struct sr_trigger_stage *stage1;
605 struct sr_trigger_match *match;
608 uint8_t buf[REG_UNKNOWN_30 - REG_TRIGGER]; /* Width of REG_TRIGGER. */
613 la2016_prepare_stream(sdi);
615 memset(&cfg, 0, sizeof(cfg));
616 cfg.channels = devc->stream.enabled_mask;
618 sr_err("Need at least one enabled logic channel.");
621 trigger = sr_session_trigger_get(sdi->session);
622 if (trigger && trigger->stages) {
623 stages = trigger->stages;
624 stage1 = stages->data;
626 sr_err("Only one trigger stage supported for now.");
629 channel = stage1->matches;
631 match = channel->data;
632 ch_mask = 1UL << match->channel->index;
634 switch (match->match) {
635 case SR_TRIGGER_ZERO:
636 cfg.level |= ch_mask;
637 cfg.high_or_falling &= ~ch_mask;
640 cfg.level |= ch_mask;
641 cfg.high_or_falling |= ch_mask;
643 case SR_TRIGGER_RISING:
644 if ((cfg.enabled & ~cfg.level)) {
645 sr_err("Device only supports one edge trigger.");
648 cfg.level &= ~ch_mask;
649 cfg.high_or_falling &= ~ch_mask;
651 case SR_TRIGGER_FALLING:
652 if ((cfg.enabled & ~cfg.level)) {
653 sr_err("Device only supports one edge trigger.");
656 cfg.level &= ~ch_mask;
657 cfg.high_or_falling |= ch_mask;
660 sr_err("Unknown trigger condition.");
663 cfg.enabled |= ch_mask;
664 channel = channel->next;
667 sr_dbg("Set trigger config: "
668 "enabled-channels 0x%04x, triggering-channels 0x%04x, "
669 "level-triggered 0x%04x, high/falling 0x%04x.",
670 cfg.channels, cfg.enabled, cfg.level, cfg.high_or_falling);
673 * Don't configure hardware trigger parameters in streaming mode
674 * or when the device lacks local memory. Yet the above dump of
675 * derived parameters from user specs is considered valueable.
677 * TODO Add support for soft triggers when hardware triggers in
678 * the device are not used or are not available at all.
680 if (!devc->model->memory_bits || devc->continuous) {
681 if (!devc->model->memory_bits)
682 sr_dbg("Device without memory. No hardware triggers.");
683 else if (devc->continuous)
684 sr_dbg("Streaming mode. No hardware triggers.");
687 cfg.high_or_falling = 0;
690 devc->trigger_involved = cfg.enabled != 0;
693 write_u32le_inc(&wrptr, cfg.channels);
694 write_u32le_inc(&wrptr, cfg.enabled);
695 write_u32le_inc(&wrptr, cfg.level);
696 write_u32le_inc(&wrptr, cfg.high_or_falling);
698 * Comment on this literal 16. Origin, meaning? Cannot be the
699 * register offset, nor the transfer length. Is it a channels
700 * count that is relevant for 16 and 32 channel models? Is it
701 * an obsolete experiment?
703 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_TRIGGER, 16, buf, wrptr - buf);
705 sr_err("Cannot setup trigger configuration.");
713 * This routine communicates the sample configuration to the device:
714 * Total samples count and samplerate, pre-trigger configuration.
716 static int set_sample_config(const struct sr_dev_inst *sdi)
718 struct dev_context *devc;
720 uint64_t min_samplerate, eff_samplerate;
721 uint64_t stream_bandwidth;
722 uint16_t divider_u16;
723 uint64_t limit_samples;
724 uint64_t pre_trigger_samples;
725 uint64_t pre_trigger_memory;
726 uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */
732 if (devc->samplerate > devc->model->samplerate) {
733 sr_err("Too high a sample rate: %" PRIu64 ".",
737 baseclock = devc->model->baseclock;
739 baseclock = devc->model->samplerate;
740 min_samplerate = baseclock;
741 min_samplerate /= 65536;
742 if (devc->samplerate < min_samplerate) {
743 sr_err("Too low a sample rate: %" PRIu64 ".",
747 divider_u16 = baseclock / devc->samplerate;
748 eff_samplerate = baseclock / divider_u16;
750 ret = sr_sw_limits_get_remain(&devc->sw_limits,
751 &limit_samples, NULL, NULL, NULL);
753 sr_err("Cannot get acquisition limits.");
756 if (limit_samples > LA2016_NUM_SAMPLES_MAX) {
757 sr_warn("Too high a sample depth: %" PRIu64 ", capping.",
759 limit_samples = LA2016_NUM_SAMPLES_MAX;
761 if (limit_samples == 0) {
762 limit_samples = LA2016_NUM_SAMPLES_MAX;
763 sr_dbg("Passing %" PRIu64 " to HW for unlimited samples.",
768 * The acquisition configuration communicates "pre-trigger"
769 * specs in several formats. sigrok users provide a percentage
770 * (0-100%), which translates to a pre-trigger samples count
771 * (assuming that a total samples count limit was specified).
772 * The device supports hardware compression, which depends on
773 * slowly changing input data to be effective. Fast changing
774 * input data may occupy more space in sample memory than its
775 * uncompressed form would. This is why a third parameter can
776 * limit the amount of sample memory to use for pre-trigger
777 * data. Only the upper 24 bits of that memory size spec get
778 * communicated to the device (written to its FPGA register).
780 if (!devc->model->memory_bits) {
781 sr_dbg("Memory-less device, skipping pre-trigger config.");
782 pre_trigger_samples = 0;
783 pre_trigger_memory = 0;
784 } else if (devc->trigger_involved) {
785 pre_trigger_samples = limit_samples;
786 pre_trigger_samples *= devc->capture_ratio;
787 pre_trigger_samples /= 100;
788 pre_trigger_memory = devc->model->memory_bits;
789 pre_trigger_memory *= UINT64_C(1024 * 1024 * 1024);
790 pre_trigger_memory /= 8; /* devc->model->channel_count ? */
791 pre_trigger_memory *= devc->capture_ratio;
792 pre_trigger_memory /= 100;
794 sr_dbg("No trigger setup, skipping pre-trigger config.");
795 pre_trigger_samples = 0;
796 pre_trigger_memory = 0;
798 /* Ensure non-zero value after LSB shift out in HW reg. */
799 if (pre_trigger_memory < 0x100)
800 pre_trigger_memory = 0x100;
802 sr_dbg("Set sample config: %" PRIu64 "kHz (div %" PRIu16 "), %" PRIu64 " samples.",
803 eff_samplerate / SR_KHZ(1), divider_u16, limit_samples);
804 sr_dbg("Capture ratio %" PRIu64 "%%, count %" PRIu64 ", mem %" PRIu64 ".",
805 devc->capture_ratio, pre_trigger_samples, pre_trigger_memory);
807 if (devc->continuous) {
808 stream_bandwidth = eff_samplerate;
809 stream_bandwidth *= devc->stream.enabled_count;
810 sr_dbg("Streaming: channel count %zu, product %" PRIu64 ".",
811 devc->stream.enabled_count, stream_bandwidth);
812 stream_bandwidth /= 1000 * 1000;
813 if (stream_bandwidth >= LA2016_STREAM_MBPS_MAX) {
814 sr_warn("High USB stream bandwidth: %" PRIu64 "Mbps.",
817 if (stream_bandwidth < LA2016_STREAM_PUSH_THR) {
818 sr_dbg("Streaming: low Mbps, suggest periodic flush.");
819 devc->stream.flush_period_ms = LA2016_STREAM_PUSH_IVAL;
824 * The acquisition configuration occupies a total of 16 bytes:
825 * - A 34bit total samples count limit (up to 10 billions) that
826 * is kept in a 40bit register.
827 * - A 34bit pre-trigger samples count limit (up to 10 billions)
828 * in another 40bit register.
829 * - A 32bit pre-trigger memory space limit (in bytes) of which
830 * the upper 24bits are kept in an FPGA register.
831 * - A 16bit clock divider which gets applied to the maximum
832 * samplerate of the device.
833 * - An 8bit register of unknown meaning. Currently always 0.
836 write_u40le_inc(&wrptr, limit_samples);
837 write_u40le_inc(&wrptr, pre_trigger_samples);
838 write_u24le_inc(&wrptr, pre_trigger_memory >> 8);
839 write_u16le_inc(&wrptr, divider_u16);
840 write_u8_inc(&wrptr, 0);
841 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, wrptr - buf);
843 sr_err("Cannot setup acquisition configuration.");
851 * FPGA register REG_RUN holds the run state (u16le format). Bit fields
853 * bit 0: value 1 = idle
854 * bit 1: value 1 = writing to SDRAM
855 * bit 2: value 0 = waiting for trigger, 1 = trigger seen
856 * bit 3: value 0 = pretrigger sampling, 1 = posttrigger sampling
857 * The meaning of other bit fields is unknown.
859 * Typical values in order of appearance during execution:
860 * 0x85e1: idle, no acquisition pending
861 * IDLE set, TRGD don't care, POST don't care; DRAM don't care
862 * "In idle state." Takes precedence over all others.
863 * 0x85e2: pre-sampling, samples before the trigger position,
864 * when capture ratio > 0%
865 * IDLE clear, TRGD clear, POST clear; DRAM don't care
866 * "Not idle any more, no post yet, not triggered yet."
867 * 0x85ea: pre-sampling complete, now waiting for the trigger
868 * (whilst sampling continuously)
869 * IDLE clear, TRGD clear, POST set; DRAM don't care
870 * "Post set thus after pre, not triggered yet"
871 * 0x85ee: trigger seen, capturing post-trigger samples, running
872 * IDLE clear, TRGD set, POST set; DRAM don't care
873 * "Triggered and in post, not idle yet."
875 * IDLE set, TRGD don't care, POST don't care; DRAM don't care
876 * "In idle state." TRGD/POST don't care, same meaning as above.
878 static const uint16_t runstate_mask_idle = RUNSTATE_IDLE_BIT;
879 static const uint16_t runstate_patt_idle = RUNSTATE_IDLE_BIT;
880 static const uint16_t runstate_mask_step =
881 RUNSTATE_IDLE_BIT | RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT;
882 static const uint16_t runstate_patt_pre_trig = 0;
883 static const uint16_t runstate_patt_wait_trig = RUNSTATE_POST_BIT;
884 static const uint16_t runstate_patt_post_trig =
885 RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT;
887 static uint16_t run_state(const struct sr_dev_inst *sdi)
889 static uint16_t previous_state;
893 uint8_t buff[REG_PWM_EN - REG_RUN]; /* Width of REG_RUN. */
894 const uint8_t *rdptr;
897 ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, sizeof(state));
899 sr_err("Cannot read run state.");
903 state = read_u16le_inc(&rdptr);
906 * Avoid flooding the log, only dump values as they change.
907 * The routine is called about every 50ms.
909 if (state == previous_state)
912 previous_state = state;
914 if ((state & runstate_mask_idle) == runstate_patt_idle)
916 if ((state & runstate_mask_step) == runstate_patt_pre_trig)
917 label = "pre-trigger sampling";
918 if ((state & runstate_mask_step) == runstate_patt_wait_trig)
919 label = "sampling, waiting for trigger";
920 if ((state & runstate_mask_step) == runstate_patt_post_trig)
921 label = "post-trigger sampling";
923 sr_dbg("Run state: 0x%04x (%s).", state, label);
925 sr_dbg("Run state: 0x%04x.", state);
930 static gboolean la2016_is_idle(const struct sr_dev_inst *sdi)
934 state = run_state(sdi);
935 if ((state & runstate_mask_idle) == runstate_patt_idle)
941 static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t mode)
945 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &mode, sizeof(mode));
947 sr_err("Cannot configure run mode %d.", mode);
954 static int get_capture_info(const struct sr_dev_inst *sdi)
956 struct dev_context *devc;
958 uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */
959 const uint8_t *rdptr;
963 ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf));
965 sr_err("Cannot read capture info.");
970 devc->info.n_rep_packets = read_u32le_inc(&rdptr);
971 devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr);
972 devc->info.write_pos = read_u32le_inc(&rdptr);
974 sr_dbg("Capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x/%d.",
975 devc->info.n_rep_packets, devc->info.n_rep_packets,
976 devc->info.n_rep_packets_before_trigger,
977 devc->info.n_rep_packets_before_trigger,
978 devc->info.write_pos, devc->info.write_pos);
980 if (devc->info.n_rep_packets % devc->packets_per_chunk) {
981 sr_warn("Unexpected packets count %lu, not a multiple of %lu.",
982 (unsigned long)devc->info.n_rep_packets,
983 (unsigned long)devc->packets_per_chunk);
989 SR_PRIV int la2016_upload_firmware(const struct sr_dev_inst *sdi,
990 struct sr_context *sr_ctx, libusb_device *dev, gboolean skip_upload)
992 struct dev_context *devc;
997 devc = sdi ? sdi->priv : NULL;
998 if (!devc || !devc->usb_pid)
1000 pid = devc->usb_pid;
1002 fw = g_strdup_printf(MCU_FWFILE_FMT, pid);
1003 sr_info("USB PID %04hx, MCU firmware '%s'.", pid, fw);
1004 devc->mcu_firmware = g_strdup(fw);
1009 ret = ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw);
1017 static void LIBUSB_CALL receive_transfer(struct libusb_transfer *xfer);
1019 static void la2016_usbxfer_release_cb(gpointer p)
1021 struct libusb_transfer *xfer;
1024 g_free(xfer->buffer);
1025 libusb_free_transfer(xfer);
1028 static int la2016_usbxfer_release(const struct sr_dev_inst *sdi)
1030 struct dev_context *devc;
1032 devc = sdi ? sdi->priv : NULL;
1036 /* Release all USB transfers. */
1037 g_slist_free_full(devc->transfers, la2016_usbxfer_release_cb);
1038 devc->transfers = NULL;
1043 static int la2016_usbxfer_allocate(const struct sr_dev_inst *sdi)
1045 struct dev_context *devc;
1046 size_t bufsize, xfercount;
1048 struct libusb_transfer *xfer;
1050 devc = sdi ? sdi->priv : NULL;
1054 /* Transfers were already allocated before? */
1055 if (devc->transfers)
1059 * Allocate all USB transfers and their buffers. Arrange for a
1060 * buffer size which is within the device's capabilities, and
1061 * is a multiple of the USB endpoint's size, to make use of the
1062 * RAW_IO performance feature.
1064 * Implementation detail: The LA2016_USB_BUFSZ value happens
1065 * to match all those constraints. No additional arithmetics is
1066 * required in this location.
1068 bufsize = LA2016_USB_BUFSZ;
1069 xfercount = LA2016_USB_XFER_COUNT;
1070 while (xfercount--) {
1071 buffer = g_try_malloc(bufsize);
1073 sr_err("Cannot allocate USB transfer buffer.");
1074 return SR_ERR_MALLOC;
1076 xfer = libusb_alloc_transfer(0);
1078 sr_err("Cannot allocate USB transfer.");
1080 return SR_ERR_MALLOC;
1082 xfer->buffer = buffer;
1083 devc->transfers = g_slist_append(devc->transfers, xfer);
1085 devc->transfer_bufsize = bufsize;
1090 static int la2016_usbxfer_cancel_all(const struct sr_dev_inst *sdi)
1092 struct dev_context *devc;
1094 struct libusb_transfer *xfer;
1096 devc = sdi ? sdi->priv : NULL;
1100 /* Unconditionally cancel the transfer. Ignore errors. */
1101 for (l = devc->transfers; l; l = l->next) {
1105 libusb_cancel_transfer(xfer);
1111 static int la2016_usbxfer_resubmit(const struct sr_dev_inst *sdi,
1112 struct libusb_transfer *xfer)
1114 struct dev_context *devc;
1115 struct sr_usb_dev_inst *usb;
1116 libusb_transfer_cb_fn cb;
1119 devc = sdi ? sdi->priv : NULL;
1120 usb = sdi ? sdi->conn : NULL;
1127 cb = receive_transfer;
1128 libusb_fill_bulk_transfer(xfer, usb->devhdl,
1129 USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN,
1130 xfer->buffer, devc->transfer_bufsize,
1131 cb, (void *)sdi, CAPTURE_TIMEOUT_MS);
1132 ret = libusb_submit_transfer(xfer);
1134 sr_err("Cannot submit USB transfer: %s.",
1135 libusb_error_name(ret));
1142 static int la2016_usbxfer_submit_all(const struct sr_dev_inst *sdi)
1144 struct dev_context *devc;
1146 struct libusb_transfer *xfer;
1149 devc = sdi ? sdi->priv : NULL;
1153 for (l = devc->transfers; l; l = l->next) {
1157 ret = la2016_usbxfer_resubmit(sdi, xfer);
1165 SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi,
1168 struct dev_context *devc;
1174 ret = set_threshold_voltage(sdi, voltage);
1178 cmd = devc->continuous ? CAPTMODE_STREAM : CAPTMODE_TO_RAM;
1179 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd));
1181 sr_err("Cannot send command to stop sampling.");
1185 ret = set_trigger_config(sdi);
1189 ret = set_sample_config(sdi);
1196 SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi)
1198 struct dev_context *devc;
1203 ret = la2016_usbxfer_allocate(sdi);
1207 if (devc->continuous) {
1208 ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0);
1212 ret = la2016_usbxfer_submit_all(sdi);
1217 * Periodic receive callback will set runmode. This
1218 * activity MUST be close to data reception, a pause
1219 * between these steps breaks the stream's operation.
1222 ret = set_run_mode(sdi, RUNMODE_RUN);
1230 static int la2016_stop_acquisition(const struct sr_dev_inst *sdi)
1232 struct dev_context *devc;
1235 ret = set_run_mode(sdi, RUNMODE_HALT);
1240 if (devc->continuous)
1241 devc->download_finished = TRUE;
1246 SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi)
1250 ret = la2016_stop_acquisition(sdi);
1254 (void)la2016_usbxfer_cancel_all(sdi);
1259 static int la2016_start_download(const struct sr_dev_inst *sdi)
1261 struct dev_context *devc;
1263 uint8_t wrbuf[REG_SAMPLING - REG_BULK]; /* Width of REG_BULK. */
1268 ret = get_capture_info(sdi);
1272 devc->n_transfer_packets_to_read = devc->info.n_rep_packets;
1273 devc->n_transfer_packets_to_read /= devc->packets_per_chunk;
1274 devc->n_bytes_to_read = devc->n_transfer_packets_to_read;
1275 devc->n_bytes_to_read *= TRANSFER_PACKET_LENGTH;
1276 devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read;
1277 devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger;
1279 sr_dbg("Want to read %u xfer-packets starting from pos %" PRIu32 ".",
1280 devc->n_transfer_packets_to_read, devc->read_pos);
1282 ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0);
1284 sr_err("Cannot reset USB bulk state.");
1287 sr_dbg("Will read from 0x%08lx, 0x%08x bytes.",
1288 (unsigned long)devc->read_pos, devc->n_bytes_to_read);
1290 write_u32le_inc(&wrptr, devc->read_pos);
1291 write_u32le_inc(&wrptr, devc->n_bytes_to_read);
1292 ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf);
1294 sr_err("Cannot send USB bulk config.");
1298 ret = la2016_usbxfer_submit_all(sdi);
1300 sr_err("Cannot submit USB bulk transfers.");
1304 ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0);
1306 sr_err("Cannot start USB bulk transfers.");
1314 * A chunk (received via USB) contains a number of transfers (USB length
1315 * divided by 16) which contain a number of packets (5 per transfer) which
1316 * contain a number of samples (8bit repeat count per 16bit sample data).
1318 static void send_chunk(struct sr_dev_inst *sdi,
1319 const uint8_t *data_buffer, size_t data_length)
1321 struct dev_context *devc;
1322 size_t num_xfers, num_pkts;
1324 uint32_t sample_value;
1326 uint8_t sample_buff[sizeof(sample_value)];
1330 /* Ignore incoming USB data after complete sample data download. */
1331 if (devc->download_finished)
1334 if (devc->trigger_involved && !devc->trigger_marked && devc->info.n_rep_packets_before_trigger == 0) {
1335 feed_queue_logic_send_trigger(devc->feed_queue);
1336 devc->trigger_marked = TRUE;
1340 * Adjust the number of remaining bytes to read from the device
1341 * before the processing of the currently received chunk affects
1342 * the variable which holds the number of received bytes.
1344 if (data_length > devc->n_bytes_to_read)
1345 devc->n_bytes_to_read = 0;
1347 devc->n_bytes_to_read -= data_length;
1349 /* Process the received chunk of capture data. */
1352 num_xfers = data_length / TRANSFER_PACKET_LENGTH;
1353 while (num_xfers--) {
1354 num_pkts = devc->packets_per_chunk;
1355 while (num_pkts--) {
1357 /* TODO Verify 32channel layout. */
1358 if (devc->model->channel_count == 32)
1359 sample_value = read_u32le_inc(&rp);
1360 else if (devc->model->channel_count == 16)
1361 sample_value = read_u16le_inc(&rp);
1362 repetitions = read_u8_inc(&rp);
1364 devc->total_samples += repetitions;
1366 write_u32le(sample_buff, sample_value);
1367 feed_queue_logic_submit(devc->feed_queue,
1368 sample_buff, repetitions);
1369 sr_sw_limits_update_samples_read(&devc->sw_limits,
1372 if (devc->trigger_involved && !devc->trigger_marked) {
1373 if (!--devc->n_reps_until_trigger) {
1374 feed_queue_logic_send_trigger(devc->feed_queue);
1375 devc->trigger_marked = TRUE;
1376 sr_dbg("Trigger position after %" PRIu64 " samples, %.6fms.",
1377 devc->total_samples,
1378 (double)devc->total_samples / devc->samplerate * 1e3);
1382 (void)read_u8_inc(&rp); /* Skip sequence number. */
1386 * Check for several conditions which shall terminate the
1387 * capture data download: When the amount of capture data in
1388 * the device is exhausted. When the user specified samples
1389 * count limit is reached.
1391 if (!devc->n_bytes_to_read) {
1392 devc->download_finished = TRUE;
1394 sr_dbg("%" PRIu32 " more bytes to download from the device.",
1395 devc->n_bytes_to_read);
1397 if (!devc->download_finished && sr_sw_limits_check(&devc->sw_limits)) {
1398 sr_dbg("Acquisition limit reached.");
1399 devc->download_finished = TRUE;
1401 if (devc->download_finished) {
1402 sr_dbg("Download finished, flushing session feed queue.");
1403 feed_queue_logic_flush(devc->feed_queue);
1405 sr_dbg("Total samples after chunk: %" PRIu64 ".", devc->total_samples);
1409 * Process a chunk of capture data in streaming mode. The memory layout
1410 * is rather different from "normal mode" (see the send_chunk() routine
1411 * above). In streaming mode data is not compressed, and memory cells
1412 * neither contain raw sampled pin values at a given point in time. The
1413 * memory content needs transformation.
1414 * - The memory content can be seen as a sequence of memory cells.
1415 * - Each cell contains samples that correspond to the same channel.
1416 * The next cell contains samples for the next channel, etc.
1417 * - Only enabled channels occupy memory cells. Disabled channels are
1418 * not part of the capture data memory layout.
1419 * - The LSB bit position in a cell is the sample which was taken first
1420 * for this channel. Upper bit positions were taken later.
1422 * Implementor's note: This routine is inspired by convert_sample_data()
1423 * in the https://github.com/AlexUg/sigrok implementation. Which in turn
1424 * appears to have been derived from the saleae-logic16 sigrok driver.
1425 * The code is phrased conservatively to verify the layout as discussed
1426 * above, performance was not a priority. Operation was verified with an
1427 * LA2016 device. The memory layout of 32 channel models is yet to get
1430 static void stream_data(struct sr_dev_inst *sdi,
1431 const uint8_t *data_buffer, size_t data_length)
1433 struct dev_context *devc;
1434 struct stream_state_t *stream;
1437 uint32_t sample_value;
1438 uint8_t sample_buff[sizeof(sample_value)];
1443 stream = &devc->stream;
1445 /* Ignore incoming USB data after complete sample data download. */
1446 if (devc->download_finished)
1448 sr_dbg("Stream mode, got another chunk: %p, length %zu.",
1449 data_buffer, data_length);
1451 /* TODO Add soft trigger support when in stream mode? */
1454 * TODO Are memory cells always as wide as the channel count?
1455 * Are they always 16bits wide? Verify for 32 channel devices.
1457 bit_count = devc->model->channel_count;
1458 if (bit_count == 32) {
1459 data_length /= sizeof(uint32_t);
1460 } else if (bit_count == 16) {
1461 data_length /= sizeof(uint16_t);
1464 * Unhandled case. Acquisition should not start.
1465 * The statement silences the compiler.
1471 while (data_length--) {
1472 /* Get another entity. */
1473 if (bit_count == 32)
1474 sample_value = read_u32le_inc(&rp);
1475 else if (bit_count == 16)
1476 sample_value = read_u16le_inc(&rp);
1478 /* Map the entity's bits to a channel's samples. */
1479 ch_mask = stream->channel_masks[stream->channel_index];
1480 for (bit_idx = 0; bit_idx < bit_count; bit_idx++) {
1481 if (sample_value & (1UL << bit_idx))
1482 stream->sample_data[bit_idx] |= ch_mask;
1486 * Advance to the next channel. Submit a block of
1487 * samples when all channels' data was seen.
1489 stream->channel_index++;
1490 if (stream->channel_index != stream->enabled_count)
1492 for (bit_idx = 0; bit_idx < bit_count; bit_idx++) {
1493 sample_value = stream->sample_data[bit_idx];
1494 write_u32le(sample_buff, sample_value);
1495 feed_queue_logic_submit(devc->feed_queue, sample_buff, 1);
1497 sr_sw_limits_update_samples_read(&devc->sw_limits, bit_count);
1498 devc->total_samples += bit_count;
1499 memset(stream->sample_data, 0, sizeof(stream->sample_data));
1500 stream->channel_index = 0;
1504 * Need we count empty or failed USB transfers? This version
1505 * doesn't, assumes that timeouts are perfectly legal because
1506 * transfers are started early, and slow samplerates or trigger
1507 * support in hardware are plausible causes for empty transfers.
1509 * TODO Maybe a good condition would be (rather large) a timeout
1510 * after a previous capture data chunk was seen? So that stalled
1511 * streaming gets detected which _is_ an exceptional condition.
1512 * We have observed these when "runmode" is set early but bulk
1513 * transfers start late with a pause after setting the runmode.
1515 if (sr_sw_limits_check(&devc->sw_limits)) {
1516 sr_dbg("Acquisition end reached (sw limits).");
1517 devc->download_finished = TRUE;
1519 if (devc->download_finished) {
1520 sr_dbg("Stream receive done, flushing session feed queue.");
1521 feed_queue_logic_flush(devc->feed_queue);
1523 sr_dbg("Total samples after chunk: %" PRIu64 ".", devc->total_samples);
1526 static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer)
1528 struct sr_dev_inst *sdi;
1529 struct dev_context *devc;
1530 gboolean was_cancelled, device_gone;
1533 sdi = transfer->user_data;
1536 was_cancelled = transfer->status == LIBUSB_TRANSFER_CANCELLED;
1537 device_gone = transfer->status == LIBUSB_TRANSFER_NO_DEVICE;
1538 sr_dbg("receive_transfer(): status %s received %d bytes.",
1539 libusb_error_name(transfer->status), transfer->actual_length);
1541 sr_warn("Lost communication to USB device.");
1542 devc->download_finished = TRUE;
1547 * Implementation detail: A USB transfer timeout is not fatal
1548 * here. We just process whatever was received, empty input is
1549 * perfectly acceptable. Reaching (or exceeding) the sw limits
1550 * or exhausting the device's captured data will complete the
1551 * sample data download.
1553 if (devc->continuous)
1554 stream_data(sdi, transfer->buffer, transfer->actual_length);
1556 send_chunk(sdi, transfer->buffer, transfer->actual_length);
1559 * Re-submit completed transfers (regardless of timeout or
1560 * data reception), unless the transfer was cancelled when
1561 * the acquisition was terminated or has completed.
1563 if (!was_cancelled && !devc->download_finished) {
1564 ret = la2016_usbxfer_resubmit(sdi, transfer);
1567 devc->download_finished = TRUE;
1571 SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data)
1573 const struct sr_dev_inst *sdi;
1574 struct dev_context *devc;
1575 struct drv_context *drvc;
1584 drvc = sdi->driver->context;
1586 /* Arrange for the start of stream mode when requested. */
1587 if (devc->continuous && !devc->frame_begin_sent) {
1588 sr_dbg("First receive callback in stream mode.");
1589 devc->download_finished = FALSE;
1590 devc->trigger_marked = FALSE;
1591 devc->total_samples = 0;
1593 std_session_send_df_frame_begin(sdi);
1594 devc->frame_begin_sent = TRUE;
1596 ret = set_run_mode(sdi, RUNMODE_RUN);
1598 sr_err("Cannot set 'runmode' to 'run'.");
1602 ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0);
1604 sr_err("Cannot start USB bulk transfers.");
1607 sr_dbg("Stream data reception initiated.");
1611 * Wait for the acquisition to complete in hardware.
1612 * Periodically check a potentially configured msecs timeout.
1614 if (!devc->continuous && !devc->completion_seen) {
1615 if (!la2016_is_idle(sdi)) {
1616 if (sr_sw_limits_check(&devc->sw_limits)) {
1617 devc->sw_limits.limit_msec = 0;
1618 sr_dbg("Limit reached. Stopping acquisition.");
1619 la2016_stop_acquisition(sdi);
1621 /* Not yet ready for sample data download. */
1624 sr_dbg("Acquisition completion seen (hardware).");
1625 devc->sw_limits.limit_msec = 0;
1626 devc->completion_seen = TRUE;
1627 devc->download_finished = FALSE;
1628 devc->trigger_marked = FALSE;
1629 devc->total_samples = 0;
1631 la2016_dump_fpga_registers(sdi, "acquisition complete", 0, 0);
1633 /* Initiate the download of acquired sample data. */
1634 std_session_send_df_frame_begin(sdi);
1635 devc->frame_begin_sent = TRUE;
1636 ret = la2016_start_download(sdi);
1638 sr_err("Cannot start acquisition data download.");
1641 sr_dbg("Acquisition data download started.");
1646 /* Handle USB reception. Drives sample data download. */
1647 memset(&tv, 0, sizeof(tv));
1648 libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv);
1651 * Periodically flush acquisition data in streaming mode.
1652 * Without this nudge, previously received and accumulated data
1653 * keeps sitting in queues and is not seen by applications.
1655 if (devc->continuous && devc->stream.flush_period_ms) {
1656 uint64_t now, elapsed;
1657 now = g_get_monotonic_time();
1658 if (!devc->stream.last_flushed)
1659 devc->stream.last_flushed = now;
1660 elapsed = now - devc->stream.last_flushed;
1662 if (elapsed >= devc->stream.flush_period_ms) {
1663 sr_dbg("Stream mode, flushing.");
1664 feed_queue_logic_flush(devc->feed_queue);
1665 devc->stream.last_flushed = now;
1669 /* Postprocess completion of sample data download. */
1670 if (devc->download_finished) {
1671 sr_dbg("Download finished, post processing.");
1673 la2016_stop_acquisition(sdi);
1674 usb_source_remove(sdi->session, drvc->sr_ctx);
1676 la2016_usbxfer_cancel_all(sdi);
1677 memset(&tv, 0, sizeof(tv));
1678 libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv);
1680 feed_queue_logic_flush(devc->feed_queue);
1681 feed_queue_logic_free(devc->feed_queue);
1682 devc->feed_queue = NULL;
1683 if (devc->frame_begin_sent) {
1684 std_session_send_df_frame_end(sdi);
1685 devc->frame_begin_sent = FALSE;
1687 std_session_send_df_end(sdi);
1689 sr_dbg("Download finished, done post processing.");
1695 SR_PRIV int la2016_identify_device(const struct sr_dev_inst *sdi,
1696 gboolean show_message)
1698 struct dev_context *devc;
1699 uint8_t buf[8]; /* Larger size of manuf date and device type magic. */
1700 size_t rdoff, rdlen;
1701 const uint8_t *rdptr;
1702 uint8_t date_yy, date_mm;
1703 uint8_t dinv_yy, dinv_mm;
1704 uint8_t magic, magic2;
1706 const struct kingst_model *model;
1712 * Four EEPROM bytes at offset 0x20 are the manufacturing date,
1713 * year and month in BCD format, followed by inverted values for
1714 * consistency checks. For example bytes 20 04 df fb translate
1715 * to 2020-04. This information can help identify the vintage of
1716 * devices when unknown magic numbers are seen.
1719 rdlen = 4 * sizeof(uint8_t);
1720 ret = ctrl_in(sdi, CMD_EEPROM, rdoff, 0, buf, rdlen);
1721 if (ret != SR_OK && !show_message) {
1722 /* Non-fatal weak attempt during probe. Not worth logging. */
1723 sr_dbg("Cannot access EEPROM.");
1725 } else if (ret != SR_OK) {
1726 /* Failed attempt in regular use. Non-fatal. Worth logging. */
1727 sr_err("Cannot read manufacture date in EEPROM.");
1729 if (sr_log_loglevel_get() >= SR_LOG_SPEW) {
1731 txt = sr_hexdump_new(buf, rdlen);
1732 sr_spew("Manufacture date bytes %s.", txt->str);
1733 sr_hexdump_free(txt);
1736 date_yy = read_u8_inc(&rdptr);
1737 date_mm = read_u8_inc(&rdptr);
1738 dinv_yy = read_u8_inc(&rdptr);
1739 dinv_mm = read_u8_inc(&rdptr);
1740 sr_info("Manufacture date: 20%02hx-%02hx.", date_yy, date_mm);
1741 if ((date_mm ^ dinv_mm) != 0xff || (date_yy ^ dinv_yy) != 0xff)
1742 sr_warn("Manufacture date fails checksum test.");
1746 * Several Kingst logic analyzer devices share the same USB VID
1747 * and PID. The product ID determines which MCU firmware to load.
1748 * The MCU firmware provides access to EEPROM content which then
1749 * allows to identify the device model. Which in turn determines
1750 * which FPGA bitstream to load. Eight bytes at offset 0x08 are
1753 * EEPROM content for model identification is kept redundantly
1754 * in memory. The values are stored in verbatim and in inverted
1755 * form, multiple copies are kept at different offsets. Example
1766 * Exclusively inspecting the magic byte appears to be sufficient,
1767 * other fields seem to be 'don't care'.
1769 * magic 2 == LA2016 using "kingst-la2016-fpga.bitstream"
1770 * magic 3 == LA1016 using "kingst-la1016-fpga.bitstream"
1771 * magic 8 == LA2016a using "kingst-la2016a1-fpga.bitstream"
1772 * (latest v1.3.0 PCB, perhaps others)
1773 * magic 9 == LA1016a using "kingst-la1016a1-fpga.bitstream"
1774 * (latest v1.3.0 PCB, perhaps others)
1776 * When EEPROM content does not match the hardware configuration
1777 * (the board layout), the software may load but yield incorrect
1778 * results (like swapped channels). The FPGA bitstream itself
1779 * will authenticate with IC U10 and fail when its capabilities
1780 * do not match the hardware model. An LA1016 won't become a
1781 * LA2016 by faking its EEPROM content.
1783 devc->identify_magic = 0;
1785 rdlen = 8 * sizeof(uint8_t);
1786 ret = ctrl_in(sdi, CMD_EEPROM, rdoff, 0, &buf, rdlen);
1788 sr_err("Cannot read EEPROM device identifier bytes.");
1791 if (sr_log_loglevel_get() >= SR_LOG_SPEW) {
1793 txt = sr_hexdump_new(buf, rdlen);
1794 sr_spew("EEPROM magic bytes %s.", txt->str);
1795 sr_hexdump_free(txt);
1799 if ((buf[0] ^ buf[1]) == 0xff && (buf[2] ^ buf[3]) == 0xff) {
1800 /* Primary copy of magic passes complement check (4 bytes). */
1803 sr_dbg("Using primary magic %hhu (%hhu).", magic, magic2);
1804 } else if ((buf[4] ^ buf[5]) == 0xff && (buf[6] ^ buf[7]) == 0xff) {
1805 /* Backup copy of magic passes complement check (4 bytes). */
1808 sr_dbg("Using secondary magic %hhu (%hhu).", magic, magic2);
1809 } else if ((buf[0] ^ buf[1]) == 0xff) {
1810 /* Primary copy of magic passes complement check (2 bytes). */
1812 sr_dbg("Using primary magic %hhu.", magic);
1813 } else if ((buf[4] ^ buf[5]) == 0xff) {
1814 /* Backup copy of magic passes complement check (2 bytes). */
1816 sr_dbg("Using secondary magic %hhu.", magic);
1818 sr_err("Cannot find consistent device type identification.");
1820 devc->identify_magic = magic;
1821 devc->identify_magic2 = magic2;
1824 for (model_idx = 0; model_idx < ARRAY_SIZE(models); model_idx++) {
1825 model = &models[model_idx];
1826 if (model->magic != magic)
1828 if (model->magic2 && model->magic2 != magic2)
1830 devc->model = model;
1831 sr_info("Model '%s', %zu channels, max %" PRIu64 "MHz.",
1832 model->name, model->channel_count,
1833 model->samplerate / SR_MHZ(1));
1834 devc->fpga_bitstream = g_strdup_printf(FPGA_FWFILE_FMT,
1836 sr_info("FPGA bitstream file '%s'.", devc->fpga_bitstream);
1837 if (!model->channel_count) {
1838 sr_warn("Device lacks logic channels. Not supported.");
1844 sr_err("Cannot identify as one of the supported models.");
1851 SR_PRIV int la2016_init_hardware(const struct sr_dev_inst *sdi)
1853 struct dev_context *devc;
1854 const char *bitstream_fn;
1859 bitstream_fn = devc ? devc->fpga_bitstream : "";
1861 ret = check_fpga_bitstream(sdi);
1863 ret = upload_fpga_bitstream(sdi, bitstream_fn);
1865 sr_err("Cannot upload FPGA bitstream.");
1869 ret = enable_fpga_bitstream(sdi);
1871 sr_err("Cannot enable FPGA bitstream after upload.");
1875 state = run_state(sdi);
1876 if ((state & 0xfff0) != 0x85e0) {
1877 sr_warn("Unexpected run state, want 0x85eX, got 0x%04x.", state);
1880 ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0);
1882 sr_err("Cannot reset USB bulk transfer.");
1886 sr_dbg("Device should be initialized.");
1891 SR_PRIV int la2016_deinit_hardware(const struct sr_dev_inst *sdi)
1895 ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0);
1897 sr_err("Cannot deinitialize device's FPGA.");
1904 SR_PRIV void la2016_release_resources(const struct sr_dev_inst *sdi)
1906 (void)la2016_usbxfer_release(sdi);
1909 SR_PRIV int la2016_write_pwm_config(const struct sr_dev_inst *sdi, size_t idx)
1911 return set_pwm_config(sdi, idx);