2 * This file is part of the libsigrok project.
4 * Copyright (C) 2013 Uwe Hermann <uwe@hermann-uwe.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
24 * Logic level thresholds.
26 * For each of the two channel groups (1-4 and 5-9), the logic level
27 * threshold can be set independently.
29 * The threshold can be set to values that are usable for systems with
30 * different voltage levels, e.g. for 1.8V or 3.3V systems.
32 * The actual threshold value is always the middle of the values below.
33 * E.g. for a system voltage level of 1.8V, the threshold is at 0.9V. That
34 * means that values <= 0.9V are considered to be a logic 0/low, and
35 * values > 0.9V are considered to be a logic 1/high.
37 * - 1.2V system: threshold = 0.6V
38 * - 1.5V system: threshold = 0.75V
39 * - 1.8V system: threshold = 0.9V
40 * - 2.8V system: threshold = 1.4V
41 * - 3.3V system: threshold = 1.65V
43 #define THRESHOLD_1_2V_SYSTEM 0x2e
44 #define THRESHOLD_1_5V_SYSTEM 0x39
45 #define THRESHOLD_1_8V_SYSTEM 0x45
46 #define THRESHOLD_2_8V_SYSTEM 0x6c
47 #define THRESHOLD_3_3V_SYSTEM 0x7f
49 static int scanaplus_write(struct dev_context *devc, uint8_t *buf, int size)
54 /* Note: Caller checks devc, devc->ftdic, buf, size. */
56 s = g_string_sized_new(100);
57 g_string_printf(s, "Writing %d bytes: ", size);
58 for (i = 0; i < size; i++)
59 g_string_append_printf(s, "0x%02x ", buf[i]);
60 sr_spew("%s", s->str);
61 g_string_free(s, TRUE);
63 bytes_written = ftdi_write_data(devc->ftdic, buf, size);
64 if (bytes_written < 0) {
65 sr_err("Failed to write FTDI data (%d): %s.",
66 bytes_written, ftdi_get_error_string(devc->ftdic));
67 } else if (bytes_written != size) {
68 sr_err("FTDI write error, only %d/%d bytes written: %s.",
69 bytes_written, size, ftdi_get_error_string(devc->ftdic));
75 SR_PRIV int scanaplus_close(struct dev_context *devc)
79 /* Note: Caller checks devc and devc->ftdic. */
81 if ((ret = ftdi_usb_close(devc->ftdic)) < 0) {
82 sr_err("Failed to close FTDI device (%d): %s.",
83 ret, ftdi_get_error_string(devc->ftdic));
90 static void scanaplus_uncompress_block(struct dev_context *devc,
94 uint8_t num_samples, low, high;
96 for (i = 0; i < num_bytes; i += 2) {
97 num_samples = devc->compressed_buf[i + 0] >> 1;
99 low = devc->compressed_buf[i + 0] & (1 << 0);
100 high = devc->compressed_buf[i + 1];
102 for (j = 0; j < num_samples; j++) {
103 devc->sample_buf[devc->bytes_received++] = high;
104 devc->sample_buf[devc->bytes_received++] = low;
109 static void send_samples(const struct sr_dev_inst *sdi, uint64_t samples_to_send)
111 struct sr_datafeed_packet packet;
112 struct sr_datafeed_logic logic;
113 struct dev_context *devc;
117 sr_spew("Sending %" PRIu64 " samples.", samples_to_send);
119 packet.type = SR_DF_LOGIC;
120 packet.payload = &logic;
121 logic.length = samples_to_send * 2;
122 logic.unitsize = 2; /* We need 2 bytes for 9 channels. */
123 logic.data = devc->sample_buf;
124 sr_session_send(sdi, &packet);
126 devc->samples_sent += samples_to_send;
127 devc->bytes_received -= samples_to_send * 2;
130 SR_PRIV int scanaplus_get_device_id(struct dev_context *devc)
135 /* FTDI EEPROM indices 16+17 contain the 3 device ID bytes. */
136 if ((ret = ftdi_read_eeprom_location(devc->ftdic, 16, &val1)) < 0) {
137 sr_err("Failed to read EEPROM index 16 (%d): %s.",
138 ret, ftdi_get_error_string(devc->ftdic));
141 if ((ret = ftdi_read_eeprom_location(devc->ftdic, 17, &val2)) < 0) {
142 sr_err("Failed to read EEPROM index 17 (%d): %s.",
143 ret, ftdi_get_error_string(devc->ftdic));
148 * Note: Bit 7 of the three bytes must not be used, apparently.
150 * Even though the three bits can be either 0 or 1 (we've seen both
151 * in actual ScanaPLUS devices), the device ID as sent to the FPGA
152 * has bit 7 of each byte zero'd out.
154 * It is unknown whether bit 7 of these bytes has any meaning,
155 * whether it's used somewhere, or whether it can be simply ignored.
157 devc->devid[0] = ((val1 >> 0) & 0xff) & ~(1 << 7);
158 devc->devid[1] = ((val1 >> 8) & 0xff) & ~(1 << 7);
159 devc->devid[2] = ((val2 >> 0) & 0xff) & ~(1 << 7);
164 static int scanaplus_clear_device_id(struct dev_context *devc)
170 if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
175 if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
180 if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
186 static int scanaplus_send_device_id(struct dev_context *devc)
191 buf[1] = devc->devid[0];
192 if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
196 buf[1] = devc->devid[1];
197 if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
201 buf[1] = devc->devid[2];
202 if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
208 SR_PRIV int scanaplus_init(struct dev_context *devc)
215 if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
222 if (scanaplus_write(devc, (uint8_t *)&buf, 4) < 0)
227 if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
232 if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
243 if (scanaplus_write(devc, (uint8_t *)&buf, 8) < 0)
246 for (i = 0; i < 57; i++) {
249 if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
254 if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
258 if (scanaplus_send_device_id(devc) < 0)
263 if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
269 SR_PRIV int scanaplus_start_acquisition(struct dev_context *devc)
273 /* Threshold and differential channel settings not yet implemented. */
276 buf[1] = 0x7f; /* Logic level threshold for channels 1-4. */
278 buf[3] = 0x7f; /* Logic level threshold for channels 5-9. */
279 if (scanaplus_write(devc, (uint8_t *)&buf, 4) < 0)
283 buf[1] = 0x40; /* Special config of channels 5/6 and 7/8. */
284 /* 0x40: normal, 0x50: ch56 diff, 0x48: ch78 diff, 0x58: ch5678 diff */
285 if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
288 if (scanaplus_clear_device_id(devc) < 0)
291 if (scanaplus_send_device_id(devc) < 0)
297 SR_PRIV int scanaplus_receive_data(int fd, int revents, void *cb_data)
300 struct sr_dev_inst *sdi;
301 struct dev_context *devc;
307 if (!(sdi = cb_data))
310 if (!(devc = sdi->priv))
316 /* Get a block of data. */
317 bytes_read = ftdi_read_data(devc->ftdic, devc->compressed_buf,
318 COMPRESSED_BUF_SIZE);
319 if (bytes_read < 0) {
320 sr_err("Failed to read FTDI data (%d): %s.",
321 bytes_read, ftdi_get_error_string(devc->ftdic));
322 sr_dev_acquisition_stop(sdi);
325 if (bytes_read == 0) {
326 sr_spew("Received 0 bytes, nothing to do.");
331 * After a ScanaPLUS acquisition starts, a bunch of samples will be
332 * returned as all-zero, no matter which signals are actually present
333 * on the channels. This is probably due to the FPGA reconfiguring some
334 * of its internal state/config during this time.
336 * As far as we know there is apparently no way for the PC-side to
337 * know when this "reconfiguration" starts or ends. The FTDI chip
338 * will return all-zero "dummy" samples during this time, which is
339 * indistinguishable from actual all-zero samples.
341 * We currently simply ignore the first 64kB of data after an
342 * acquisition starts. Empirical tests have shown that the
343 * "reconfigure" time is a lot less than that usually.
345 if (devc->compressed_bytes_ignored < COMPRESSED_BUF_SIZE) {
346 /* Ignore the first 64kB of data of every acquisition. */
347 sr_spew("Ignoring first 64kB chunk of data.");
348 devc->compressed_bytes_ignored += COMPRESSED_BUF_SIZE;
352 /* TODO: Handle bytes_read which is not a multiple of 2? */
353 scanaplus_uncompress_block(devc, bytes_read);
355 n = devc->samples_sent + (devc->bytes_received / 2);
356 max = (SR_MHZ(100) / 1000) * devc->limit_msec;
358 if (devc->limit_samples && (n >= devc->limit_samples)) {
359 send_samples(sdi, devc->limit_samples - devc->samples_sent);
360 sr_info("Requested number of samples reached.");
361 sr_dev_acquisition_stop(sdi);
363 } else if (devc->limit_msec && (n >= max)) {
364 send_samples(sdi, max - devc->samples_sent);
365 sr_info("Requested time limit reached.");
366 sr_dev_acquisition_stop(sdi);
369 send_samples(sdi, devc->bytes_received / 2);