2 * This file is part of the libsigrok project.
4 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
5 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 3 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <sys/types.h>
27 #include <glib/gstdio.h>
31 #define FW_BUFSIZE 4096
32 int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
37 struct sr_usb_dev_inst *usb;
38 int chunksize, result, ret;
42 sr_dbg("Uploading FPGA firmware at %s.", filename);
45 if (stat(filename, &st) < 0) {
46 sr_err("Unable to upload FPGA firmware: %s", strerror(errno));
50 /* Tell the device firmware is coming. */
51 if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
52 LIBUSB_ENDPOINT_OUT, DS_CMD_FPGA_FW, 0x0000, 0x0000,
53 NULL, 0, 3000)) < 0) {
54 sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
57 buf = g_malloc(FW_BUFSIZE);
59 if ((fw = g_fopen(filename, "rb")) == NULL) {
60 sr_err("Unable to open %s for reading: %s.", filename, strerror(errno));
64 /* Give the FX2 time to get ready for FPGA firmware upload. */
70 if ((chunksize = fread(buf, 1, FW_BUFSIZE, fw)) == 0)
73 if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
74 buf, chunksize, &transferred, 1000)) < 0) {
75 sr_err("Unable to configure FPGA firmware: %s.",
76 libusb_error_name(ret));
81 sr_spew("Uploaded %d/%d bytes.", sum, st.st_size);
83 if (transferred != chunksize) {
84 sr_err("Short transfer while uploading FPGA firmware.");
92 sr_dbg("FPGA firmware upload done.");
97 int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
99 struct dev_context *devc;
100 struct sr_usb_dev_inst *usb;
101 struct dslogic_mode mode;
106 mode.sample_delay_h = mode.sample_delay_l = 0;
107 if (devc->sample_wide)
108 mode.flags |= DS_START_FLAGS_SAMPLE_WIDE;
111 ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
112 LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
113 (unsigned char *)&mode, sizeof(mode), 3000);
115 sr_err("Failed to send start command: %s.", libusb_error_name(ret));
122 int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
124 struct sr_usb_dev_inst *usb;
125 struct dslogic_mode mode;
128 mode.flags = DS_START_FLAGS_STOP;
129 mode.sample_delay_h = mode.sample_delay_l = 0;
132 ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
133 LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
134 (unsigned char *)&mode, sizeof(struct dslogic_mode), 3000);
136 sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
143 int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
145 struct dev_context *devc;
146 struct sr_usb_dev_inst *usb;
148 struct dslogic_fpga_config cfg;
151 int transferred, len, ret;
153 sr_dbg("Configuring FPGA.");
157 WL32(&cfg.sync, DS_CFG_START);
158 WL16(&cfg.mode_header, DS_CFG_MODE);
159 WL32(&cfg.divider_header, DS_CFG_DIVIDER);
160 WL32(&cfg.count_header, DS_CFG_COUNT);
161 WL32(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
162 WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
163 WL32(&cfg.trig_adp_header, DS_CFG_TRIG_ADP);
164 WL32(&cfg.trig_sda_header, DS_CFG_TRIG_SDA);
165 WL32(&cfg.trig_mask0_header, DS_CFG_TRIG_MASK0);
166 WL32(&cfg.trig_mask1_header, DS_CFG_TRIG_MASK1);
167 WL32(&cfg.trig_value0_header, DS_CFG_TRIG_VALUE0);
168 WL32(&cfg.trig_value1_header, DS_CFG_TRIG_VALUE1);
169 WL32(&cfg.trig_edge0_header, DS_CFG_TRIG_EDGE0);
170 WL32(&cfg.trig_edge1_header, DS_CFG_TRIG_EDGE1);
171 WL32(&cfg.trig_count0_header, DS_CFG_TRIG_COUNT0);
172 WL32(&cfg.trig_count1_header, DS_CFG_TRIG_COUNT1);
173 WL32(&cfg.trig_logic0_header, DS_CFG_TRIG_LOGIC0);
174 WL32(&cfg.trig_logic1_header, DS_CFG_TRIG_LOGIC1);
175 WL32(&cfg.end_sync, DS_CFG_END);
177 /* Pass in the length of a fixed-size struct. Really. */
178 len = sizeof(struct dslogic_fpga_config) / 2;
180 c[1] = (len >> 8) & 0xff;
181 c[2] = (len >> 16) & 0xff;
183 ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
184 LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
187 sr_err("Failed to send FPGA configure command: %s.", libusb_error_name(ret));
192 * 15 1 = internal test mode
193 * 14 1 = external test mode
194 * 13 1 = loopback test mode
197 * 6 1 = samplerate 400MHz
198 * 5 1 = samplerate 200MHz or analog mode
199 * 4 0 = logic, 1 = dso or analog
201 * 1 0 = internal clock, 1 = external clock
202 * 0 1 = trigger enabled
205 if (devc->dslogic_mode == DS_OP_INTERNAL_TEST)
207 else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST)
209 else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
211 if (devc->dslogic_external_clock)
213 WL16(&cfg.mode, v16);
215 v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate);
216 WL32(&cfg.divider, v32);
217 WL32(&cfg.count, devc->limit_samples);
219 len = sizeof(struct dslogic_fpga_config);
220 ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
221 (unsigned char *)&cfg, len,
223 if (ret < 0 || transferred != len) {
224 sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));