2 * This file is part of the libsigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
7 * Copyright (C) 2020 Gerhard Sittig <gerhard.sittig@gmx.net>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 3 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #ifndef LIBSIGROK_HARDWARE_ASIX_SIGMA_PROTOCOL_H
24 #define LIBSIGROK_HARDWARE_ASIX_SIGMA_PROTOCOL_H
31 #include <libsigrok/libsigrok.h>
32 #include "libsigrok-internal.h"
34 #define LOG_PREFIX "asix-sigma"
37 * Triggers are not working in this implementation. Stop claiming
38 * support for the feature which effectively is not available, until
39 * the implementation got fixed. Yet keep the code in place and allow
40 * developers to turn on this switch during development.
42 #define ASIX_SIGMA_WITH_TRIGGER 0
44 /* Experimental support for OMEGA (scan only, operation is ENOIMPL). */
45 #define ASIX_WITH_OMEGA 0
47 #define USB_VENDOR_ASIX 0xa600
48 #define USB_PRODUCT_SIGMA 0xa000
49 #define USB_PRODUCT_OMEGA 0xa004
51 enum asix_device_type {
58 * FPGA commands are 8bits wide. The upper nibble is a command opcode,
59 * the lower nibble can carry operand values. 8bit register addresses
60 * and 8bit data values get communicated in two steps.
63 /* Register access. */
64 #define REG_ADDR_LOW (0x0 << 4)
65 #define REG_ADDR_HIGH (0x1 << 4)
66 #define REG_DATA_LOW (0x2 << 4)
67 #define REG_DATA_HIGH_WRITE (0x3 << 4)
68 #define REG_READ_ADDR (0x4 << 4)
69 #define REG_ADDR_ADJUST (1 << 0) /* Auto adjust register address. */
70 #define REG_ADDR_DOWN (1 << 1) /* 1 decrement, 0 increment. */
71 #define REG_ADDR_INC (REG_ADDR_ADJUST)
72 #define REG_ADDR_DEC (REG_ADDR_ADJUST | REG_ADDR_DOWN)
74 /* Sample memory access. */
75 #define REG_DRAM_WAIT_ACK (0x5 << 4) /* Wait for completion. */
76 #define REG_DRAM_BLOCK (0x6 << 4) /* DRAM to BRAM, plus bank select. */
77 #define REG_DRAM_BLOCK_BEGIN (0x8 << 4) /* Read first BRAM bytes. */
78 #define REG_DRAM_BLOCK_DATA (0xa << 4) /* Read full BRAM block. */
79 #define REG_DRAM_SEL_N (0x1 << 4) /* Bank select, added to 6/8/a. */
80 #define REG_DRAM_SEL_BOOL(b) ((b) ? REG_DRAM_SEL_N : 0)
83 * Registers at a specific address can have different meanings depending
84 * on whether data is read or written. This is why direction is part of
85 * the programming language identifiers.
87 * The vendor documentation suggests that in addition to the first 16
88 * register addresses which implement the logic analyzer's feature set,
89 * there are 240 more registers in the 16 to 255 address range which
90 * are available to applications and plugin features. Can libsigrok's
91 * asix-sigma driver store configuration data there, to avoid expensive
92 * operations (think: firmware re-load).
95 enum sigma_write_register {
96 WRITE_CLOCK_SELECT = 0,
97 WRITE_TRIGGER_SELECT = 1,
98 WRITE_TRIGGER_SELECT2 = 2,
101 WRITE_POST_TRIGGER = 5,
102 WRITE_TRIGGER_OPTION = 6,
104 /* Unassigned register locations. */
108 enum sigma_read_register {
110 READ_TRIGGER_POS_LOW = 1,
111 READ_TRIGGER_POS_HIGH = 2,
112 READ_TRIGGER_POS_UP = 3,
113 READ_STOP_POS_LOW = 4,
114 READ_STOP_POS_HIGH = 5,
115 READ_STOP_POS_UP = 6,
117 READ_PIN_CHANGE_LOW = 8,
118 READ_PIN_CHANGE_HIGH = 9,
119 READ_BLOCK_LAST_TS_LOW = 10,
120 READ_BLOCK_LAST_TS_HIGH = 11,
121 READ_BLOCK_TS_OVERRUN = 12,
123 /* Unassigned register location. */
127 #define HI4(b) (((b) >> 4) & 0x0f)
128 #define LO4(b) (((b) >> 0) & 0x0f)
130 #define BIT_MASK(l) ((1UL << (l)) - 1)
132 #define TRGSEL_SELC_MASK BIT_MASK(2)
133 #define TRGSEL_SELC_SHIFT 0
134 #define TRGSEL_SELPRESC_MASK BIT_MASK(4)
135 #define TRGSEL_SELPRESC_SHIFT 4
136 #define TRGSEL_SELINC_MASK BIT_MASK(2)
137 #define TRGSEL_SELINC_SHIFT 0
138 #define TRGSEL_SELRES_MASK BIT_MASK(2)
139 #define TRGSEL_SELRES_SHIFT 2
140 #define TRGSEL_SELA_MASK BIT_MASK(2)
141 #define TRGSEL_SELA_SHIFT 4
142 #define TRGSEL_SELB_MASK BIT_MASK(2)
143 #define TRGSEL_SELB_SHIFT 6
145 #define TRGSEL2_PINS_MASK (0x07 << 0)
146 #define TRGSEL2_PINPOL_RISE (1 << 3)
147 #define TRGSEL2_LUT_ADDR_MASK (0x0f << 0)
148 #define TRGSEL2_LUT_WRITE (1 << 4)
149 #define TRGSEL2_RESET (1 << 5)
150 #define TRGSEL2_LEDSEL0 (1 << 6)
151 #define TRGSEL2_LEDSEL1 (1 << 7)
153 /* WRITE_MODE register fields. */
154 #define WMR_SDRAMWRITEEN (1 << 0)
155 #define WMR_SDRAMREADEN (1 << 1)
156 #define WMR_TRGRES (1 << 2)
157 #define WMR_TRGEN (1 << 3)
158 #define WMR_FORCESTOP (1 << 4)
159 #define WMR_TRGSW (1 << 5)
160 /* not used: bit position 6 */
161 #define WMR_SDRAMINIT (1 << 7)
163 /* READ_MODE register fields. */
164 #define RMR_SDRAMWRITEEN (1 << 0)
165 #define RMR_SDRAMREADEN (1 << 1)
166 /* not used: bit position 2 */
167 #define RMR_TRGEN (1 << 3)
168 #define RMR_ROUND (1 << 4)
169 #define RMR_TRIGGERED (1 << 5)
170 #define RMR_POSTTRIGGERED (1 << 6)
171 /* not used: bit position 7 */
174 * Trigger options. First and second write are similar, but _some_
175 * positions change their meaning.
177 #define TRGOPT_TRGIEN (1 << 7)
178 #define TRGOPT_TRGOEN (1 << 6)
179 #define TRGOPT_TRGOINEN (1 << 5) /* 1st write */
180 #define TRGOPT_TRGINEG TRGOPT1_TRGOINEN /* 2nd write */
181 #define TRGOPT_TRGOEVNTEN (1 << 4) /* 1st write */
182 #define TRGOPT_TRGOPIN TRGOPT1_TRGOEVNTEN /* 2nd write */
183 #define TRGOPT_TRGOOUTEN (1 << 3) /* 1st write */
184 #define TRGOPT_TRGOLONG TRGOPT1_TRGOOUTEN /* 2nd write */
185 #define TRGOPT_TRGOUTR_OUT (1 << 1)
186 #define TRGOPT_TRGOUTR_EN (1 << 0)
187 #define TRGOPT_CLEAR_MASK (TRGOPT_TRGOINEN | TRGOPT_TRGOEVNTEN | TRGOPT_TRGOOUTEN)
190 * Layout of the sample data DRAM, which will be downloaded to the PC:
192 * Sigma memory is organized in 32K rows. Each row contains 64 clusters.
193 * Each cluster contains a timestamp (16bit) and 7 events (16bits each).
194 * Events contain 16 bits of sample data (potentially taken at multiple
195 * sample points, see below).
197 * Total memory size is 32K x 64 x 8 x 2 bytes == 32 MiB (256 Mbit). The
198 * size of a memory row is 1024 bytes. Assuming x16 organization of the
199 * memory array, address specs (sample count, trigger position) are kept
200 * in 24bit entities. The upper 15 bit address the "row", the lower 9 bit
201 * refer to the "event" within the row. Because there is one timestamp for
202 * seven events each, one memory row can hold up to 64x7 == 448 events.
204 * Sample data is represented in 16bit quantities. The first sample in
205 * the cluster corresponds to the cluster's timestamp. Each next sample
206 * corresponds to the timestamp + 1, timestamp + 2, etc (the distance is
207 * one sample period, according to the samplerate). In the absence of
208 * pin level changes, no data is provided (RLE compression). A cluster
209 * is enforced for each 64K ticks of the timestamp, to reliably handle
210 * rollover and determine the next timestamp of the next cluster.
212 * For samplerates up to 50MHz, an event directly translates to one set
213 * of sample data at a single sample point, spanning up to 16 channels.
214 * For samplerates of 100MHz, there is one 16 bit entity for each 20ns
215 * period (50MHz rate). The 16 bit memory contains 2 samples of up to
216 * 8 channels. Bits of multiple samples are interleaved. For samplerates
217 * of 200MHz one 16bit entity contains 4 samples of up to 4 channels,
221 #define ROW_COUNT 32768
222 #define ROW_LENGTH_BYTES 1024
223 #define ROW_LENGTH_U16 (ROW_LENGTH_BYTES / sizeof(uint16_t))
224 #define ROW_SHIFT 9 /* log2 of u16 count */
225 #define ROW_MASK ((1UL << ROW_SHIFT) - 1)
226 #define EVENTS_PER_CLUSTER 7
227 #define CLUSTERS_PER_ROW (ROW_LENGTH_U16 / (1 + EVENTS_PER_CLUSTER))
228 #define EVENTS_PER_ROW (CLUSTERS_PER_ROW * EVENTS_PER_CLUSTER)
230 struct sigma_dram_line {
231 struct sigma_dram_cluster {
233 uint16_t samples[EVENTS_PER_CLUSTER];
234 } cluster[CLUSTERS_PER_ROW];
237 /* The effect of all these are still a bit unclear. */
238 struct triggerinout {
239 uint8_t trgout_resistor_enable : 1;
240 uint8_t trgout_resistor_pullup : 1;
241 uint8_t reserved1 : 1;
242 uint8_t trgout_bytrigger : 1;
243 uint8_t trgout_byevent : 1;
244 uint8_t trgout_bytriggerin : 1;
245 uint8_t reserved2 : 2;
247 /* Should be set same as the first two */
248 uint8_t trgout_resistor_enable2 : 1;
249 uint8_t trgout_resistor_pullup2 : 1;
251 uint8_t reserved3 : 1;
252 uint8_t trgout_long : 1;
253 uint8_t trgout_pin : 1; /* Use 1k resistor. Pullup? */
254 uint8_t trgin_negate : 1;
255 uint8_t trgout_enable : 1;
256 uint8_t trgin_enable : 1;
260 /* The actual LUTs. */
261 uint16_t m0d[4], m1d[4], m2d[4];
262 uint16_t m3, m3s, m4;
264 /* Parameters should be sent as a single register write. */
267 uint8_t selpresc : 6;
279 /* Trigger configuration */
280 struct sigma_trigger {
281 /* Only two channels can be used in mask. */
283 uint16_t fallingmask;
285 /* Simple trigger support (<= 50 MHz). */
287 uint16_t simplevalue;
289 /* TODO: Advanced trigger support (boolean expressions). */
292 /* Events for trigger operation. */
304 /* Logical functions for trigger operation. */
316 SIGMA_UNINITIALIZED = 0,
327 enum sigma_firmware_idx {
336 struct submit_buffer;
343 enum asix_device_type type;
346 struct ftdi_context ctx;
347 gboolean is_open, must_close;
350 struct sr_sw_limits cfg_limits; /* Configured limits (user specified). */
351 struct sr_sw_limits acq_limits; /* Acquisition limits (internal use). */
352 struct sr_sw_limits feed_limits; /* Datafeed limits (internal use). */
353 enum sigma_firmware_idx firmware_idx;
355 int samples_per_event;
356 uint64_t capture_ratio;
357 struct sigma_trigger trigger;
359 struct sigma_state state;
360 struct submit_buffer *buffer;
363 /* "Automatic" and forced USB connection open/close support. */
364 SR_PRIV int sigma_check_open(const struct sr_dev_inst *sdi);
365 SR_PRIV int sigma_check_close(struct dev_context *devc);
366 SR_PRIV int sigma_force_open(const struct sr_dev_inst *sdi);
367 SR_PRIV int sigma_force_close(struct dev_context *devc);
369 /* Send register content (simple and complex) to the hardware. */
370 SR_PRIV int sigma_write_register(struct dev_context *devc,
371 uint8_t reg, uint8_t *data, size_t len);
372 SR_PRIV int sigma_set_register(struct dev_context *devc,
373 uint8_t reg, uint8_t value);
374 SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc,
375 struct triggerlut *lut);
377 /* Samplerate constraints check, get/set/list helpers. */
378 SR_PRIV int sigma_normalize_samplerate(uint64_t want_rate, uint64_t *have_rate);
379 SR_PRIV uint64_t sigma_get_samplerate(const struct sr_dev_inst *sdi);
380 SR_PRIV GVariant *sigma_get_samplerates_list(void);
382 /* Preparation of data acquisition, spec conversion, hardware configuration. */
383 SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi);
384 SR_PRIV int sigma_set_acquire_timeout(struct dev_context *devc);
385 SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi);
386 SR_PRIV int sigma_build_basic_trigger(struct dev_context *devc,
387 struct triggerlut *lut);
389 /* Callback to periodically drive acuisition progress. */
390 SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data);