2 * This file is part of the libsigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
30 * The ASIX Sigma supports arbitrary integer frequency divider in
31 * the 50MHz mode. The divider is in range 1...256 , allowing for
32 * very precise sampling rate selection. This driver supports only
33 * a subset of the sampling rates.
35 SR_PRIV const uint64_t samplerates[] = {
36 SR_KHZ(200), /* div=250 */
37 SR_KHZ(250), /* div=200 */
38 SR_KHZ(500), /* div=100 */
39 SR_MHZ(1), /* div=50 */
40 SR_MHZ(5), /* div=10 */
41 SR_MHZ(10), /* div=5 */
42 SR_MHZ(25), /* div=2 */
43 SR_MHZ(50), /* div=1 */
44 SR_MHZ(100), /* Special FW needed */
45 SR_MHZ(200), /* Special FW needed */
48 SR_PRIV const size_t samplerates_count = ARRAY_SIZE(samplerates);
50 static const char sigma_firmware_files[][24] = {
51 /* 50 MHz, supports 8 bit fractions */
57 /* Synchronous clock from pin */
58 "asix-sigma-50sync.fw",
59 /* Frequency counter */
60 "asix-sigma-phasor.fw",
63 static int sigma_read(void *buf, size_t size, struct dev_context *devc)
67 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
69 sr_err("ftdi_read_data failed: %s",
70 ftdi_get_error_string(&devc->ftdic));
76 static int sigma_write(void *buf, size_t size, struct dev_context *devc)
80 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
82 sr_err("ftdi_write_data failed: %s",
83 ftdi_get_error_string(&devc->ftdic));
84 } else if ((size_t) ret != size) {
85 sr_err("ftdi_write_data did not complete write.");
92 * NOTE: We chose the buffer size to be large enough to hold any write to the
93 * device. We still print a message just in case.
95 SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
96 struct dev_context *devc)
102 if ((2 * len + 2) > sizeof(buf)) {
103 sr_err("Attempted to write %zu bytes, but buffer is too small.",
108 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
109 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
111 for (i = 0; i < len; i++) {
112 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
113 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
116 return sigma_write(buf, idx, devc);
119 SR_PRIV int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
121 return sigma_write_register(reg, &value, 1, devc);
124 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
125 struct dev_context *devc)
129 buf[0] = REG_ADDR_LOW | (reg & 0xf);
130 buf[1] = REG_ADDR_HIGH | (reg >> 4);
131 buf[2] = REG_READ_ADDR;
133 sigma_write(buf, sizeof(buf), devc);
135 return sigma_read(data, len, devc);
138 static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
142 if (1 != sigma_read_register(reg, &value, 1, devc)) {
143 sr_err("sigma_get_register: 1 byte expected");
150 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
151 struct dev_context *devc)
154 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
156 REG_READ_ADDR | NEXT_REG,
157 REG_READ_ADDR | NEXT_REG,
158 REG_READ_ADDR | NEXT_REG,
159 REG_READ_ADDR | NEXT_REG,
160 REG_READ_ADDR | NEXT_REG,
161 REG_READ_ADDR | NEXT_REG,
165 sigma_write(buf, sizeof(buf), devc);
167 sigma_read(result, sizeof(result), devc);
169 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
170 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
172 /* Not really sure why this must be done, but according to spec. */
173 if ((--*stoppos & 0x1ff) == 0x1ff)
176 if ((*--triggerpos & 0x1ff) == 0x1ff)
182 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
183 uint8_t *data, struct dev_context *devc)
189 /* Send the startchunk. Index start with 1. */
191 buf[idx++] = startchunk >> 8;
192 buf[idx++] = startchunk & 0xff;
193 sigma_write_register(WRITE_MEMROW, buf, idx, devc);
197 buf[idx++] = REG_DRAM_BLOCK;
198 buf[idx++] = REG_DRAM_WAIT_ACK;
200 for (i = 0; i < numchunks; i++) {
201 /* Alternate bit to copy from DRAM to cache. */
202 if (i != (numchunks - 1))
203 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
205 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
207 if (i != (numchunks - 1))
208 buf[idx++] = REG_DRAM_WAIT_ACK;
211 sigma_write(buf, idx, devc);
213 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
216 /* Upload trigger look-up tables to Sigma. */
217 SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
223 /* Transpose the table and send to Sigma. */
224 for (i = 0; i < 16; i++) {
229 if (lut->m2d[0] & bit)
231 if (lut->m2d[1] & bit)
233 if (lut->m2d[2] & bit)
235 if (lut->m2d[3] & bit)
245 if (lut->m0d[0] & bit)
247 if (lut->m0d[1] & bit)
249 if (lut->m0d[2] & bit)
251 if (lut->m0d[3] & bit)
254 if (lut->m1d[0] & bit)
256 if (lut->m1d[1] & bit)
258 if (lut->m1d[2] & bit)
260 if (lut->m1d[3] & bit)
263 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
265 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
268 /* Send the parameters */
269 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
270 sizeof(lut->params), devc);
275 SR_PRIV void sigma_clear_helper(void *priv)
277 struct dev_context *devc;
281 ftdi_deinit(&devc->ftdic);
285 * Configure the FPGA for bitbang mode.
286 * This sequence is documented in section 2. of the ASIX Sigma programming
287 * manual. This sequence is necessary to configure the FPGA in the Sigma
288 * into Bitbang mode, in which it can be programmed with the firmware.
290 static int sigma_fpga_init_bitbang(struct dev_context *devc)
292 uint8_t suicide[] = {
293 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
295 uint8_t init_array[] = {
296 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
299 int i, ret, timeout = (10 * 1000);
302 /* Section 2. part 1), do the FPGA suicide. */
303 sigma_write(suicide, sizeof(suicide), devc);
304 sigma_write(suicide, sizeof(suicide), devc);
305 sigma_write(suicide, sizeof(suicide), devc);
306 sigma_write(suicide, sizeof(suicide), devc);
308 /* Section 2. part 2), do pulse on D1. */
309 sigma_write(init_array, sizeof(init_array), devc);
310 ftdi_usb_purge_buffers(&devc->ftdic);
312 /* Wait until the FPGA asserts D6/INIT_B. */
313 for (i = 0; i < timeout; i++) {
314 ret = sigma_read(&data, 1, devc);
317 /* Test if pin D6 got asserted. */
320 /* The D6 was not asserted yet, wait a bit. */
324 return SR_ERR_TIMEOUT;
328 * Configure the FPGA for logic-analyzer mode.
330 static int sigma_fpga_init_la(struct dev_context *devc)
332 /* Initialize the logic analyzer mode. */
333 uint8_t mode_regval = WMR_SDRAMINIT;
334 uint8_t logic_mode_start[] = {
335 REG_ADDR_LOW | (READ_ID & 0xf),
336 REG_ADDR_HIGH | (READ_ID >> 4),
337 REG_READ_ADDR, /* Read ID register. */
339 REG_ADDR_LOW | (WRITE_TEST & 0xf),
341 REG_DATA_HIGH_WRITE | 0x5,
342 REG_READ_ADDR, /* Read scratch register. */
345 REG_DATA_HIGH_WRITE | 0xa,
346 REG_READ_ADDR, /* Read scratch register. */
348 REG_ADDR_LOW | (WRITE_MODE & 0xf),
349 REG_DATA_LOW | (mode_regval & 0xf),
350 REG_DATA_HIGH_WRITE | (mode_regval >> 4),
356 /* Initialize the logic analyzer mode. */
357 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
359 /* Expect a 3 byte reply since we issued three READ requests. */
360 ret = sigma_read(result, 3, devc);
364 if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa)
369 sr_err("Configuration failed. Invalid reply received.");
374 * Read the firmware from a file and transform it into a series of bitbang
375 * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d
376 * by the caller of this function.
378 static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name,
379 uint8_t **bb_cmd, gsize *bb_cmd_size)
381 size_t i, file_size, bb_size;
383 uint8_t *bb_stream, *bbs;
388 /* Retrieve the on-disk firmware file content. */
389 firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE,
390 name, &file_size, 256 * 1024);
394 /* Unscramble the file content (XOR with "random" sequence). */
396 for (i = 0; i < file_size; i++) {
397 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
398 firmware[i] ^= imm & 0xff;
402 * Generate a sequence of bitbang samples. With two samples per
403 * FPGA configuration bit, providing the level for the DIN signal
404 * as well as two edges for CCLK. See Xilinx UG332 for details
405 * ("slave serial" mode).
407 * Note that CCLK is inverted in hardware. That's why the
408 * respective bit is first set and then cleared in the bitbang
409 * sample sets. So that the DIN level will be stable when the
410 * data gets sampled at the rising CCLK edge, and the signals'
411 * setup time constraint will be met.
413 * The caller will put the FPGA into download mode, will send
414 * the bitbang samples, and release the allocated memory.
416 bb_size = file_size * 8 * 2;
417 bb_stream = (uint8_t *)g_try_malloc(bb_size);
419 sr_err("%s: Failed to allocate bitbang stream", __func__);
424 for (i = 0; i < file_size; i++) {
425 for (bit = 7; bit >= 0; bit--) {
426 v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00;
432 /* The transformation completed successfully, return the result. */
434 *bb_cmd_size = bb_size;
441 static int upload_firmware(struct sr_context *ctx,
442 int firmware_idx, struct dev_context *devc)
448 const char *firmware;
449 struct ftdi_context *ftdic;
451 /* Avoid downloading the same firmware multiple times. */
452 firmware = sigma_firmware_files[firmware_idx];
453 if (devc->cur_firmware == firmware_idx) {
454 sr_info("Not uploading firmware file '%s' again.", firmware);
458 /* Make sure it's an ASIX SIGMA. */
459 ftdic = &devc->ftdic;
460 ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT,
461 USB_DESCRIPTION, NULL);
463 sr_err("ftdi_usb_open failed: %s",
464 ftdi_get_error_string(ftdic));
468 ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG);
470 sr_err("ftdi_set_bitmode failed: %s",
471 ftdi_get_error_string(ftdic));
475 /* Four times the speed of sigmalogan - Works well. */
476 ret = ftdi_set_baudrate(ftdic, 750 * 1000);
478 sr_err("ftdi_set_baudrate failed: %s",
479 ftdi_get_error_string(ftdic));
483 /* Initialize the FPGA for firmware upload. */
484 ret = sigma_fpga_init_bitbang(devc);
488 /* Prepare firmware. */
489 ret = sigma_fw_2_bitbang(ctx, firmware, &buf, &buf_size);
491 sr_err("An error occurred while reading the firmware: %s",
496 /* Upload firmware. */
497 sr_info("Uploading firmware file '%s'.", firmware);
498 sigma_write(buf, buf_size, devc);
502 ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET);
504 sr_err("ftdi_set_bitmode failed: %s",
505 ftdi_get_error_string(ftdic));
509 ftdi_usb_purge_buffers(ftdic);
511 /* Discard garbage. */
512 while (sigma_read(&pins, 1, devc) == 1)
515 /* Initialize the FPGA for logic-analyzer mode. */
516 ret = sigma_fpga_init_la(devc);
520 devc->cur_firmware = firmware_idx;
522 sr_info("Firmware uploaded.");
528 * Sigma doesn't support limiting the number of samples, so we have to
529 * translate the number and the samplerate to an elapsed time.
531 * In addition we need to ensure that the last data cluster has passed
532 * the hardware pipeline, and became available to the PC side. With RLE
533 * compression up to 327ms could pass before another cluster accumulates
534 * at 200kHz samplerate when input pins don't change.
536 SR_PRIV uint64_t sigma_limit_samples_to_msec(const struct dev_context *devc,
537 uint64_t limit_samples)
540 uint64_t worst_cluster_time_ms;
542 limit_msec = limit_samples * 1000 / devc->cur_samplerate;
543 worst_cluster_time_ms = 65536 * 1000 / devc->cur_samplerate;
545 * One cluster time is not enough to flush pipeline when sampling
546 * grounded pins with 1 sample limit at 200kHz. Hence the 2* fix.
548 return limit_msec + 2 * worst_cluster_time_ms;
551 SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
553 struct dev_context *devc;
554 struct drv_context *drvc;
559 drvc = sdi->driver->context;
562 /* Reject rates that are not in the list of supported rates. */
563 for (i = 0; i < samplerates_count; i++) {
564 if (samplerates[i] == samplerate)
567 if (i >= samplerates_count || samplerates[i] == 0)
568 return SR_ERR_SAMPLERATE;
571 * Depending on the samplerates of 200/100/50- MHz, specific
572 * firmware is required and higher rates might limit the set
573 * of available channels.
575 if (samplerate <= SR_MHZ(50)) {
576 ret = upload_firmware(drvc->sr_ctx, 0, devc);
577 devc->num_channels = 16;
578 } else if (samplerate == SR_MHZ(100)) {
579 ret = upload_firmware(drvc->sr_ctx, 1, devc);
580 devc->num_channels = 8;
581 } else if (samplerate == SR_MHZ(200)) {
582 ret = upload_firmware(drvc->sr_ctx, 2, devc);
583 devc->num_channels = 4;
587 * Derive the sample period from the sample rate as well as the
588 * number of samples that the device will communicate within
589 * an "event" (memory organization internal to the device).
592 devc->cur_samplerate = samplerate;
593 devc->period_ps = 1000000000000ULL / samplerate;
594 devc->samples_per_event = 16 / devc->num_channels;
595 devc->state.state = SIGMA_IDLE;
599 * Support for "limit_samples" is implemented by stopping
600 * acquisition after a corresponding period of time.
601 * Re-calculate that period of time, in case the limit is
602 * set first and the samplerate gets (re-)configured later.
604 if (ret == SR_OK && devc->limit_samples) {
606 msecs = sigma_limit_samples_to_msec(devc, devc->limit_samples);
607 devc->limit_msec = msecs;
614 * In 100 and 200 MHz mode, only a single pin rising/falling can be
615 * set as trigger. In other modes, two rising/falling triggers can be set,
616 * in addition to value/mask trigger for any number of channels.
618 * The Sigma supports complex triggers using boolean expressions, but this
619 * has not been implemented yet.
621 SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi)
623 struct dev_context *devc;
624 struct sr_trigger *trigger;
625 struct sr_trigger_stage *stage;
626 struct sr_trigger_match *match;
628 int channelbit, trigger_set;
631 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
632 if (!(trigger = sr_session_trigger_get(sdi->session)))
636 for (l = trigger->stages; l; l = l->next) {
638 for (m = stage->matches; m; m = m->next) {
640 if (!match->channel->enabled)
641 /* Ignore disabled channels with a trigger. */
643 channelbit = 1 << (match->channel->index);
644 if (devc->cur_samplerate >= SR_MHZ(100)) {
645 /* Fast trigger support. */
647 sr_err("Only a single pin trigger is "
648 "supported in 100 and 200MHz mode.");
651 if (match->match == SR_TRIGGER_FALLING)
652 devc->trigger.fallingmask |= channelbit;
653 else if (match->match == SR_TRIGGER_RISING)
654 devc->trigger.risingmask |= channelbit;
656 sr_err("Only rising/falling trigger is "
657 "supported in 100 and 200MHz mode.");
663 /* Simple trigger support (event). */
664 if (match->match == SR_TRIGGER_ONE) {
665 devc->trigger.simplevalue |= channelbit;
666 devc->trigger.simplemask |= channelbit;
668 else if (match->match == SR_TRIGGER_ZERO) {
669 devc->trigger.simplevalue &= ~channelbit;
670 devc->trigger.simplemask |= channelbit;
672 else if (match->match == SR_TRIGGER_FALLING) {
673 devc->trigger.fallingmask |= channelbit;
676 else if (match->match == SR_TRIGGER_RISING) {
677 devc->trigger.risingmask |= channelbit;
682 * Actually, Sigma supports 2 rising/falling triggers,
683 * but they are ORed and the current trigger syntax
684 * does not permit ORed triggers.
686 if (trigger_set > 1) {
687 sr_err("Only 1 rising/falling trigger "
699 /* Software trigger to determine exact trigger position. */
700 static int get_trigger_offset(uint8_t *samples, uint16_t last_sample,
701 struct sigma_trigger *t)
706 for (i = 0; i < 8; i++) {
708 last_sample = sample;
709 sample = samples[2 * i] | (samples[2 * i + 1] << 8);
711 /* Simple triggers. */
712 if ((sample & t->simplemask) != t->simplevalue)
716 if (((last_sample & t->risingmask) != 0) ||
717 ((sample & t->risingmask) != t->risingmask))
721 if ((last_sample & t->fallingmask) != t->fallingmask ||
722 (sample & t->fallingmask) != 0)
728 /* If we did not match, return original trigger pos. */
733 * Return the timestamp of "DRAM cluster".
735 static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster)
737 return (cluster->timestamp_hi << 8) | cluster->timestamp_lo;
741 * Return one 16bit data entity of a DRAM cluster at the specified index.
743 static uint16_t sigma_dram_cluster_data(struct sigma_dram_cluster *cl, int idx)
748 sample |= cl->samples[idx].sample_lo << 0;
749 sample |= cl->samples[idx].sample_hi << 8;
750 sample = (sample >> 8) | (sample << 8);
755 * Deinterlace sample data that was retrieved at 100MHz samplerate.
756 * One 16bit item contains two samples of 8bits each. The bits of
757 * multiple samples are interleaved.
759 static uint16_t sigma_deinterlace_100mhz_data(uint16_t indata, int idx)
765 outdata |= (indata >> (0 * 2 - 0)) & (1 << 0);
766 outdata |= (indata >> (1 * 2 - 1)) & (1 << 1);
767 outdata |= (indata >> (2 * 2 - 2)) & (1 << 2);
768 outdata |= (indata >> (3 * 2 - 3)) & (1 << 3);
769 outdata |= (indata >> (4 * 2 - 4)) & (1 << 4);
770 outdata |= (indata >> (5 * 2 - 5)) & (1 << 5);
771 outdata |= (indata >> (6 * 2 - 6)) & (1 << 6);
772 outdata |= (indata >> (7 * 2 - 7)) & (1 << 7);
777 * Deinterlace sample data that was retrieved at 200MHz samplerate.
778 * One 16bit item contains four samples of 4bits each. The bits of
779 * multiple samples are interleaved.
781 static uint16_t sigma_deinterlace_200mhz_data(uint16_t indata, int idx)
787 outdata |= (indata >> (0 * 4 - 0)) & (1 << 0);
788 outdata |= (indata >> (1 * 4 - 1)) & (1 << 1);
789 outdata |= (indata >> (2 * 4 - 2)) & (1 << 2);
790 outdata |= (indata >> (3 * 4 - 3)) & (1 << 3);
794 static void store_sr_sample(uint8_t *samples, int idx, uint16_t data)
796 samples[2 * idx + 0] = (data >> 0) & 0xff;
797 samples[2 * idx + 1] = (data >> 8) & 0xff;
801 * Local wrapper around sr_session_send() calls. Make sure to not send
802 * more samples to the session's datafeed than what was requested by a
803 * previously configured (optional) sample count.
805 static void sigma_session_send(struct sr_dev_inst *sdi,
806 struct sr_datafeed_packet *packet)
808 struct dev_context *devc;
809 struct sr_datafeed_logic *logic;
813 if (devc->limit_samples) {
814 logic = (void *)packet->payload;
815 send_now = logic->length / logic->unitsize;
816 if (devc->sent_samples + send_now > devc->limit_samples) {
817 send_now = devc->limit_samples - devc->sent_samples;
818 logic->length = send_now * logic->unitsize;
822 devc->sent_samples += send_now;
825 sr_session_send(sdi, packet);
829 * This size translates to: event count (1K events per cluster), times
830 * the sample width (unitsize, 16bits per event), times the maximum
831 * number of samples per event.
833 #define SAMPLES_BUFFER_SIZE (1024 * 2 * 4)
835 static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster,
836 unsigned int events_in_cluster,
837 unsigned int triggered,
838 struct sr_dev_inst *sdi)
840 struct dev_context *devc = sdi->priv;
841 struct sigma_state *ss = &devc->state;
842 struct sr_datafeed_packet packet;
843 struct sr_datafeed_logic logic;
844 uint16_t tsdiff, ts, sample, item16;
845 uint8_t samples[SAMPLES_BUFFER_SIZE];
847 size_t send_count, trig_count;
851 ts = sigma_dram_cluster_ts(dram_cluster);
852 tsdiff = ts - ss->lastts;
853 ss->lastts = ts + EVENTS_PER_CLUSTER;
855 packet.type = SR_DF_LOGIC;
856 packet.payload = &logic;
858 logic.data = samples;
861 * First of all, send Sigrok a copy of the last sample from
862 * previous cluster as many times as needed to make up for
863 * the differential characteristics of data we get from the
864 * Sigma. Sigrok needs one sample of data per period.
866 * One DRAM cluster contains a timestamp and seven samples,
867 * the units of timestamp are "devc->period_ps" , the first
868 * sample in the cluster happens at the time of the timestamp
869 * and the remaining samples happen at timestamp +1...+6 .
871 for (ts = 0; ts < tsdiff; ts++) {
873 store_sr_sample(samples, i, ss->lastsample);
876 * If we have 1024 samples ready or we're at the
877 * end of submitting the padding samples, submit
878 * the packet to Sigrok. Since constant data is
879 * sent, duplication of data for rates above 50MHz
882 if ((i == 1023) || (ts == tsdiff - 1)) {
883 logic.length = (i + 1) * logic.unitsize;
884 for (j = 0; j < devc->samples_per_event; j++)
885 sigma_session_send(sdi, &packet);
890 * Parse the samples in current cluster and prepare them
891 * to be submitted to Sigrok. Cope with memory layouts that
892 * vary with the samplerate.
894 send_ptr = &samples[0];
897 for (i = 0; i < events_in_cluster; i++) {
898 item16 = sigma_dram_cluster_data(dram_cluster, i);
899 if (devc->cur_samplerate == SR_MHZ(200)) {
900 sample = sigma_deinterlace_200mhz_data(item16, 0);
901 store_sr_sample(samples, send_count++, sample);
902 sample = sigma_deinterlace_200mhz_data(item16, 1);
903 store_sr_sample(samples, send_count++, sample);
904 sample = sigma_deinterlace_200mhz_data(item16, 2);
905 store_sr_sample(samples, send_count++, sample);
906 sample = sigma_deinterlace_200mhz_data(item16, 3);
907 store_sr_sample(samples, send_count++, sample);
908 } else if (devc->cur_samplerate == SR_MHZ(100)) {
909 sample = sigma_deinterlace_100mhz_data(item16, 0);
910 store_sr_sample(samples, send_count++, sample);
911 sample = sigma_deinterlace_100mhz_data(item16, 1);
912 store_sr_sample(samples, send_count++, sample);
915 store_sr_sample(samples, send_count++, sample);
920 * If a trigger position applies, then provide the datafeed with
921 * the first part of data up to that position, then send the
924 int trigger_offset = 0;
927 * Trigger is not always accurate to sample because of
928 * pipeline delay. However, it always triggers before
929 * the actual event. We therefore look at the next
930 * samples to pinpoint the exact position of the trigger.
932 trigger_offset = get_trigger_offset(samples,
933 ss->lastsample, &devc->trigger);
935 if (trigger_offset > 0) {
936 trig_count = trigger_offset * devc->samples_per_event;
937 packet.type = SR_DF_LOGIC;
938 logic.length = trig_count * logic.unitsize;
939 sigma_session_send(sdi, &packet);
940 send_ptr += trig_count * logic.unitsize;
941 send_count -= trig_count;
944 /* Only send trigger if explicitly enabled. */
945 if (devc->use_triggers) {
946 packet.type = SR_DF_TRIGGER;
947 sr_session_send(sdi, &packet);
952 * Send the data after the trigger, or all of the received data
953 * if no trigger position applies.
956 packet.type = SR_DF_LOGIC;
957 logic.length = send_count * logic.unitsize;
958 logic.data = send_ptr;
959 sigma_session_send(sdi, &packet);
962 ss->lastsample = sample;
966 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
967 * Each event is 20ns apart, and can contain multiple samples.
969 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
970 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
971 * For 50 MHz and below, events contain one sample for each channel,
972 * spread 20 ns apart.
974 static int decode_chunk_ts(struct sigma_dram_line *dram_line,
975 uint16_t events_in_line,
976 uint32_t trigger_event,
977 struct sr_dev_inst *sdi)
979 struct sigma_dram_cluster *dram_cluster;
980 struct dev_context *devc;
981 unsigned int clusters_in_line;
982 unsigned int events_in_cluster;
984 uint32_t trigger_cluster, triggered;
987 clusters_in_line = events_in_line;
988 clusters_in_line += EVENTS_PER_CLUSTER - 1;
989 clusters_in_line /= EVENTS_PER_CLUSTER;
990 trigger_cluster = ~0;
993 /* Check if trigger is in this chunk. */
994 if (trigger_event < (64 * 7)) {
995 if (devc->cur_samplerate <= SR_MHZ(50)) {
996 trigger_event -= MIN(EVENTS_PER_CLUSTER - 1,
1000 /* Find in which cluster the trigger occurred. */
1001 trigger_cluster = trigger_event / EVENTS_PER_CLUSTER;
1004 /* For each full DRAM cluster. */
1005 for (i = 0; i < clusters_in_line; i++) {
1006 dram_cluster = &dram_line->cluster[i];
1008 /* The last cluster might not be full. */
1009 if ((i == clusters_in_line - 1) &&
1010 (events_in_line % EVENTS_PER_CLUSTER)) {
1011 events_in_cluster = events_in_line % EVENTS_PER_CLUSTER;
1013 events_in_cluster = EVENTS_PER_CLUSTER;
1016 triggered = (i == trigger_cluster);
1017 sigma_decode_dram_cluster(dram_cluster, events_in_cluster,
1024 static int download_capture(struct sr_dev_inst *sdi)
1026 const uint32_t chunks_per_read = 32;
1028 struct dev_context *devc;
1029 struct sigma_dram_line *dram_line;
1031 uint32_t stoppos, triggerpos;
1034 uint32_t dl_lines_total, dl_lines_curr, dl_lines_done;
1035 uint32_t dl_events_in_line;
1036 uint32_t trg_line, trg_event;
1039 dl_events_in_line = 64 * 7;
1043 dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line));
1047 sr_info("Downloading sample data.");
1050 * Ask the hardware to stop data acquisition. Reception of the
1051 * FORCESTOP request makes the hardware "disable RLE" (store
1052 * clusters to DRAM regardless of whether pin state changes) and
1053 * raise the POSTTRIGGERED flag.
1055 sigma_set_register(WRITE_MODE, WMR_FORCESTOP | WMR_SDRAMWRITEEN, devc);
1057 modestatus = sigma_get_register(READ_MODE, devc);
1058 } while (!(modestatus & RMR_POSTTRIGGERED));
1060 /* Set SDRAM Read Enable. */
1061 sigma_set_register(WRITE_MODE, WMR_SDRAMREADEN, devc);
1063 /* Get the current position. */
1064 sigma_read_pos(&stoppos, &triggerpos, devc);
1066 /* Check if trigger has fired. */
1067 modestatus = sigma_get_register(READ_MODE, devc);
1068 if (modestatus & RMR_TRIGGERED) {
1069 trg_line = triggerpos >> 9;
1070 trg_event = triggerpos & 0x1ff;
1073 devc->sent_samples = 0;
1076 * Determine how many 1024b "DRAM lines" do we need to read from the
1077 * Sigma so we have a complete set of samples. Note that the last
1078 * line can be only partial, containing less than 64 clusters.
1080 dl_lines_total = (stoppos >> 9) + 1;
1084 while (dl_lines_total > dl_lines_done) {
1085 /* We can download only up-to 32 DRAM lines in one go! */
1086 dl_lines_curr = MIN(chunks_per_read, dl_lines_total);
1088 bufsz = sigma_read_dram(dl_lines_done, dl_lines_curr,
1089 (uint8_t *)dram_line, devc);
1090 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1093 /* This is the first DRAM line, so find the initial timestamp. */
1094 if (dl_lines_done == 0) {
1095 devc->state.lastts =
1096 sigma_dram_cluster_ts(&dram_line[0].cluster[0]);
1097 devc->state.lastsample = 0;
1100 for (i = 0; i < dl_lines_curr; i++) {
1101 uint32_t trigger_event = ~0;
1102 /* The last "DRAM line" can be only partially full. */
1103 if (dl_lines_done + i == dl_lines_total - 1)
1104 dl_events_in_line = stoppos & 0x1ff;
1106 /* Test if the trigger happened on this line. */
1107 if (dl_lines_done + i == trg_line)
1108 trigger_event = trg_event;
1110 decode_chunk_ts(dram_line + i, dl_events_in_line,
1111 trigger_event, sdi);
1114 dl_lines_done += dl_lines_curr;
1117 std_session_send_df_end(sdi);
1119 sdi->driver->dev_acquisition_stop(sdi);
1127 * Handle the Sigma when in CAPTURE mode. This function checks:
1128 * - Sampling time ended
1129 * - DRAM capacity overflow
1130 * This function triggers download of the samples from Sigma
1131 * in case either of the above conditions is true.
1133 static int sigma_capture_mode(struct sr_dev_inst *sdi)
1135 struct dev_context *devc;
1136 uint64_t running_msec;
1138 uint32_t stoppos, triggerpos;
1142 /* Check if the selected sampling duration passed. */
1143 gettimeofday(&tv, 0);
1144 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1145 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1146 if (running_msec >= devc->limit_msec)
1147 return download_capture(sdi);
1149 /* Get the position in DRAM to which the FPGA is writing now. */
1150 sigma_read_pos(&stoppos, &triggerpos, devc);
1151 /* Test if DRAM is full and if so, download the data. */
1152 if ((stoppos >> 9) == 32767)
1153 return download_capture(sdi);
1158 SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data)
1160 struct sr_dev_inst *sdi;
1161 struct dev_context *devc;
1169 if (devc->state.state == SIGMA_IDLE)
1172 if (devc->state.state == SIGMA_CAPTURE)
1173 return sigma_capture_mode(sdi);
1178 /* Build a LUT entry used by the trigger functions. */
1179 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1183 /* For each quad channel. */
1184 for (i = 0; i < 4; i++) {
1187 /* For each bit in LUT. */
1188 for (j = 0; j < 16; j++)
1190 /* For each channel in quad. */
1191 for (k = 0; k < 4; k++) {
1192 bit = 1 << (i * 4 + k);
1194 /* Set bit in entry */
1195 if ((mask & bit) && ((!(value & bit)) !=
1197 entry[i] &= ~(1 << j);
1202 /* Add a logical function to LUT mask. */
1203 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1204 int index, int neg, uint16_t *mask)
1207 int x[2][2], tmp, a, b, aset, bset, rset;
1209 memset(x, 0, 4 * sizeof(int));
1211 /* Trigger detect condition. */
1241 case OP_NOTRISEFALL:
1247 /* Transpose if neg is set. */
1249 for (i = 0; i < 2; i++) {
1250 for (j = 0; j < 2; j++) {
1252 x[i][j] = x[1 - i][1 - j];
1253 x[1 - i][1 - j] = tmp;
1258 /* Update mask with function. */
1259 for (i = 0; i < 16; i++) {
1260 a = (i >> (2 * index + 0)) & 1;
1261 b = (i >> (2 * index + 1)) & 1;
1263 aset = (*mask >> i) & 1;
1267 if (func == FUNC_AND || func == FUNC_NAND)
1269 else if (func == FUNC_OR || func == FUNC_NOR)
1271 else if (func == FUNC_XOR || func == FUNC_NXOR)
1274 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1285 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1286 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1287 * set at any time, but a full mask and value can be set (0/1).
1289 SR_PRIV int sigma_build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1292 uint16_t masks[2] = { 0, 0 };
1294 memset(lut, 0, sizeof(struct triggerlut));
1296 /* Constant for simple triggers. */
1299 /* Value/mask trigger support. */
1300 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1303 /* Rise/fall trigger support. */
1304 for (i = 0, j = 0; i < 16; i++) {
1305 if (devc->trigger.risingmask & (1 << i) ||
1306 devc->trigger.fallingmask & (1 << i))
1307 masks[j++] = 1 << i;
1310 build_lut_entry(masks[0], masks[0], lut->m0d);
1311 build_lut_entry(masks[1], masks[1], lut->m1d);
1313 /* Add glue logic */
1314 if (masks[0] || masks[1]) {
1315 /* Transition trigger. */
1316 if (masks[0] & devc->trigger.risingmask)
1317 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1318 if (masks[0] & devc->trigger.fallingmask)
1319 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1320 if (masks[1] & devc->trigger.risingmask)
1321 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1322 if (masks[1] & devc->trigger.fallingmask)
1323 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1325 /* Only value/mask trigger. */
1329 /* Triggertype: event. */
1330 lut->params.selres = 3;