2 * This file is part of the libsigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
30 * The ASIX Sigma supports arbitrary integer frequency divider in
31 * the 50MHz mode. The divider is in range 1...256 , allowing for
32 * very precise sampling rate selection. This driver supports only
33 * a subset of the sampling rates.
35 SR_PRIV const uint64_t samplerates[] = {
36 SR_KHZ(200), /* div=250 */
37 SR_KHZ(250), /* div=200 */
38 SR_KHZ(500), /* div=100 */
39 SR_MHZ(1), /* div=50 */
40 SR_MHZ(5), /* div=10 */
41 SR_MHZ(10), /* div=5 */
42 SR_MHZ(25), /* div=2 */
43 SR_MHZ(50), /* div=1 */
44 SR_MHZ(100), /* Special FW needed */
45 SR_MHZ(200), /* Special FW needed */
48 SR_PRIV const size_t samplerates_count = ARRAY_SIZE(samplerates);
50 static const char sigma_firmware_files[][24] = {
51 /* 50 MHz, supports 8 bit fractions */
57 /* Synchronous clock from pin */
58 "asix-sigma-50sync.fw",
59 /* Frequency counter */
60 "asix-sigma-phasor.fw",
63 static int sigma_read(void *buf, size_t size, struct dev_context *devc)
67 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
69 sr_err("ftdi_read_data failed: %s",
70 ftdi_get_error_string(&devc->ftdic));
76 static int sigma_write(void *buf, size_t size, struct dev_context *devc)
80 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
82 sr_err("ftdi_write_data failed: %s",
83 ftdi_get_error_string(&devc->ftdic));
84 } else if ((size_t) ret != size) {
85 sr_err("ftdi_write_data did not complete write.");
92 * NOTE: We chose the buffer size to be large enough to hold any write to the
93 * device. We still print a message just in case.
95 SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
96 struct dev_context *devc)
102 if ((2 * len + 2) > sizeof(buf)) {
103 sr_err("Attempted to write %zu bytes, but buffer is too small.",
108 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
109 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
111 for (i = 0; i < len; i++) {
112 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
113 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
116 return sigma_write(buf, idx, devc);
119 SR_PRIV int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
121 return sigma_write_register(reg, &value, 1, devc);
124 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
125 struct dev_context *devc)
129 buf[0] = REG_ADDR_LOW | (reg & 0xf);
130 buf[1] = REG_ADDR_HIGH | (reg >> 4);
131 buf[2] = REG_READ_ADDR;
133 sigma_write(buf, sizeof(buf), devc);
135 return sigma_read(data, len, devc);
138 static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
142 if (1 != sigma_read_register(reg, &value, 1, devc)) {
143 sr_err("sigma_get_register: 1 byte expected");
150 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
151 struct dev_context *devc)
154 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
156 REG_READ_ADDR | NEXT_REG,
157 REG_READ_ADDR | NEXT_REG,
158 REG_READ_ADDR | NEXT_REG,
159 REG_READ_ADDR | NEXT_REG,
160 REG_READ_ADDR | NEXT_REG,
161 REG_READ_ADDR | NEXT_REG,
165 sigma_write(buf, sizeof(buf), devc);
167 sigma_read(result, sizeof(result), devc);
169 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
170 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
172 /* Not really sure why this must be done, but according to spec. */
173 if ((--*stoppos & 0x1ff) == 0x1ff)
176 if ((*--triggerpos & 0x1ff) == 0x1ff)
182 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
183 uint8_t *data, struct dev_context *devc)
189 /* Send the startchunk. Index start with 1. */
190 buf[0] = startchunk >> 8;
191 buf[1] = startchunk & 0xff;
192 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
195 buf[idx++] = REG_DRAM_BLOCK;
196 buf[idx++] = REG_DRAM_WAIT_ACK;
198 for (i = 0; i < numchunks; i++) {
199 /* Alternate bit to copy from DRAM to cache. */
200 if (i != (numchunks - 1))
201 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
203 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
205 if (i != (numchunks - 1))
206 buf[idx++] = REG_DRAM_WAIT_ACK;
209 sigma_write(buf, idx, devc);
211 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
214 /* Upload trigger look-up tables to Sigma. */
215 SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
221 /* Transpose the table and send to Sigma. */
222 for (i = 0; i < 16; i++) {
227 if (lut->m2d[0] & bit)
229 if (lut->m2d[1] & bit)
231 if (lut->m2d[2] & bit)
233 if (lut->m2d[3] & bit)
243 if (lut->m0d[0] & bit)
245 if (lut->m0d[1] & bit)
247 if (lut->m0d[2] & bit)
249 if (lut->m0d[3] & bit)
252 if (lut->m1d[0] & bit)
254 if (lut->m1d[1] & bit)
256 if (lut->m1d[2] & bit)
258 if (lut->m1d[3] & bit)
261 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
263 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
266 /* Send the parameters */
267 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
268 sizeof(lut->params), devc);
273 SR_PRIV void sigma_clear_helper(void *priv)
275 struct dev_context *devc;
279 ftdi_deinit(&devc->ftdic);
283 * Configure the FPGA for bitbang mode.
284 * This sequence is documented in section 2. of the ASIX Sigma programming
285 * manual. This sequence is necessary to configure the FPGA in the Sigma
286 * into Bitbang mode, in which it can be programmed with the firmware.
288 static int sigma_fpga_init_bitbang(struct dev_context *devc)
290 uint8_t suicide[] = {
291 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
293 uint8_t init_array[] = {
294 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
297 int i, ret, timeout = (10 * 1000);
300 /* Section 2. part 1), do the FPGA suicide. */
301 sigma_write(suicide, sizeof(suicide), devc);
302 sigma_write(suicide, sizeof(suicide), devc);
303 sigma_write(suicide, sizeof(suicide), devc);
304 sigma_write(suicide, sizeof(suicide), devc);
306 /* Section 2. part 2), do pulse on D1. */
307 sigma_write(init_array, sizeof(init_array), devc);
308 ftdi_usb_purge_buffers(&devc->ftdic);
310 /* Wait until the FPGA asserts D6/INIT_B. */
311 for (i = 0; i < timeout; i++) {
312 ret = sigma_read(&data, 1, devc);
315 /* Test if pin D6 got asserted. */
318 /* The D6 was not asserted yet, wait a bit. */
322 return SR_ERR_TIMEOUT;
326 * Configure the FPGA for logic-analyzer mode.
328 static int sigma_fpga_init_la(struct dev_context *devc)
330 /* Initialize the logic analyzer mode. */
331 uint8_t logic_mode_start[] = {
332 REG_ADDR_LOW | (READ_ID & 0xf),
333 REG_ADDR_HIGH | (READ_ID >> 8),
334 REG_READ_ADDR, /* Read ID register. */
336 REG_ADDR_LOW | (WRITE_TEST & 0xf),
338 REG_DATA_HIGH_WRITE | 0x5,
339 REG_READ_ADDR, /* Read scratch register. */
342 REG_DATA_HIGH_WRITE | 0xa,
343 REG_READ_ADDR, /* Read scratch register. */
345 REG_ADDR_LOW | (WRITE_MODE & 0xf),
347 REG_DATA_HIGH_WRITE | 0x8,
353 /* Initialize the logic analyzer mode. */
354 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
356 /* Expect a 3 byte reply since we issued three READ requests. */
357 ret = sigma_read(result, 3, devc);
361 if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa)
366 sr_err("Configuration failed. Invalid reply received.");
371 * Read the firmware from a file and transform it into a series of bitbang
372 * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d
373 * by the caller of this function.
375 static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name,
376 uint8_t **bb_cmd, gsize *bb_cmd_size)
378 size_t i, file_size, bb_size;
380 uint8_t *bb_stream, *bbs;
385 /* Retrieve the on-disk firmware file content. */
386 firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE,
387 name, &file_size, 256 * 1024);
391 /* Unscramble the file content (XOR with "random" sequence). */
393 for (i = 0; i < file_size; i++) {
394 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
395 firmware[i] ^= imm & 0xff;
399 * Generate a sequence of bitbang samples. With two samples per
400 * FPGA configuration bit, providing the level for the DIN signal
401 * as well as two edges for CCLK. See Xilinx UG332 for details
402 * ("slave serial" mode).
404 * Note that CCLK is inverted in hardware. That's why the
405 * respective bit is first set and then cleared in the bitbang
406 * sample sets. So that the DIN level will be stable when the
407 * data gets sampled at the rising CCLK edge, and the signals'
408 * setup time constraint will be met.
410 * The caller will put the FPGA into download mode, will send
411 * the bitbang samples, and release the allocated memory.
413 bb_size = file_size * 8 * 2;
414 bb_stream = (uint8_t *)g_try_malloc(bb_size);
416 sr_err("%s: Failed to allocate bitbang stream", __func__);
421 for (i = 0; i < file_size; i++) {
422 for (bit = 7; bit >= 0; bit--) {
423 v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00;
429 /* The transformation completed successfully, return the result. */
431 *bb_cmd_size = bb_size;
438 static int upload_firmware(struct sr_context *ctx,
439 int firmware_idx, struct dev_context *devc)
445 const char *firmware = sigma_firmware_files[firmware_idx];
446 struct ftdi_context *ftdic = &devc->ftdic;
448 /* Make sure it's an ASIX SIGMA. */
449 ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT,
450 USB_DESCRIPTION, NULL);
452 sr_err("ftdi_usb_open failed: %s",
453 ftdi_get_error_string(ftdic));
457 ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG);
459 sr_err("ftdi_set_bitmode failed: %s",
460 ftdi_get_error_string(ftdic));
464 /* Four times the speed of sigmalogan - Works well. */
465 ret = ftdi_set_baudrate(ftdic, 750 * 1000);
467 sr_err("ftdi_set_baudrate failed: %s",
468 ftdi_get_error_string(ftdic));
472 /* Initialize the FPGA for firmware upload. */
473 ret = sigma_fpga_init_bitbang(devc);
477 /* Prepare firmware. */
478 ret = sigma_fw_2_bitbang(ctx, firmware, &buf, &buf_size);
480 sr_err("An error occurred while reading the firmware: %s",
485 /* Upload firmware. */
486 sr_info("Uploading firmware file '%s'.", firmware);
487 sigma_write(buf, buf_size, devc);
491 ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET);
493 sr_err("ftdi_set_bitmode failed: %s",
494 ftdi_get_error_string(ftdic));
498 ftdi_usb_purge_buffers(ftdic);
500 /* Discard garbage. */
501 while (sigma_read(&pins, 1, devc) == 1)
504 /* Initialize the FPGA for logic-analyzer mode. */
505 ret = sigma_fpga_init_la(devc);
509 devc->cur_firmware = firmware_idx;
511 sr_info("Firmware uploaded.");
517 * Sigma doesn't support limiting the number of samples, so we have to
518 * translate the number and the samplerate to an elapsed time.
520 * In addition we need to ensure that the last data cluster has passed
521 * the hardware pipeline, and became available to the PC side. With RLE
522 * compression up to 327ms could pass before another cluster accumulates
523 * at 200kHz samplerate when input pins don't change.
525 SR_PRIV uint64_t sigma_limit_samples_to_msec(const struct dev_context *devc,
526 uint64_t limit_samples)
529 uint64_t worst_cluster_time_ms;
531 limit_msec = limit_samples * 1000 / devc->cur_samplerate;
532 worst_cluster_time_ms = 65536 * 1000 / devc->cur_samplerate;
534 * One cluster time is not enough to flush pipeline when sampling
535 * grounded pins with 1 sample limit at 200kHz. Hence the 2* fix.
537 return limit_msec + 2 * worst_cluster_time_ms;
540 SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
542 struct dev_context *devc;
543 struct drv_context *drvc;
548 drvc = sdi->driver->context;
551 /* Reject rates that are not in the list of supported rates. */
552 for (i = 0; i < samplerates_count; i++) {
553 if (samplerates[i] == samplerate)
556 if (i >= samplerates_count || samplerates[i] == 0)
557 return SR_ERR_SAMPLERATE;
560 * Depending on the samplerates of 200/100/50- MHz, specific
561 * firmware is required and higher rates might limit the set
562 * of available channels.
564 if (samplerate <= SR_MHZ(50)) {
565 ret = upload_firmware(drvc->sr_ctx, 0, devc);
566 devc->num_channels = 16;
567 } else if (samplerate == SR_MHZ(100)) {
568 ret = upload_firmware(drvc->sr_ctx, 1, devc);
569 devc->num_channels = 8;
570 } else if (samplerate == SR_MHZ(200)) {
571 ret = upload_firmware(drvc->sr_ctx, 2, devc);
572 devc->num_channels = 4;
576 * Derive the sample period from the sample rate as well as the
577 * number of samples that the device will communicate within
578 * an "event" (memory organization internal to the device).
581 devc->cur_samplerate = samplerate;
582 devc->period_ps = 1000000000000ULL / samplerate;
583 devc->samples_per_event = 16 / devc->num_channels;
584 devc->state.state = SIGMA_IDLE;
588 * Support for "limit_samples" is implemented by stopping
589 * acquisition after a corresponding period of time.
590 * Re-calculate that period of time, in case the limit is
591 * set first and the samplerate gets (re-)configured later.
593 if (ret == SR_OK && devc->limit_samples) {
595 msecs = sigma_limit_samples_to_msec(devc, devc->limit_samples);
596 devc->limit_msec = msecs;
603 * In 100 and 200 MHz mode, only a single pin rising/falling can be
604 * set as trigger. In other modes, two rising/falling triggers can be set,
605 * in addition to value/mask trigger for any number of channels.
607 * The Sigma supports complex triggers using boolean expressions, but this
608 * has not been implemented yet.
610 SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi)
612 struct dev_context *devc;
613 struct sr_trigger *trigger;
614 struct sr_trigger_stage *stage;
615 struct sr_trigger_match *match;
617 int channelbit, trigger_set;
620 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
621 if (!(trigger = sr_session_trigger_get(sdi->session)))
625 for (l = trigger->stages; l; l = l->next) {
627 for (m = stage->matches; m; m = m->next) {
629 if (!match->channel->enabled)
630 /* Ignore disabled channels with a trigger. */
632 channelbit = 1 << (match->channel->index);
633 if (devc->cur_samplerate >= SR_MHZ(100)) {
634 /* Fast trigger support. */
636 sr_err("Only a single pin trigger is "
637 "supported in 100 and 200MHz mode.");
640 if (match->match == SR_TRIGGER_FALLING)
641 devc->trigger.fallingmask |= channelbit;
642 else if (match->match == SR_TRIGGER_RISING)
643 devc->trigger.risingmask |= channelbit;
645 sr_err("Only rising/falling trigger is "
646 "supported in 100 and 200MHz mode.");
652 /* Simple trigger support (event). */
653 if (match->match == SR_TRIGGER_ONE) {
654 devc->trigger.simplevalue |= channelbit;
655 devc->trigger.simplemask |= channelbit;
657 else if (match->match == SR_TRIGGER_ZERO) {
658 devc->trigger.simplevalue &= ~channelbit;
659 devc->trigger.simplemask |= channelbit;
661 else if (match->match == SR_TRIGGER_FALLING) {
662 devc->trigger.fallingmask |= channelbit;
665 else if (match->match == SR_TRIGGER_RISING) {
666 devc->trigger.risingmask |= channelbit;
671 * Actually, Sigma supports 2 rising/falling triggers,
672 * but they are ORed and the current trigger syntax
673 * does not permit ORed triggers.
675 if (trigger_set > 1) {
676 sr_err("Only 1 rising/falling trigger "
688 /* Software trigger to determine exact trigger position. */
689 static int get_trigger_offset(uint8_t *samples, uint16_t last_sample,
690 struct sigma_trigger *t)
695 for (i = 0; i < 8; i++) {
697 last_sample = sample;
698 sample = samples[2 * i] | (samples[2 * i + 1] << 8);
700 /* Simple triggers. */
701 if ((sample & t->simplemask) != t->simplevalue)
705 if (((last_sample & t->risingmask) != 0) ||
706 ((sample & t->risingmask) != t->risingmask))
710 if ((last_sample & t->fallingmask) != t->fallingmask ||
711 (sample & t->fallingmask) != 0)
717 /* If we did not match, return original trigger pos. */
722 * Return the timestamp of "DRAM cluster".
724 static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster)
726 return (cluster->timestamp_hi << 8) | cluster->timestamp_lo;
730 * Return one 16bit data entity of a DRAM cluster at the specified index.
732 static uint16_t sigma_dram_cluster_data(struct sigma_dram_cluster *cl, int idx)
737 sample |= cl->samples[idx].sample_lo << 0;
738 sample |= cl->samples[idx].sample_hi << 8;
739 sample = (sample >> 8) | (sample << 8);
744 * Deinterlace sample data that was retrieved at 100MHz samplerate.
745 * One 16bit item contains two samples of 8bits each. The bits of
746 * multiple samples are interleaved.
748 static uint16_t sigma_deinterlace_100mhz_data(uint16_t indata, int idx)
754 outdata |= (indata >> (0 * 2 - 0)) & (1 << 0);
755 outdata |= (indata >> (1 * 2 - 1)) & (1 << 1);
756 outdata |= (indata >> (2 * 2 - 2)) & (1 << 2);
757 outdata |= (indata >> (3 * 2 - 3)) & (1 << 3);
758 outdata |= (indata >> (4 * 2 - 4)) & (1 << 4);
759 outdata |= (indata >> (5 * 2 - 5)) & (1 << 5);
760 outdata |= (indata >> (6 * 2 - 6)) & (1 << 6);
761 outdata |= (indata >> (7 * 2 - 7)) & (1 << 7);
766 * Deinterlace sample data that was retrieved at 200MHz samplerate.
767 * One 16bit item contains four samples of 4bits each. The bits of
768 * multiple samples are interleaved.
770 static uint16_t sigma_deinterlace_200mhz_data(uint16_t indata, int idx)
776 outdata |= (indata >> (0 * 4 - 0)) & (1 << 0);
777 outdata |= (indata >> (1 * 4 - 1)) & (1 << 1);
778 outdata |= (indata >> (2 * 4 - 2)) & (1 << 2);
779 outdata |= (indata >> (3 * 4 - 3)) & (1 << 3);
783 static void store_sr_sample(uint8_t *samples, int idx, uint16_t data)
785 samples[2 * idx + 0] = (data >> 0) & 0xff;
786 samples[2 * idx + 1] = (data >> 8) & 0xff;
790 * This size translates to: event count (1K events per cluster), times
791 * the sample width (unitsize, 16bits per event), times the maximum
792 * number of samples per event.
794 #define SAMPLES_BUFFER_SIZE (1024 * 2 * 4)
796 static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster,
797 unsigned int events_in_cluster,
798 unsigned int triggered,
799 struct sr_dev_inst *sdi)
801 struct dev_context *devc = sdi->priv;
802 struct sigma_state *ss = &devc->state;
803 struct sr_datafeed_packet packet;
804 struct sr_datafeed_logic logic;
805 uint16_t tsdiff, ts, sample, item16;
806 uint8_t samples[SAMPLES_BUFFER_SIZE];
808 size_t send_count, trig_count;
812 ts = sigma_dram_cluster_ts(dram_cluster);
813 tsdiff = ts - ss->lastts;
814 ss->lastts = ts + EVENTS_PER_CLUSTER;
816 packet.type = SR_DF_LOGIC;
817 packet.payload = &logic;
819 logic.data = samples;
822 * First of all, send Sigrok a copy of the last sample from
823 * previous cluster as many times as needed to make up for
824 * the differential characteristics of data we get from the
825 * Sigma. Sigrok needs one sample of data per period.
827 * One DRAM cluster contains a timestamp and seven samples,
828 * the units of timestamp are "devc->period_ps" , the first
829 * sample in the cluster happens at the time of the timestamp
830 * and the remaining samples happen at timestamp +1...+6 .
832 for (ts = 0; ts < tsdiff; ts++) {
834 store_sr_sample(samples, i, ss->lastsample);
837 * If we have 1024 samples ready or we're at the
838 * end of submitting the padding samples, submit
839 * the packet to Sigrok. Since constant data is
840 * sent, duplication of data for rates above 50MHz
843 if ((i == 1023) || (ts == tsdiff - 1)) {
844 logic.length = (i + 1) * logic.unitsize;
845 for (j = 0; j < devc->samples_per_event; j++)
846 sr_session_send(sdi, &packet);
851 * Parse the samples in current cluster and prepare them
852 * to be submitted to Sigrok. Cope with memory layouts that
853 * vary with the samplerate.
855 send_ptr = &samples[0];
858 for (i = 0; i < events_in_cluster; i++) {
859 item16 = sigma_dram_cluster_data(dram_cluster, i);
860 if (devc->cur_samplerate == SR_MHZ(200)) {
861 sample = sigma_deinterlace_200mhz_data(item16, 0);
862 store_sr_sample(samples, send_count++, sample);
863 sample = sigma_deinterlace_200mhz_data(item16, 1);
864 store_sr_sample(samples, send_count++, sample);
865 sample = sigma_deinterlace_200mhz_data(item16, 2);
866 store_sr_sample(samples, send_count++, sample);
867 sample = sigma_deinterlace_200mhz_data(item16, 3);
868 store_sr_sample(samples, send_count++, sample);
869 } else if (devc->cur_samplerate == SR_MHZ(100)) {
870 sample = sigma_deinterlace_100mhz_data(item16, 0);
871 store_sr_sample(samples, send_count++, sample);
872 sample = sigma_deinterlace_100mhz_data(item16, 1);
873 store_sr_sample(samples, send_count++, sample);
876 store_sr_sample(samples, send_count++, sample);
881 * If a trigger position applies, then provide the datafeed with
882 * the first part of data up to that position, then send the
885 int trigger_offset = 0;
888 * Trigger is not always accurate to sample because of
889 * pipeline delay. However, it always triggers before
890 * the actual event. We therefore look at the next
891 * samples to pinpoint the exact position of the trigger.
893 trigger_offset = get_trigger_offset(samples,
894 ss->lastsample, &devc->trigger);
896 if (trigger_offset > 0) {
897 trig_count = trigger_offset * devc->samples_per_event;
898 packet.type = SR_DF_LOGIC;
899 logic.length = trig_count * logic.unitsize;
900 sr_session_send(sdi, &packet);
901 send_ptr += trig_count * logic.unitsize;
902 send_count -= trig_count;
905 /* Only send trigger if explicitly enabled. */
906 if (devc->use_triggers) {
907 packet.type = SR_DF_TRIGGER;
908 sr_session_send(sdi, &packet);
913 * Send the data after the trigger, or all of the received data
914 * if no trigger position applies.
917 packet.type = SR_DF_LOGIC;
918 logic.length = send_count * logic.unitsize;
919 logic.data = send_ptr;
920 sr_session_send(sdi, &packet);
923 ss->lastsample = sample;
927 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
928 * Each event is 20ns apart, and can contain multiple samples.
930 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
931 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
932 * For 50 MHz and below, events contain one sample for each channel,
933 * spread 20 ns apart.
935 static int decode_chunk_ts(struct sigma_dram_line *dram_line,
936 uint16_t events_in_line,
937 uint32_t trigger_event,
938 struct sr_dev_inst *sdi)
940 struct sigma_dram_cluster *dram_cluster;
941 struct dev_context *devc = sdi->priv;
942 unsigned int clusters_in_line =
943 (events_in_line + (EVENTS_PER_CLUSTER - 1)) / EVENTS_PER_CLUSTER;
944 unsigned int events_in_cluster;
946 uint32_t trigger_cluster = ~0, triggered = 0;
948 /* Check if trigger is in this chunk. */
949 if (trigger_event < (64 * 7)) {
950 if (devc->cur_samplerate <= SR_MHZ(50)) {
951 trigger_event -= MIN(EVENTS_PER_CLUSTER - 1,
955 /* Find in which cluster the trigger occurred. */
956 trigger_cluster = trigger_event / EVENTS_PER_CLUSTER;
959 /* For each full DRAM cluster. */
960 for (i = 0; i < clusters_in_line; i++) {
961 dram_cluster = &dram_line->cluster[i];
963 /* The last cluster might not be full. */
964 if ((i == clusters_in_line - 1) &&
965 (events_in_line % EVENTS_PER_CLUSTER)) {
966 events_in_cluster = events_in_line % EVENTS_PER_CLUSTER;
968 events_in_cluster = EVENTS_PER_CLUSTER;
971 triggered = (i == trigger_cluster);
972 sigma_decode_dram_cluster(dram_cluster, events_in_cluster,
979 static int download_capture(struct sr_dev_inst *sdi)
981 struct dev_context *devc = sdi->priv;
982 const uint32_t chunks_per_read = 32;
983 struct sigma_dram_line *dram_line;
985 uint32_t stoppos, triggerpos;
989 uint32_t dl_lines_total, dl_lines_curr, dl_lines_done;
990 uint32_t dl_events_in_line = 64 * 7;
991 uint32_t trg_line = ~0, trg_event = ~0;
993 dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line));
997 sr_info("Downloading sample data.");
999 /* Stop acquisition. */
1000 sigma_set_register(WRITE_MODE, 0x11, devc);
1002 /* Set SDRAM Read Enable. */
1003 sigma_set_register(WRITE_MODE, 0x02, devc);
1005 /* Get the current position. */
1006 sigma_read_pos(&stoppos, &triggerpos, devc);
1008 /* Check if trigger has fired. */
1009 modestatus = sigma_get_register(READ_MODE, devc);
1010 if (modestatus & 0x20) {
1011 trg_line = triggerpos >> 9;
1012 trg_event = triggerpos & 0x1ff;
1016 * Determine how many 1024b "DRAM lines" do we need to read from the
1017 * Sigma so we have a complete set of samples. Note that the last
1018 * line can be only partial, containing less than 64 clusters.
1020 dl_lines_total = (stoppos >> 9) + 1;
1024 while (dl_lines_total > dl_lines_done) {
1025 /* We can download only up-to 32 DRAM lines in one go! */
1026 dl_lines_curr = MIN(chunks_per_read, dl_lines_total);
1028 bufsz = sigma_read_dram(dl_lines_done, dl_lines_curr,
1029 (uint8_t *)dram_line, devc);
1030 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1033 /* This is the first DRAM line, so find the initial timestamp. */
1034 if (dl_lines_done == 0) {
1035 devc->state.lastts =
1036 sigma_dram_cluster_ts(&dram_line[0].cluster[0]);
1037 devc->state.lastsample = 0;
1040 for (i = 0; i < dl_lines_curr; i++) {
1041 uint32_t trigger_event = ~0;
1042 /* The last "DRAM line" can be only partially full. */
1043 if (dl_lines_done + i == dl_lines_total - 1)
1044 dl_events_in_line = stoppos & 0x1ff;
1046 /* Test if the trigger happened on this line. */
1047 if (dl_lines_done + i == trg_line)
1048 trigger_event = trg_event;
1050 decode_chunk_ts(dram_line + i, dl_events_in_line,
1051 trigger_event, sdi);
1054 dl_lines_done += dl_lines_curr;
1057 std_session_send_df_end(sdi);
1059 sdi->driver->dev_acquisition_stop(sdi);
1067 * Handle the Sigma when in CAPTURE mode. This function checks:
1068 * - Sampling time ended
1069 * - DRAM capacity overflow
1070 * This function triggers download of the samples from Sigma
1071 * in case either of the above conditions is true.
1073 static int sigma_capture_mode(struct sr_dev_inst *sdi)
1075 struct dev_context *devc = sdi->priv;
1077 uint64_t running_msec;
1080 uint32_t stoppos, triggerpos;
1082 /* Check if the selected sampling duration passed. */
1083 gettimeofday(&tv, 0);
1084 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1085 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1086 if (running_msec >= devc->limit_msec)
1087 return download_capture(sdi);
1089 /* Get the position in DRAM to which the FPGA is writing now. */
1090 sigma_read_pos(&stoppos, &triggerpos, devc);
1091 /* Test if DRAM is full and if so, download the data. */
1092 if ((stoppos >> 9) == 32767)
1093 return download_capture(sdi);
1098 SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data)
1100 struct sr_dev_inst *sdi;
1101 struct dev_context *devc;
1109 if (devc->state.state == SIGMA_IDLE)
1112 if (devc->state.state == SIGMA_CAPTURE)
1113 return sigma_capture_mode(sdi);
1118 /* Build a LUT entry used by the trigger functions. */
1119 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1123 /* For each quad channel. */
1124 for (i = 0; i < 4; i++) {
1127 /* For each bit in LUT. */
1128 for (j = 0; j < 16; j++)
1130 /* For each channel in quad. */
1131 for (k = 0; k < 4; k++) {
1132 bit = 1 << (i * 4 + k);
1134 /* Set bit in entry */
1135 if ((mask & bit) && ((!(value & bit)) !=
1137 entry[i] &= ~(1 << j);
1142 /* Add a logical function to LUT mask. */
1143 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1144 int index, int neg, uint16_t *mask)
1147 int x[2][2], tmp, a, b, aset, bset, rset;
1149 memset(x, 0, 4 * sizeof(int));
1151 /* Trigger detect condition. */
1181 case OP_NOTRISEFALL:
1187 /* Transpose if neg is set. */
1189 for (i = 0; i < 2; i++) {
1190 for (j = 0; j < 2; j++) {
1192 x[i][j] = x[1 - i][1 - j];
1193 x[1 - i][1 - j] = tmp;
1198 /* Update mask with function. */
1199 for (i = 0; i < 16; i++) {
1200 a = (i >> (2 * index + 0)) & 1;
1201 b = (i >> (2 * index + 1)) & 1;
1203 aset = (*mask >> i) & 1;
1207 if (func == FUNC_AND || func == FUNC_NAND)
1209 else if (func == FUNC_OR || func == FUNC_NOR)
1211 else if (func == FUNC_XOR || func == FUNC_NXOR)
1214 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1225 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1226 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1227 * set at any time, but a full mask and value can be set (0/1).
1229 SR_PRIV int sigma_build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1232 uint16_t masks[2] = { 0, 0 };
1234 memset(lut, 0, sizeof(struct triggerlut));
1236 /* Constant for simple triggers. */
1239 /* Value/mask trigger support. */
1240 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1243 /* Rise/fall trigger support. */
1244 for (i = 0, j = 0; i < 16; i++) {
1245 if (devc->trigger.risingmask & (1 << i) ||
1246 devc->trigger.fallingmask & (1 << i))
1247 masks[j++] = 1 << i;
1250 build_lut_entry(masks[0], masks[0], lut->m0d);
1251 build_lut_entry(masks[1], masks[1], lut->m1d);
1253 /* Add glue logic */
1254 if (masks[0] || masks[1]) {
1255 /* Transition trigger. */
1256 if (masks[0] & devc->trigger.risingmask)
1257 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1258 if (masks[0] & devc->trigger.fallingmask)
1259 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1260 if (masks[1] & devc->trigger.risingmask)
1261 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1262 if (masks[1] & devc->trigger.fallingmask)
1263 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1265 /* Only value/mask trigger. */
1269 /* Triggertype: event. */
1270 lut->params.selres = 3;