2 * This file is part of the libsigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
30 * The ASIX Sigma supports arbitrary integer frequency divider in
31 * the 50MHz mode. The divider is in range 1...256 , allowing for
32 * very precise sampling rate selection. This driver supports only
33 * a subset of the sampling rates.
35 SR_PRIV const uint64_t samplerates[] = {
36 SR_KHZ(200), /* div=250 */
37 SR_KHZ(250), /* div=200 */
38 SR_KHZ(500), /* div=100 */
39 SR_MHZ(1), /* div=50 */
40 SR_MHZ(5), /* div=10 */
41 SR_MHZ(10), /* div=5 */
42 SR_MHZ(25), /* div=2 */
43 SR_MHZ(50), /* div=1 */
44 SR_MHZ(100), /* Special FW needed */
45 SR_MHZ(200), /* Special FW needed */
48 SR_PRIV const size_t samplerates_count = ARRAY_SIZE(samplerates);
50 static const char firmware_files[][24] = {
51 /* 50 MHz, supports 8 bit fractions */
57 /* Synchronous clock from pin */
58 "asix-sigma-50sync.fw",
59 /* Frequency counter */
60 "asix-sigma-phasor.fw",
63 static int sigma_read(void *buf, size_t size, struct dev_context *devc)
67 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
69 sr_err("ftdi_read_data failed: %s",
70 ftdi_get_error_string(&devc->ftdic));
76 static int sigma_write(void *buf, size_t size, struct dev_context *devc)
80 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
82 sr_err("ftdi_write_data failed: %s",
83 ftdi_get_error_string(&devc->ftdic));
84 } else if ((size_t) ret != size) {
85 sr_err("ftdi_write_data did not complete write.");
92 * NOTE: We chose the buffer size to be large enough to hold any write to the
93 * device. We still print a message just in case.
95 SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
96 struct dev_context *devc)
102 if ((2 * len + 2) > sizeof(buf)) {
103 sr_err("Attempted to write %zu bytes, but buffer is too small.",
108 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
109 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
111 for (i = 0; i < len; i++) {
112 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
113 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
116 return sigma_write(buf, idx, devc);
119 SR_PRIV int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
121 return sigma_write_register(reg, &value, 1, devc);
124 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
125 struct dev_context *devc)
129 buf[0] = REG_ADDR_LOW | (reg & 0xf);
130 buf[1] = REG_ADDR_HIGH | (reg >> 4);
131 buf[2] = REG_READ_ADDR;
133 sigma_write(buf, sizeof(buf), devc);
135 return sigma_read(data, len, devc);
138 static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
142 if (1 != sigma_read_register(reg, &value, 1, devc)) {
143 sr_err("sigma_get_register: 1 byte expected");
150 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
151 struct dev_context *devc)
154 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
156 REG_READ_ADDR | NEXT_REG,
157 REG_READ_ADDR | NEXT_REG,
158 REG_READ_ADDR | NEXT_REG,
159 REG_READ_ADDR | NEXT_REG,
160 REG_READ_ADDR | NEXT_REG,
161 REG_READ_ADDR | NEXT_REG,
165 sigma_write(buf, sizeof(buf), devc);
167 sigma_read(result, sizeof(result), devc);
169 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
170 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
172 /* Not really sure why this must be done, but according to spec. */
173 if ((--*stoppos & 0x1ff) == 0x1ff)
176 if ((*--triggerpos & 0x1ff) == 0x1ff)
182 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
183 uint8_t *data, struct dev_context *devc)
189 /* Send the startchunk. Index start with 1. */
191 buf[idx++] = startchunk >> 8;
192 buf[idx++] = startchunk & 0xff;
193 sigma_write_register(WRITE_MEMROW, buf, idx, devc);
197 buf[idx++] = REG_DRAM_BLOCK;
198 buf[idx++] = REG_DRAM_WAIT_ACK;
200 for (i = 0; i < numchunks; i++) {
201 /* Alternate bit to copy from DRAM to cache. */
202 if (i != (numchunks - 1))
203 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
205 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
207 if (i != (numchunks - 1))
208 buf[idx++] = REG_DRAM_WAIT_ACK;
211 sigma_write(buf, idx, devc);
213 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
216 /* Upload trigger look-up tables to Sigma. */
217 SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
223 /* Transpose the table and send to Sigma. */
224 for (i = 0; i < 16; i++) {
229 if (lut->m2d[0] & bit)
231 if (lut->m2d[1] & bit)
233 if (lut->m2d[2] & bit)
235 if (lut->m2d[3] & bit)
245 if (lut->m0d[0] & bit)
247 if (lut->m0d[1] & bit)
249 if (lut->m0d[2] & bit)
251 if (lut->m0d[3] & bit)
254 if (lut->m1d[0] & bit)
256 if (lut->m1d[1] & bit)
258 if (lut->m1d[2] & bit)
260 if (lut->m1d[3] & bit)
263 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
265 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
268 /* Send the parameters */
269 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
270 sizeof(lut->params), devc);
276 * Configure the FPGA for bitbang mode.
277 * This sequence is documented in section 2. of the ASIX Sigma programming
278 * manual. This sequence is necessary to configure the FPGA in the Sigma
279 * into Bitbang mode, in which it can be programmed with the firmware.
281 static int sigma_fpga_init_bitbang(struct dev_context *devc)
283 uint8_t suicide[] = {
284 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
286 uint8_t init_array[] = {
287 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
290 int i, ret, timeout = (10 * 1000);
293 /* Section 2. part 1), do the FPGA suicide. */
294 sigma_write(suicide, sizeof(suicide), devc);
295 sigma_write(suicide, sizeof(suicide), devc);
296 sigma_write(suicide, sizeof(suicide), devc);
297 sigma_write(suicide, sizeof(suicide), devc);
299 /* Section 2. part 2), do pulse on D1. */
300 sigma_write(init_array, sizeof(init_array), devc);
301 ftdi_usb_purge_buffers(&devc->ftdic);
303 /* Wait until the FPGA asserts D6/INIT_B. */
304 for (i = 0; i < timeout; i++) {
305 ret = sigma_read(&data, 1, devc);
308 /* Test if pin D6 got asserted. */
311 /* The D6 was not asserted yet, wait a bit. */
315 return SR_ERR_TIMEOUT;
319 * Configure the FPGA for logic-analyzer mode.
321 static int sigma_fpga_init_la(struct dev_context *devc)
323 /* Initialize the logic analyzer mode. */
324 uint8_t mode_regval = WMR_SDRAMINIT;
325 uint8_t logic_mode_start[] = {
326 REG_ADDR_LOW | (READ_ID & 0xf),
327 REG_ADDR_HIGH | (READ_ID >> 4),
328 REG_READ_ADDR, /* Read ID register. */
330 REG_ADDR_LOW | (WRITE_TEST & 0xf),
332 REG_DATA_HIGH_WRITE | 0x5,
333 REG_READ_ADDR, /* Read scratch register. */
336 REG_DATA_HIGH_WRITE | 0xa,
337 REG_READ_ADDR, /* Read scratch register. */
339 REG_ADDR_LOW | (WRITE_MODE & 0xf),
340 REG_DATA_LOW | (mode_regval & 0xf),
341 REG_DATA_HIGH_WRITE | (mode_regval >> 4),
347 /* Initialize the logic analyzer mode. */
348 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
350 /* Expect a 3 byte reply since we issued three READ requests. */
351 ret = sigma_read(result, 3, devc);
355 if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa)
360 sr_err("Configuration failed. Invalid reply received.");
365 * Read the firmware from a file and transform it into a series of bitbang
366 * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d
367 * by the caller of this function.
369 static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name,
370 uint8_t **bb_cmd, gsize *bb_cmd_size)
372 size_t i, file_size, bb_size;
374 uint8_t *bb_stream, *bbs;
379 /* Retrieve the on-disk firmware file content. */
380 firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE,
381 name, &file_size, 256 * 1024);
385 /* Unscramble the file content (XOR with "random" sequence). */
387 for (i = 0; i < file_size; i++) {
388 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
389 firmware[i] ^= imm & 0xff;
393 * Generate a sequence of bitbang samples. With two samples per
394 * FPGA configuration bit, providing the level for the DIN signal
395 * as well as two edges for CCLK. See Xilinx UG332 for details
396 * ("slave serial" mode).
398 * Note that CCLK is inverted in hardware. That's why the
399 * respective bit is first set and then cleared in the bitbang
400 * sample sets. So that the DIN level will be stable when the
401 * data gets sampled at the rising CCLK edge, and the signals'
402 * setup time constraint will be met.
404 * The caller will put the FPGA into download mode, will send
405 * the bitbang samples, and release the allocated memory.
407 bb_size = file_size * 8 * 2;
408 bb_stream = (uint8_t *)g_try_malloc(bb_size);
410 sr_err("%s: Failed to allocate bitbang stream", __func__);
415 for (i = 0; i < file_size; i++) {
416 for (bit = 7; bit >= 0; bit--) {
417 v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00;
423 /* The transformation completed successfully, return the result. */
425 *bb_cmd_size = bb_size;
432 static int upload_firmware(struct sr_context *ctx,
433 int firmware_idx, struct dev_context *devc)
439 const char *firmware;
441 /* Avoid downloading the same firmware multiple times. */
442 firmware = firmware_files[firmware_idx];
443 if (devc->cur_firmware == firmware_idx) {
444 sr_info("Not uploading firmware file '%s' again.", firmware);
448 ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG);
450 sr_err("ftdi_set_bitmode failed: %s",
451 ftdi_get_error_string(&devc->ftdic));
455 /* Four times the speed of sigmalogan - Works well. */
456 ret = ftdi_set_baudrate(&devc->ftdic, 750 * 1000);
458 sr_err("ftdi_set_baudrate failed: %s",
459 ftdi_get_error_string(&devc->ftdic));
463 /* Initialize the FPGA for firmware upload. */
464 ret = sigma_fpga_init_bitbang(devc);
468 /* Prepare firmware. */
469 ret = sigma_fw_2_bitbang(ctx, firmware, &buf, &buf_size);
471 sr_err("An error occurred while reading the firmware: %s",
476 /* Upload firmware. */
477 sr_info("Uploading firmware file '%s'.", firmware);
478 sigma_write(buf, buf_size, devc);
482 ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET);
484 sr_err("ftdi_set_bitmode failed: %s",
485 ftdi_get_error_string(&devc->ftdic));
489 ftdi_usb_purge_buffers(&devc->ftdic);
491 /* Discard garbage. */
492 while (sigma_read(&pins, 1, devc) == 1)
495 /* Initialize the FPGA for logic-analyzer mode. */
496 ret = sigma_fpga_init_la(devc);
500 devc->cur_firmware = firmware_idx;
502 sr_info("Firmware uploaded.");
508 * Sigma doesn't support limiting the number of samples, so we have to
509 * translate the number and the samplerate to an elapsed time.
511 * In addition we need to ensure that the last data cluster has passed
512 * the hardware pipeline, and became available to the PC side. With RLE
513 * compression up to 327ms could pass before another cluster accumulates
514 * at 200kHz samplerate when input pins don't change.
516 SR_PRIV uint64_t sigma_limit_samples_to_msec(const struct dev_context *devc,
517 uint64_t limit_samples)
520 uint64_t worst_cluster_time_ms;
522 limit_msec = limit_samples * 1000 / devc->cur_samplerate;
523 worst_cluster_time_ms = 65536 * 1000 / devc->cur_samplerate;
525 * One cluster time is not enough to flush pipeline when sampling
526 * grounded pins with 1 sample limit at 200kHz. Hence the 2* fix.
528 return limit_msec + 2 * worst_cluster_time_ms;
531 SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
533 struct dev_context *devc;
534 struct drv_context *drvc;
540 drvc = sdi->driver->context;
543 /* Reject rates that are not in the list of supported rates. */
544 for (i = 0; i < samplerates_count; i++) {
545 if (samplerates[i] == samplerate)
548 if (i >= samplerates_count || samplerates[i] == 0)
549 return SR_ERR_SAMPLERATE;
552 * Depending on the samplerates of 200/100/50- MHz, specific
553 * firmware is required and higher rates might limit the set
554 * of available channels.
556 num_channels = devc->num_channels;
557 if (samplerate <= SR_MHZ(50)) {
558 ret = upload_firmware(drvc->sr_ctx, 0, devc);
560 } else if (samplerate == SR_MHZ(100)) {
561 ret = upload_firmware(drvc->sr_ctx, 1, devc);
563 } else if (samplerate == SR_MHZ(200)) {
564 ret = upload_firmware(drvc->sr_ctx, 2, devc);
569 * Derive the sample period from the sample rate as well as the
570 * number of samples that the device will communicate within
571 * an "event" (memory organization internal to the device).
574 devc->num_channels = num_channels;
575 devc->cur_samplerate = samplerate;
576 devc->samples_per_event = 16 / devc->num_channels;
577 devc->state.state = SIGMA_IDLE;
581 * Support for "limit_samples" is implemented by stopping
582 * acquisition after a corresponding period of time.
583 * Re-calculate that period of time, in case the limit is
584 * set first and the samplerate gets (re-)configured later.
586 if (ret == SR_OK && devc->limit_samples) {
588 msecs = sigma_limit_samples_to_msec(devc, devc->limit_samples);
589 devc->limit_msec = msecs;
596 * In 100 and 200 MHz mode, only a single pin rising/falling can be
597 * set as trigger. In other modes, two rising/falling triggers can be set,
598 * in addition to value/mask trigger for any number of channels.
600 * The Sigma supports complex triggers using boolean expressions, but this
601 * has not been implemented yet.
603 SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi)
605 struct dev_context *devc;
606 struct sr_trigger *trigger;
607 struct sr_trigger_stage *stage;
608 struct sr_trigger_match *match;
610 int channelbit, trigger_set;
613 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
614 if (!(trigger = sr_session_trigger_get(sdi->session)))
618 for (l = trigger->stages; l; l = l->next) {
620 for (m = stage->matches; m; m = m->next) {
622 if (!match->channel->enabled)
623 /* Ignore disabled channels with a trigger. */
625 channelbit = 1 << (match->channel->index);
626 if (devc->cur_samplerate >= SR_MHZ(100)) {
627 /* Fast trigger support. */
629 sr_err("Only a single pin trigger is "
630 "supported in 100 and 200MHz mode.");
633 if (match->match == SR_TRIGGER_FALLING)
634 devc->trigger.fallingmask |= channelbit;
635 else if (match->match == SR_TRIGGER_RISING)
636 devc->trigger.risingmask |= channelbit;
638 sr_err("Only rising/falling trigger is "
639 "supported in 100 and 200MHz mode.");
645 /* Simple trigger support (event). */
646 if (match->match == SR_TRIGGER_ONE) {
647 devc->trigger.simplevalue |= channelbit;
648 devc->trigger.simplemask |= channelbit;
650 else if (match->match == SR_TRIGGER_ZERO) {
651 devc->trigger.simplevalue &= ~channelbit;
652 devc->trigger.simplemask |= channelbit;
654 else if (match->match == SR_TRIGGER_FALLING) {
655 devc->trigger.fallingmask |= channelbit;
658 else if (match->match == SR_TRIGGER_RISING) {
659 devc->trigger.risingmask |= channelbit;
664 * Actually, Sigma supports 2 rising/falling triggers,
665 * but they are ORed and the current trigger syntax
666 * does not permit ORed triggers.
668 if (trigger_set > 1) {
669 sr_err("Only 1 rising/falling trigger "
680 /* Software trigger to determine exact trigger position. */
681 static int get_trigger_offset(uint8_t *samples, uint16_t last_sample,
682 struct sigma_trigger *t)
687 for (i = 0; i < 8; i++) {
689 last_sample = sample;
690 sample = samples[2 * i] | (samples[2 * i + 1] << 8);
692 /* Simple triggers. */
693 if ((sample & t->simplemask) != t->simplevalue)
697 if (((last_sample & t->risingmask) != 0) ||
698 ((sample & t->risingmask) != t->risingmask))
702 if ((last_sample & t->fallingmask) != t->fallingmask ||
703 (sample & t->fallingmask) != 0)
709 /* If we did not match, return original trigger pos. */
714 * Return the timestamp of "DRAM cluster".
716 static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster)
718 return (cluster->timestamp_hi << 8) | cluster->timestamp_lo;
722 * Return one 16bit data entity of a DRAM cluster at the specified index.
724 static uint16_t sigma_dram_cluster_data(struct sigma_dram_cluster *cl, int idx)
729 sample |= cl->samples[idx].sample_lo << 0;
730 sample |= cl->samples[idx].sample_hi << 8;
731 sample = (sample >> 8) | (sample << 8);
736 * Deinterlace sample data that was retrieved at 100MHz samplerate.
737 * One 16bit item contains two samples of 8bits each. The bits of
738 * multiple samples are interleaved.
740 static uint16_t sigma_deinterlace_100mhz_data(uint16_t indata, int idx)
746 outdata |= (indata >> (0 * 2 - 0)) & (1 << 0);
747 outdata |= (indata >> (1 * 2 - 1)) & (1 << 1);
748 outdata |= (indata >> (2 * 2 - 2)) & (1 << 2);
749 outdata |= (indata >> (3 * 2 - 3)) & (1 << 3);
750 outdata |= (indata >> (4 * 2 - 4)) & (1 << 4);
751 outdata |= (indata >> (5 * 2 - 5)) & (1 << 5);
752 outdata |= (indata >> (6 * 2 - 6)) & (1 << 6);
753 outdata |= (indata >> (7 * 2 - 7)) & (1 << 7);
758 * Deinterlace sample data that was retrieved at 200MHz samplerate.
759 * One 16bit item contains four samples of 4bits each. The bits of
760 * multiple samples are interleaved.
762 static uint16_t sigma_deinterlace_200mhz_data(uint16_t indata, int idx)
768 outdata |= (indata >> (0 * 4 - 0)) & (1 << 0);
769 outdata |= (indata >> (1 * 4 - 1)) & (1 << 1);
770 outdata |= (indata >> (2 * 4 - 2)) & (1 << 2);
771 outdata |= (indata >> (3 * 4 - 3)) & (1 << 3);
775 static void store_sr_sample(uint8_t *samples, int idx, uint16_t data)
777 samples[2 * idx + 0] = (data >> 0) & 0xff;
778 samples[2 * idx + 1] = (data >> 8) & 0xff;
782 * Local wrapper around sr_session_send() calls. Make sure to not send
783 * more samples to the session's datafeed than what was requested by a
784 * previously configured (optional) sample count.
786 static void sigma_session_send(struct sr_dev_inst *sdi,
787 struct sr_datafeed_packet *packet)
789 struct dev_context *devc;
790 struct sr_datafeed_logic *logic;
794 if (devc->limit_samples) {
795 logic = (void *)packet->payload;
796 send_now = logic->length / logic->unitsize;
797 if (devc->sent_samples + send_now > devc->limit_samples) {
798 send_now = devc->limit_samples - devc->sent_samples;
799 logic->length = send_now * logic->unitsize;
803 devc->sent_samples += send_now;
806 sr_session_send(sdi, packet);
810 * This size translates to: event count (1K events per cluster), times
811 * the sample width (unitsize, 16bits per event), times the maximum
812 * number of samples per event.
814 #define SAMPLES_BUFFER_SIZE (1024 * 2 * 4)
816 static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster,
817 unsigned int events_in_cluster,
818 unsigned int triggered,
819 struct sr_dev_inst *sdi)
821 struct dev_context *devc = sdi->priv;
822 struct sigma_state *ss = &devc->state;
823 struct sr_datafeed_packet packet;
824 struct sr_datafeed_logic logic;
825 uint16_t tsdiff, ts, sample, item16;
826 uint8_t samples[SAMPLES_BUFFER_SIZE];
828 size_t send_count, trig_count;
832 ts = sigma_dram_cluster_ts(dram_cluster);
833 tsdiff = ts - ss->lastts;
834 ss->lastts = ts + EVENTS_PER_CLUSTER;
836 packet.type = SR_DF_LOGIC;
837 packet.payload = &logic;
839 logic.data = samples;
842 * If this cluster is not adjacent to the previously received
843 * cluster, then send the appropriate number of samples with the
844 * previous values to the sigrok session. This "decodes RLE".
846 for (ts = 0; ts < tsdiff; ts++) {
848 store_sr_sample(samples, i, ss->lastsample);
851 * If we have 1024 samples ready or we're at the
852 * end of submitting the padding samples, submit
853 * the packet to Sigrok. Since constant data is
854 * sent, duplication of data for rates above 50MHz
857 if ((i == 1023) || (ts == tsdiff - 1)) {
858 logic.length = (i + 1) * logic.unitsize;
859 for (j = 0; j < devc->samples_per_event; j++)
860 sigma_session_send(sdi, &packet);
865 * Parse the samples in current cluster and prepare them
866 * to be submitted to Sigrok. Cope with memory layouts that
867 * vary with the samplerate.
869 send_ptr = &samples[0];
872 for (i = 0; i < events_in_cluster; i++) {
873 item16 = sigma_dram_cluster_data(dram_cluster, i);
874 if (devc->cur_samplerate == SR_MHZ(200)) {
875 sample = sigma_deinterlace_200mhz_data(item16, 0);
876 store_sr_sample(samples, send_count++, sample);
877 sample = sigma_deinterlace_200mhz_data(item16, 1);
878 store_sr_sample(samples, send_count++, sample);
879 sample = sigma_deinterlace_200mhz_data(item16, 2);
880 store_sr_sample(samples, send_count++, sample);
881 sample = sigma_deinterlace_200mhz_data(item16, 3);
882 store_sr_sample(samples, send_count++, sample);
883 } else if (devc->cur_samplerate == SR_MHZ(100)) {
884 sample = sigma_deinterlace_100mhz_data(item16, 0);
885 store_sr_sample(samples, send_count++, sample);
886 sample = sigma_deinterlace_100mhz_data(item16, 1);
887 store_sr_sample(samples, send_count++, sample);
890 store_sr_sample(samples, send_count++, sample);
895 * If a trigger position applies, then provide the datafeed with
896 * the first part of data up to that position, then send the
899 int trigger_offset = 0;
902 * Trigger is not always accurate to sample because of
903 * pipeline delay. However, it always triggers before
904 * the actual event. We therefore look at the next
905 * samples to pinpoint the exact position of the trigger.
907 trigger_offset = get_trigger_offset(samples,
908 ss->lastsample, &devc->trigger);
910 if (trigger_offset > 0) {
911 trig_count = trigger_offset * devc->samples_per_event;
912 packet.type = SR_DF_LOGIC;
913 logic.length = trig_count * logic.unitsize;
914 sigma_session_send(sdi, &packet);
915 send_ptr += trig_count * logic.unitsize;
916 send_count -= trig_count;
919 /* Only send trigger if explicitly enabled. */
920 if (devc->use_triggers) {
921 packet.type = SR_DF_TRIGGER;
922 sr_session_send(sdi, &packet);
927 * Send the data after the trigger, or all of the received data
928 * if no trigger position applies.
931 packet.type = SR_DF_LOGIC;
932 logic.length = send_count * logic.unitsize;
933 logic.data = send_ptr;
934 sigma_session_send(sdi, &packet);
937 ss->lastsample = sample;
941 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
942 * Each event is 20ns apart, and can contain multiple samples.
944 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
945 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
946 * For 50 MHz and below, events contain one sample for each channel,
947 * spread 20 ns apart.
949 static int decode_chunk_ts(struct sigma_dram_line *dram_line,
950 uint16_t events_in_line,
951 uint32_t trigger_event,
952 struct sr_dev_inst *sdi)
954 struct sigma_dram_cluster *dram_cluster;
955 struct dev_context *devc;
956 unsigned int clusters_in_line;
957 unsigned int events_in_cluster;
959 uint32_t trigger_cluster, triggered;
962 clusters_in_line = events_in_line;
963 clusters_in_line += EVENTS_PER_CLUSTER - 1;
964 clusters_in_line /= EVENTS_PER_CLUSTER;
965 trigger_cluster = ~0;
968 /* Check if trigger is in this chunk. */
969 if (trigger_event < (64 * 7)) {
970 if (devc->cur_samplerate <= SR_MHZ(50)) {
971 trigger_event -= MIN(EVENTS_PER_CLUSTER - 1,
975 /* Find in which cluster the trigger occurred. */
976 trigger_cluster = trigger_event / EVENTS_PER_CLUSTER;
979 /* For each full DRAM cluster. */
980 for (i = 0; i < clusters_in_line; i++) {
981 dram_cluster = &dram_line->cluster[i];
983 /* The last cluster might not be full. */
984 if ((i == clusters_in_line - 1) &&
985 (events_in_line % EVENTS_PER_CLUSTER)) {
986 events_in_cluster = events_in_line % EVENTS_PER_CLUSTER;
988 events_in_cluster = EVENTS_PER_CLUSTER;
991 triggered = (i == trigger_cluster);
992 sigma_decode_dram_cluster(dram_cluster, events_in_cluster,
999 static int download_capture(struct sr_dev_inst *sdi)
1001 const uint32_t chunks_per_read = 32;
1003 struct dev_context *devc;
1004 struct sigma_dram_line *dram_line;
1006 uint32_t stoppos, triggerpos;
1009 uint32_t dl_lines_total, dl_lines_curr, dl_lines_done;
1010 uint32_t dl_first_line, dl_line;
1011 uint32_t dl_events_in_line;
1012 uint32_t trg_line, trg_event;
1015 dl_events_in_line = 64 * 7;
1019 dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line));
1023 sr_info("Downloading sample data.");
1026 * Ask the hardware to stop data acquisition. Reception of the
1027 * FORCESTOP request makes the hardware "disable RLE" (store
1028 * clusters to DRAM regardless of whether pin state changes) and
1029 * raise the POSTTRIGGERED flag.
1031 sigma_set_register(WRITE_MODE, WMR_FORCESTOP | WMR_SDRAMWRITEEN, devc);
1033 modestatus = sigma_get_register(READ_MODE, devc);
1034 } while (!(modestatus & RMR_POSTTRIGGERED));
1036 /* Set SDRAM Read Enable. */
1037 sigma_set_register(WRITE_MODE, WMR_SDRAMREADEN, devc);
1039 /* Get the current position. */
1040 sigma_read_pos(&stoppos, &triggerpos, devc);
1042 /* Check if trigger has fired. */
1043 modestatus = sigma_get_register(READ_MODE, devc);
1044 if (modestatus & RMR_TRIGGERED) {
1045 trg_line = triggerpos >> 9;
1046 trg_event = triggerpos & 0x1ff;
1049 devc->sent_samples = 0;
1052 * Determine how many "DRAM lines" of 1024 bytes each we need to
1053 * retrieve from the Sigma hardware, so that we have a complete
1054 * set of samples. Note that the last line need not contain 64
1055 * clusters, it might be partially filled only.
1057 * When RMR_ROUND is set, the circular buffer in DRAM has wrapped
1058 * around. Since the status of the very next line is uncertain in
1059 * that case, we skip it and start reading from the next line. The
1060 * circular buffer has 32K lines (0x8000).
1062 dl_lines_total = (stoppos >> 9) + 1;
1063 if (modestatus & RMR_ROUND) {
1064 dl_first_line = dl_lines_total + 1;
1065 dl_lines_total = 0x8000 - 2;
1070 while (dl_lines_total > dl_lines_done) {
1071 /* We can download only up-to 32 DRAM lines in one go! */
1072 dl_lines_curr = MIN(chunks_per_read, dl_lines_total - dl_lines_done);
1074 dl_line = dl_first_line + dl_lines_done;
1076 bufsz = sigma_read_dram(dl_line, dl_lines_curr,
1077 (uint8_t *)dram_line, devc);
1078 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1081 /* This is the first DRAM line, so find the initial timestamp. */
1082 if (dl_lines_done == 0) {
1083 devc->state.lastts =
1084 sigma_dram_cluster_ts(&dram_line[0].cluster[0]);
1085 devc->state.lastsample = 0;
1088 for (i = 0; i < dl_lines_curr; i++) {
1089 uint32_t trigger_event = ~0;
1090 /* The last "DRAM line" can be only partially full. */
1091 if (dl_lines_done + i == dl_lines_total - 1)
1092 dl_events_in_line = stoppos & 0x1ff;
1094 /* Test if the trigger happened on this line. */
1095 if (dl_lines_done + i == trg_line)
1096 trigger_event = trg_event;
1098 decode_chunk_ts(dram_line + i, dl_events_in_line,
1099 trigger_event, sdi);
1102 dl_lines_done += dl_lines_curr;
1105 std_session_send_df_end(sdi);
1107 sr_dev_acquisition_stop(sdi);
1115 * Periodically check the Sigma status when in CAPTURE mode. This routine
1116 * checks whether the configured sample count or sample time have passed,
1117 * and will stop acquisition and download the acquired samples.
1119 static int sigma_capture_mode(struct sr_dev_inst *sdi)
1121 struct dev_context *devc;
1122 uint64_t running_msec;
1123 uint64_t current_time;
1128 * Check if the selected sampling duration passed. Sample count
1129 * limits are covered by this enforced timeout as well.
1131 current_time = g_get_monotonic_time();
1132 running_msec = (current_time - devc->start_time) / 1000;
1133 if (running_msec >= devc->limit_msec)
1134 return download_capture(sdi);
1139 SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data)
1141 struct sr_dev_inst *sdi;
1142 struct dev_context *devc;
1150 if (devc->state.state == SIGMA_IDLE)
1153 if (devc->state.state == SIGMA_CAPTURE)
1154 return sigma_capture_mode(sdi);
1159 /* Build a LUT entry used by the trigger functions. */
1160 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1164 /* For each quad channel. */
1165 for (i = 0; i < 4; i++) {
1168 /* For each bit in LUT. */
1169 for (j = 0; j < 16; j++)
1171 /* For each channel in quad. */
1172 for (k = 0; k < 4; k++) {
1173 bit = 1 << (i * 4 + k);
1175 /* Set bit in entry */
1176 if ((mask & bit) && ((!(value & bit)) !=
1178 entry[i] &= ~(1 << j);
1183 /* Add a logical function to LUT mask. */
1184 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1185 int index, int neg, uint16_t *mask)
1188 int x[2][2], tmp, a, b, aset, bset, rset;
1190 memset(x, 0, 4 * sizeof(int));
1192 /* Trigger detect condition. */
1222 case OP_NOTRISEFALL:
1228 /* Transpose if neg is set. */
1230 for (i = 0; i < 2; i++) {
1231 for (j = 0; j < 2; j++) {
1233 x[i][j] = x[1 - i][1 - j];
1234 x[1 - i][1 - j] = tmp;
1239 /* Update mask with function. */
1240 for (i = 0; i < 16; i++) {
1241 a = (i >> (2 * index + 0)) & 1;
1242 b = (i >> (2 * index + 1)) & 1;
1244 aset = (*mask >> i) & 1;
1248 if (func == FUNC_AND || func == FUNC_NAND)
1250 else if (func == FUNC_OR || func == FUNC_NOR)
1252 else if (func == FUNC_XOR || func == FUNC_NXOR)
1255 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1266 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1267 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1268 * set at any time, but a full mask and value can be set (0/1).
1270 SR_PRIV int sigma_build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1273 uint16_t masks[2] = { 0, 0 };
1275 memset(lut, 0, sizeof(struct triggerlut));
1277 /* Constant for simple triggers. */
1280 /* Value/mask trigger support. */
1281 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1284 /* Rise/fall trigger support. */
1285 for (i = 0, j = 0; i < 16; i++) {
1286 if (devc->trigger.risingmask & (1 << i) ||
1287 devc->trigger.fallingmask & (1 << i))
1288 masks[j++] = 1 << i;
1291 build_lut_entry(masks[0], masks[0], lut->m0d);
1292 build_lut_entry(masks[1], masks[1], lut->m1d);
1294 /* Add glue logic */
1295 if (masks[0] || masks[1]) {
1296 /* Transition trigger. */
1297 if (masks[0] & devc->trigger.risingmask)
1298 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1299 if (masks[0] & devc->trigger.fallingmask)
1300 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1301 if (masks[1] & devc->trigger.risingmask)
1302 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1303 if (masks[1] & devc->trigger.fallingmask)
1304 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1306 /* Only value/mask trigger. */
1310 /* Triggertype: event. */
1311 lut->params.selres = 3;