2 * This file is part of the sigrok-firmware-fx2lafw project.
4 * Copyright (C) 2009 Ubixum, Inc.
5 * Copyright (C) 2015 Jochen Hoenicke
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include <fx2macros.h>
23 #include <autovector.h>
27 /* Change to support as many interfaces as you need. */
28 static BYTE altiface = 0;
30 static volatile __bit dosud = FALSE;
31 static volatile __bit dosuspend = FALSE;
33 extern __code BYTE highspd_dscr;
34 extern __code BYTE fullspd_dscr;
36 void resume_isr(void) __interrupt RESUME_ISR
41 void sudav_isr(void) __interrupt SUDAV_ISR
47 void usbreset_isr(void) __interrupt USBRESET_ISR
49 handle_hispeed(FALSE);
53 void hispeed_isr(void) __interrupt HISPEED_ISR
59 void suspend_isr(void) __interrupt SUSPEND_ISR
65 void timer2_isr(void) __interrupt TF2_ISR
67 /* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
73 * The gain stage is 2 stage approach. -6dB and -20dB on the first stage
74 * (attentuator). The second stage is then doing the gain by 3 different
75 * resistor values switched into the feedback loop.
78 * PC1=1; PC2=0; PC3= 0 -> Gain x0.1 = -20dB
79 * PC1=1; PC2=0; PC3= 1 -> Gain x0.2 = -14dB
80 * PC1=1; PC2=1; PC3= 0 -> Gain x0.4 = -8dB
81 * PC1=0; PC2=0; PC3= 0 -> Gain x0.5 = -6dB
82 * PC1=0; PC2=0; PC3= 1 -> Gain x1 = 0dB
83 * PC1=0; PC2=1; PC3= 0 -> Gain x2 = +6dB
86 * PE1=1; PC4=0; PC5= 0 -> Gain x0.1 = -20dB
87 * PE1=1; PC4=0; PC5= 1 -> Gain x0.2 = -14dB
88 * PE1=1; PC4=1; PC5= 0 -> Gain x0.4 = -8dB
89 * PE1=0; PC4=0; PC5= 0 -> Gain x0.5 = -6dB
90 * PE1=0; PC4=0; PC5= 1 -> Gain x1 = 0dB
91 * PE1=0; PC4=1; PC5= 0 -> Gain x2 = +6dB
93 static BOOL set_voltage(BYTE channel, BYTE val)
95 BYTE bits_C, bit_E, mask_C, mask_E;
120 } else if (channel == 1) {
150 IOC = (IOC & ~mask_C) | (bits_C & mask_C);
151 IOE = (IOE & ~mask_E) | (bit_E & mask_E);
157 * Each LSB in the nibble of the byte controls the coupling per channel.
159 * Setting PE3 disables AC coupling capacitor on CH0.
160 * Setting PE0 disables AC coupling capacitor on CH1.
162 static void set_coupling(BYTE coupling_cfg)
164 if (coupling_cfg & 0x01)
169 if (coupling_cfg & 0x10)
175 static BOOL set_numchannels(BYTE numchannels)
177 if (numchannels == 1 || numchannels == 2) {
178 BYTE fifocfg = 7 + numchannels;
179 EP2FIFOCFG = fifocfg;
180 EP6FIFOCFG = fifocfg;
187 static void clear_fifo(void)
200 static void stop_sampling(void)
204 INPKTEND = (altiface == 0) ? 6 : 2;
207 static void start_sampling(void)
213 for (i = 0; i < 1000; i++);
215 while (!(GPIFTRIG & 0x80))
222 GPIFTRIG = (altiface == 0) ? 6 : 4;
226 static void select_interface(BYTE alt)
228 const BYTE *pPacketSize = \
229 ((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
230 + (9 + (16 * alt) + 9 + 4);
239 EP6AUTOINLENL = pPacketSize[0];
240 EP6AUTOINLENH = pPacketSize[1];
246 EP2AUTOINLENL = pPacketSize[0];
247 EP2AUTOINLENH = pPacketSize[1] & 0x7;
248 EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
252 static const struct samplerate_info {
261 { 48, 0x80, 0, 3, 0, 0x00, 0xea },
262 { 30, 0x80, 0, 3, 0, 0x00, 0xaa },
263 { 24, 1, 0, 2, 1, 0x40, 0xea },
264 { 16, 1, 1, 2, 0, 0x40, 0xea },
265 { 15, 1, 0, 2, 1, 0x40, 0xaa },
266 { 12, 2, 1, 2, 0, 0x40, 0xea },
267 { 11, 1, 1, 2, 0, 0x40, 0xaa },
268 { 8, 3, 2, 2, 0, 0x40, 0xea },
269 { 6, 2, 2, 2, 0, 0x40, 0xaa },
270 { 5, 3, 2, 2, 0, 0x40, 0xaa },
271 { 4, 6, 5, 2, 0, 0x40, 0xea },
272 { 3, 5, 4, 2, 0, 0x40, 0xaa },
273 { 2, 12, 11, 2, 0, 0x40, 0xea },
274 { 1, 24, 23, 2, 0, 0x40, 0xea },
275 { 50, 48, 47, 2, 0, 0x40, 0xea },
276 { 20, 120, 119, 2, 0, 0x40, 0xea },
277 { 10, 240, 239, 2, 0, 0x40, 0xea },
280 static BOOL set_samplerate(BYTE rate)
284 while (samplerates[i].rate != rate) {
286 if (i == sizeof(samplerates) / sizeof(samplerates[0]))
290 IFCONFIG = samplerates[i].ifcfg;
293 AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
297 * The program for low-speed, e.g. 1 MHz, is:
298 * wait 24, CTLx=0, FIFO
302 * The program for 24 MHz is:
303 * wait 1, CTLx=0, FIFO
306 * The program for 30/48 MHz is:
307 * jump 0, CTLx=Z, FIFO, LOOP
309 * (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
312 /* LENGTH / BRANCH 0-7 */
313 EXTAUTODAT2 = samplerates[i].wait0;
314 EXTAUTODAT2 = samplerates[i].wait1;
323 EXTAUTODAT2 = samplerates[i].opc0;
324 EXTAUTODAT2 = samplerates[i].opc1;
325 EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
333 EXTAUTODAT2 = samplerates[i].out0;
334 EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
335 EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
342 /* LOGIC FUNCTION 0-7 */
352 for (i = 0; i < 96; i++)
358 static BOOL set_calibration_pulse(BYTE fs)
362 RCAP2L = -10000 & 0xff;
363 RCAP2H = (-10000 & 0xff00) >> 8;
366 RCAP2L = -1000 & 0xff;
367 RCAP2H = (-1000 & 0xff00) >> 8;
370 RCAP2L = (BYTE)(-100 & 0xff);
374 RCAP2L = (BYTE)(-20 & 0xff);
382 /* Set *alt_ifc to the current alt interface for ifc. */
383 BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
393 * Return TRUE if you set the interface requested.
395 * Note: This function should reconfigure and reset the endpoints
396 * according to the interface descriptors you provided.
398 BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
401 select_interface(alt_ifc);
406 BYTE handle_get_configuration(void)
408 /* We only support configuration 0. */
412 BOOL handle_set_configuration(BYTE cfg)
414 /* We only support configuration 0. */
420 BOOL handle_vendorcommand(BYTE cmd)
424 /* Clear EP0BCH/L for each valid command. */
425 if (cmd >= 0xe0 && cmd <= 0xe6) {
428 while (EP0CS & bmEPBUSY);
434 set_voltage(cmd - 0xe0, EP0BUF[0]);
437 set_samplerate(EP0BUF[0]);
444 set_numchannels(EP0BUF[0]);
447 set_coupling(EP0BUF[0]);
450 set_calibration_pulse(EP0BUF[0]);
454 return FALSE; /* Not handled by handlers. */
457 static void init(void)
462 /* In idle mode tristate all outputs. */
463 GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
464 GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
466 GPIFREADYSTAT = 0x00;
477 static void main(void)
484 /* Set up interrupts. */
493 /* Global (8051) interrupt enable. */
497 RCAP2L = -1000 & 0xff;
498 RCAP2H = (-1000 & 0xff00) >> 8;
523 /* Make sure ext wakeups are cleared. */
524 WAKEUPCS |= bmWU | bmWU2;
536 } while (!remote_wakeup_allowed && REMOTE_WAKEUP());
538 /* Resume (TRM 6.4). */
539 if (REMOTE_WAKEUP()) {
541 USBCS |= bmSIGRESUME;
543 USBCS &= ~bmSIGRESUME;