2 * This file is part of the libsigrok project.
4 * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
5 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
6 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
26 #include <glib/gstdio.h>
30 #include <libsigrok/libsigrok.h>
31 #include "libsigrok-internal.h"
34 #define FPGA_FIRMWARE_18 "saleae-logic16-fpga-18.bitstream"
35 #define FPGA_FIRMWARE_33 "saleae-logic16-fpga-33.bitstream"
37 #define MAX_SAMPLE_RATE SR_MHZ(100)
38 #define MAX_SAMPLE_RATE_X_CH SR_MHZ(300)
40 #define BASE_CLOCK_0_FREQ SR_MHZ(100)
41 #define BASE_CLOCK_1_FREQ SR_MHZ(160)
43 #define COMMAND_START_ACQUISITION 1
44 #define COMMAND_ABORT_ACQUISITION_ASYNC 2
45 #define COMMAND_WRITE_EEPROM 6
46 #define COMMAND_READ_EEPROM 7
47 #define COMMAND_WRITE_LED_TABLE 0x7a
48 #define COMMAND_SET_LED_MODE 0x7b
49 #define COMMAND_RETURN_TO_BOOTLOADER 0x7c
50 #define COMMAND_ABORT_ACQUISITION_SYNC 0x7d
51 #define COMMAND_FPGA_UPLOAD_INIT 0x7e
52 #define COMMAND_FPGA_UPLOAD_SEND_DATA 0x7f
53 #define COMMAND_FPGA_WRITE_REGISTER 0x80
54 #define COMMAND_FPGA_READ_REGISTER 0x81
55 #define COMMAND_GET_REVID 0x82
57 #define WRITE_EEPROM_COOKIE1 0x42
58 #define WRITE_EEPROM_COOKIE2 0x55
59 #define READ_EEPROM_COOKIE1 0x33
60 #define READ_EEPROM_COOKIE2 0x81
61 #define ABORT_ACQUISITION_SYNC_PATTERN 0x55
63 #define MAX_EMPTY_TRANSFERS 64
65 /* Register mappings for old and new bitstream versions */
67 enum fpga_register_id {
68 FPGA_REGISTER_VERSION,
69 FPGA_REGISTER_STATUS_CONTROL,
70 FPGA_REGISTER_CHANNEL_SELECT_LOW,
71 FPGA_REGISTER_CHANNEL_SELECT_HIGH,
72 FPGA_REGISTER_SAMPLE_RATE_DIVISOR,
73 FPGA_REGISTER_LED_BRIGHTNESS,
74 FPGA_REGISTER_PRIMER_DATA1,
75 FPGA_REGISTER_PRIMER_CONTROL,
77 FPGA_REGISTER_PRIMER_DATA2,
78 FPGA_REGISTER_MAX = FPGA_REGISTER_PRIMER_DATA2
81 enum fpga_status_control_bit {
82 FPGA_STATUS_CONTROL_BIT_RUNNING,
83 FPGA_STATUS_CONTROL_BIT_UPDATE,
84 FPGA_STATUS_CONTROL_BIT_UNKNOWN1,
85 FPGA_STATUS_CONTROL_BIT_OVERFLOW,
86 FPGA_STATUS_CONTROL_BIT_UNKNOWN2,
87 FPGA_STATUS_CONTROL_BIT_MAX = FPGA_STATUS_CONTROL_BIT_UNKNOWN2
92 FPGA_MODE_BIT_UNKNOWN1,
93 FPGA_MODE_BIT_UNKNOWN2,
94 FPGA_MODE_BIT_MAX = FPGA_MODE_BIT_UNKNOWN2
97 static const uint8_t fpga_register_map_old[FPGA_REGISTER_MAX + 1] = {
98 [FPGA_REGISTER_VERSION] = 0,
99 [FPGA_REGISTER_STATUS_CONTROL] = 1,
100 [FPGA_REGISTER_CHANNEL_SELECT_LOW] = 2,
101 [FPGA_REGISTER_CHANNEL_SELECT_HIGH] = 3,
102 [FPGA_REGISTER_SAMPLE_RATE_DIVISOR] = 4,
103 [FPGA_REGISTER_LED_BRIGHTNESS] = 5,
104 [FPGA_REGISTER_PRIMER_DATA1] = 6,
105 [FPGA_REGISTER_PRIMER_CONTROL] = 7,
106 [FPGA_REGISTER_MODE] = 10,
107 [FPGA_REGISTER_PRIMER_DATA2] = 12,
110 static const uint8_t fpga_register_map_new[FPGA_REGISTER_MAX + 1] = {
111 [FPGA_REGISTER_VERSION] = 7,
112 [FPGA_REGISTER_STATUS_CONTROL] = 15,
113 [FPGA_REGISTER_CHANNEL_SELECT_LOW] = 1,
114 [FPGA_REGISTER_CHANNEL_SELECT_HIGH] = 6,
115 [FPGA_REGISTER_SAMPLE_RATE_DIVISOR] = 11,
116 [FPGA_REGISTER_LED_BRIGHTNESS] = 5,
117 [FPGA_REGISTER_PRIMER_DATA1] = 14,
118 [FPGA_REGISTER_PRIMER_CONTROL] = 2,
119 [FPGA_REGISTER_MODE] = 4,
120 [FPGA_REGISTER_PRIMER_DATA2] = 3,
123 static const uint8_t fpga_status_control_bit_map_old[FPGA_STATUS_CONTROL_BIT_MAX + 1] = {
124 [FPGA_STATUS_CONTROL_BIT_RUNNING] = 0x01,
125 [FPGA_STATUS_CONTROL_BIT_UPDATE] = 0x02,
126 [FPGA_STATUS_CONTROL_BIT_UNKNOWN1] = 0x08,
127 [FPGA_STATUS_CONTROL_BIT_OVERFLOW] = 0x20,
128 [FPGA_STATUS_CONTROL_BIT_UNKNOWN2] = 0x40,
131 static const uint8_t fpga_status_control_bit_map_new[FPGA_STATUS_CONTROL_BIT_MAX + 1] = {
132 [FPGA_STATUS_CONTROL_BIT_RUNNING] = 0x20,
133 [FPGA_STATUS_CONTROL_BIT_UPDATE] = 0x08,
134 [FPGA_STATUS_CONTROL_BIT_UNKNOWN1] = 0x10,
135 [FPGA_STATUS_CONTROL_BIT_OVERFLOW] = 0x01,
136 [FPGA_STATUS_CONTROL_BIT_UNKNOWN2] = 0x04,
139 static const uint8_t fpga_mode_bit_map_old[FPGA_MODE_BIT_MAX + 1] = {
140 [FPGA_MODE_BIT_CLOCK] = 0x01,
141 [FPGA_MODE_BIT_UNKNOWN1] = 0x40,
142 [FPGA_MODE_BIT_UNKNOWN2] = 0x80,
145 static const uint8_t fpga_mode_bit_map_new[FPGA_MODE_BIT_MAX + 1] = {
146 [FPGA_MODE_BIT_CLOCK] = 0x04,
147 [FPGA_MODE_BIT_UNKNOWN1] = 0x80,
148 [FPGA_MODE_BIT_UNKNOWN2] = 0x01,
151 #define FPGA_REG(x) \
152 (devc->fpga_register_map[FPGA_REGISTER_ ## x])
154 #define FPGA_STATUS_CONTROL(x) \
155 (devc->fpga_status_control_bit_map[FPGA_STATUS_CONTROL_BIT_ ## x])
157 #define FPGA_MODE(x) \
158 (devc->fpga_mode_bit_map[FPGA_MODE_BIT_ ## x])
160 static void encrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt)
162 uint8_t state1 = 0x9b, state2 = 0x54;
166 for (i = 0; i < cnt; i++) {
168 t = (((v ^ state2 ^ 0x2b) - 0x05) ^ 0x35) - 0x39;
169 t = (((t ^ state1 ^ 0x5a) - 0xb0) ^ 0x38) - 0x45;
170 dest[i] = state2 = t;
175 static void decrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt)
177 uint8_t state1 = 0x9b, state2 = 0x54;
181 for (i = 0; i < cnt; i++) {
183 t = (((v + 0x45) ^ 0x38) + 0xb0) ^ 0x5a ^ state1;
184 t = (((t + 0x39) ^ 0x35) + 0x05) ^ 0x2b ^ state2;
185 dest[i] = state1 = t;
190 static int do_ep1_command(const struct sr_dev_inst *sdi,
191 const uint8_t *command, uint8_t cmd_len,
192 uint8_t *reply, uint8_t reply_len)
195 struct sr_usb_dev_inst *usb;
200 if (cmd_len < 1 || cmd_len > 64 || reply_len > 64 ||
201 !command || (reply_len > 0 && !reply))
204 encrypt(buf, command, cmd_len);
206 ret = libusb_bulk_transfer(usb->devhdl, 1, buf, cmd_len, &xfer, 1000);
208 sr_dbg("Failed to send EP1 command 0x%02x: %s.",
209 command[0], libusb_error_name(ret));
212 if (xfer != cmd_len) {
213 sr_dbg("Failed to send EP1 command 0x%02x: incorrect length "
214 "%d != %d.", command[0], xfer, cmd_len);
221 ret = libusb_bulk_transfer(usb->devhdl, 0x80 | 1, buf, reply_len,
224 sr_dbg("Failed to receive reply to EP1 command 0x%02x: %s.",
225 command[0], libusb_error_name(ret));
228 if (xfer != reply_len) {
229 sr_dbg("Failed to receive reply to EP1 command 0x%02x: "
230 "incorrect length %d != %d.", command[0], xfer, reply_len);
234 decrypt(reply, buf, reply_len);
239 static int read_eeprom(const struct sr_dev_inst *sdi,
240 uint8_t address, uint8_t length, uint8_t *buf)
242 uint8_t command[5] = {
250 return do_ep1_command(sdi, command, 5, buf, length);
253 static int upload_led_table(const struct sr_dev_inst *sdi,
254 const uint8_t *table, uint8_t offset, uint8_t cnt)
256 uint8_t chunk, command[64];
259 if (cnt < 1 || cnt + offset > 64 || !table)
263 chunk = (cnt > 32 ? 32 : cnt);
265 command[0] = COMMAND_WRITE_LED_TABLE;
268 memcpy(command + 3, table, chunk);
270 ret = do_ep1_command(sdi, command, 3 + chunk, NULL, 0);
282 static int set_led_mode(const struct sr_dev_inst *sdi,
283 uint8_t animate, uint16_t t2reload, uint8_t div,
286 uint8_t command[6] = {
287 COMMAND_SET_LED_MODE,
295 return do_ep1_command(sdi, command, 6, NULL, 0);
298 static int read_fpga_register(const struct sr_dev_inst *sdi,
299 uint8_t address, uint8_t *value)
301 uint8_t command[3] = {
302 COMMAND_FPGA_READ_REGISTER,
307 return do_ep1_command(sdi, command, 3, value, 1);
310 static int write_fpga_registers(const struct sr_dev_inst *sdi,
311 uint8_t (*regs)[2], uint8_t cnt)
316 if (cnt < 1 || cnt > 31)
319 command[0] = COMMAND_FPGA_WRITE_REGISTER;
321 for (i = 0; i < cnt; i++) {
322 command[2 + 2 * i] = regs[i][0];
323 command[3 + 2 * i] = regs[i][1];
326 return do_ep1_command(sdi, command, 2 * (cnt + 1), NULL, 0);
329 static int write_fpga_register(const struct sr_dev_inst *sdi,
330 uint8_t address, uint8_t value)
332 uint8_t regs[2] = { address, value };
334 return write_fpga_registers(sdi, ®s, 1);
337 static uint8_t map_eeprom_data(uint8_t v)
339 return (((v ^ 0x80) + 0x44) ^ 0xd5) + 0x69;
342 static int setup_register_mapping(const struct sr_dev_inst *sdi)
344 struct dev_context *devc;
349 if (devc->fpga_variant != FPGA_VARIANT_MCUPRO) {
353 * Check for newer bitstream version by polling the
354 * version register at the old and new location.
357 if ((ret = read_fpga_register(sdi, 0 /* No mapping */, ®0)) != SR_OK)
360 if ((ret = read_fpga_register(sdi, 7 /* No mapping */, ®7)) != SR_OK)
363 if (reg0 == 0 && reg7 > 0x10) {
364 sr_info("Original Saleae Logic16 using new bitstream.");
365 devc->fpga_variant = FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM;
367 sr_info("Original Saleae Logic16 using old bitstream.");
368 devc->fpga_variant = FPGA_VARIANT_ORIGINAL;
372 if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM) {
373 devc->fpga_register_map = fpga_register_map_new;
374 devc->fpga_status_control_bit_map = fpga_status_control_bit_map_new;
375 devc->fpga_mode_bit_map = fpga_mode_bit_map_new;
377 devc->fpga_register_map = fpga_register_map_old;
378 devc->fpga_status_control_bit_map = fpga_status_control_bit_map_old;
379 devc->fpga_mode_bit_map = fpga_mode_bit_map_old;
385 static int prime_fpga(const struct sr_dev_inst *sdi)
387 struct dev_context *devc = sdi->priv;
388 uint8_t eeprom_data[16];
389 uint8_t old_mode_reg, version;
390 uint8_t regs[8][2] = {
391 {FPGA_REG(MODE), 0x00},
392 {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1)},
393 {FPGA_REG(PRIMER_DATA2), 0},
394 {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1) | FPGA_MODE(UNKNOWN2)},
395 {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1)},
396 {FPGA_REG(PRIMER_DATA1), 0},
397 {FPGA_REG(PRIMER_CONTROL), 1},
398 {FPGA_REG(PRIMER_CONTROL), 0}
402 if ((ret = read_eeprom(sdi, 16, 16, eeprom_data)) != SR_OK)
405 if ((ret = read_fpga_register(sdi, FPGA_REG(MODE), &old_mode_reg)) != SR_OK)
408 regs[0][1] = (old_mode_reg &= ~FPGA_MODE(UNKNOWN2));
409 regs[1][1] |= old_mode_reg;
410 regs[3][1] |= old_mode_reg;
411 regs[4][1] |= old_mode_reg;
413 for (i = 0; i < 16; i++) {
414 regs[2][1] = eeprom_data[i];
415 regs[5][1] = map_eeprom_data(eeprom_data[i]);
417 ret = write_fpga_registers(sdi, ®s[2], 6);
419 ret = write_fpga_registers(sdi, ®s[0], 8);
424 if ((ret = write_fpga_register(sdi, FPGA_REG(MODE), old_mode_reg)) != SR_OK)
427 if ((ret = read_fpga_register(sdi, FPGA_REG(VERSION), &version)) != SR_OK)
430 if (version != 0x10 && version != 0x13 && version != 0x40 && version != 0x41) {
431 sr_err("Unsupported FPGA version: 0x%02x.", version);
438 static void make_heartbeat(uint8_t *table, int len)
442 memset(table, 0, len);
444 for (i = 0; i < 2; i++)
445 for (j = 0; j < len; j++)
446 *table++ = sin(j * G_PI / len) * 255;
449 static int configure_led(const struct sr_dev_inst *sdi)
454 make_heartbeat(table, 64);
455 if ((ret = upload_led_table(sdi, table, 0, 64)) != SR_OK)
458 return set_led_mode(sdi, 1, 6250, 0, 1);
461 static int upload_fpga_bitstream(const struct sr_dev_inst *sdi,
462 enum voltage_range vrange)
465 struct sr_resource bitstream;
466 struct dev_context *devc;
467 struct drv_context *drvc;
474 drvc = sdi->driver->context;
476 if (devc->cur_voltage_range == vrange)
479 if (devc->fpga_variant != FPGA_VARIANT_MCUPRO) {
481 case VOLTAGE_RANGE_18_33_V:
482 name = FPGA_FIRMWARE_18;
484 case VOLTAGE_RANGE_5_V:
485 name = FPGA_FIRMWARE_33;
488 sr_err("Unsupported voltage range.");
492 sr_info("Uploading FPGA bitstream '%s'.", name);
493 ret = sr_resource_open(drvc->sr_ctx, &bitstream,
494 SR_RESOURCE_FIRMWARE, name);
498 command[0] = COMMAND_FPGA_UPLOAD_INIT;
499 if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK) {
500 sr_resource_close(drvc->sr_ctx, &bitstream);
506 chunksize = sr_resource_read(drvc->sr_ctx, &bitstream,
507 &command[2], sizeof(command) - 2);
509 sr_resource_close(drvc->sr_ctx, &bitstream);
514 command[0] = COMMAND_FPGA_UPLOAD_SEND_DATA;
515 command[1] = chunksize;
517 ret = do_ep1_command(sdi, command, chunksize + 2,
520 sr_resource_close(drvc->sr_ctx, &bitstream);
525 sr_resource_close(drvc->sr_ctx, &bitstream);
526 sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", sum);
529 /* This needs to be called before accessing any FPGA registers. */
530 if ((ret = setup_register_mapping(sdi)) != SR_OK)
533 if ((ret = prime_fpga(sdi)) != SR_OK)
536 if ((ret = configure_led(sdi)) != SR_OK)
539 devc->cur_voltage_range = vrange;
543 static int abort_acquisition_sync(const struct sr_dev_inst *sdi)
545 static const uint8_t command[2] = {
546 COMMAND_ABORT_ACQUISITION_SYNC,
547 ABORT_ACQUISITION_SYNC_PATTERN,
549 uint8_t reply, expected_reply;
552 if ((ret = do_ep1_command(sdi, command, 2, &reply, 1)) != SR_OK)
555 expected_reply = ~command[1];
556 if (reply != expected_reply) {
557 sr_err("Invalid response for abort acquisition command: "
558 "0x%02x != 0x%02x.", reply, expected_reply);
565 SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
566 uint64_t samplerate, uint16_t channels)
568 uint8_t clock_select, sta_con_reg, mode_reg;
570 int i, ret, nchan = 0;
571 struct dev_context *devc;
575 if (samplerate == 0 || samplerate > MAX_SAMPLE_RATE) {
576 sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate);
580 if (BASE_CLOCK_0_FREQ % samplerate == 0 &&
581 (div = BASE_CLOCK_0_FREQ / samplerate) <= 256) {
583 } else if (BASE_CLOCK_1_FREQ % samplerate == 0 &&
584 (div = BASE_CLOCK_1_FREQ / samplerate) <= 256) {
587 sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate);
591 for (i = 0; i < 16; i++)
592 if (channels & (1U << i))
595 if (nchan * samplerate > MAX_SAMPLE_RATE_X_CH) {
596 sr_err("Unable to sample at %" PRIu64 "Hz "
597 "with this many channels.", samplerate);
601 ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range);
605 if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK)
608 /* Ignore FIFO overflow on previous capture */
609 sta_con_reg &= ~FPGA_STATUS_CONTROL(OVERFLOW);
611 if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg != FPGA_STATUS_CONTROL(UNKNOWN1)) {
612 sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x%02x. "
613 "Proceeding anyway.", sta_con_reg, FPGA_STATUS_CONTROL(UNKNOWN1));
616 if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2))) != SR_OK)
619 if ((ret = write_fpga_register(sdi, FPGA_REG(MODE), (clock_select? FPGA_MODE(CLOCK) : 0))) != SR_OK)
622 if ((ret = write_fpga_register(sdi, FPGA_REG(SAMPLE_RATE_DIVISOR), (uint8_t)(div - 1))) != SR_OK)
625 if ((ret = write_fpga_register(sdi, FPGA_REG(CHANNEL_SELECT_LOW), (uint8_t)(channels & 0xff))) != SR_OK)
628 if ((ret = write_fpga_register(sdi, FPGA_REG(CHANNEL_SELECT_HIGH), (uint8_t)(channels >> 8))) != SR_OK)
631 if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UPDATE))) != SR_OK)
634 if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2))) != SR_OK)
637 if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK)
640 if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg != (FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UNKNOWN1))) {
641 sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x%02x. "
642 "Proceeding anyway.", sta_con_reg, FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UNKNOWN1));
645 if ((ret = read_fpga_register(sdi, FPGA_REG(MODE), &mode_reg)) != SR_OK)
648 if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && mode_reg != (clock_select? FPGA_MODE(CLOCK) : 0)) {
649 sr_dbg("Invalid state at acquisition setup register 10: 0x%02x != 0x%02x. "
650 "Proceeding anyway.", mode_reg, (clock_select? FPGA_MODE(CLOCK) : 0));
656 SR_PRIV int logic16_start_acquisition(const struct sr_dev_inst *sdi)
658 static const uint8_t command[1] = {
659 COMMAND_START_ACQUISITION,
662 struct dev_context *devc;
666 if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK)
669 return write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(RUNNING));
672 SR_PRIV int logic16_abort_acquisition(const struct sr_dev_inst *sdi)
674 static const uint8_t command[1] = {
675 COMMAND_ABORT_ACQUISITION_ASYNC,
679 struct dev_context *devc;
683 if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK)
686 if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), 0x00)) != SR_OK)
689 if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK)
692 if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && (sta_con_reg & ~FPGA_STATUS_CONTROL(OVERFLOW)) != FPGA_STATUS_CONTROL(UNKNOWN1)) {
693 sr_dbg("Invalid state at acquisition stop: 0x%02x != 0x%02x.", sta_con_reg & ~0x20, FPGA_STATUS_CONTROL(UNKNOWN1));
698 if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL) {
701 if ((ret = read_fpga_register(sdi, 8, ®8)) != SR_OK)
704 if ((ret = read_fpga_register(sdi, 9, ®9)) != SR_OK)
708 if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg & FPGA_STATUS_CONTROL(OVERFLOW)) {
709 sr_warn("FIFO overflow, capture data may be truncated.");
716 SR_PRIV int logic16_init_device(const struct sr_dev_inst *sdi)
719 struct dev_context *devc;
724 devc->cur_voltage_range = VOLTAGE_RANGE_UNKNOWN;
726 if ((ret = abort_acquisition_sync(sdi)) != SR_OK)
729 if ((ret = read_eeprom(sdi, 8, 8, devc->eeprom_data)) != SR_OK)
732 /* mcupro Saleae16 has firmware pre-stored in FPGA.
733 So, we can query it right away. */
734 if (read_fpga_register(sdi, 0 /* No mapping */, &version) == SR_OK &&
735 (version == 0x40 || version == 0x41)) {
736 sr_info("mcupro Saleae16 detected.");
737 devc->fpga_variant = FPGA_VARIANT_MCUPRO;
739 sr_info("Original Saleae Logic16 detected.");
740 devc->fpga_variant = FPGA_VARIANT_ORIGINAL;
743 ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range);
750 static void finish_acquisition(struct sr_dev_inst *sdi)
752 struct dev_context *devc;
756 std_session_send_df_end(sdi);
758 usb_source_remove(sdi->session, devc->ctx);
760 devc->num_transfers = 0;
761 g_free(devc->transfers);
762 g_free(devc->convbuffer);
764 soft_trigger_logic_free(devc->stl);
769 static void free_transfer(struct libusb_transfer *transfer)
771 struct sr_dev_inst *sdi;
772 struct dev_context *devc;
775 sdi = transfer->user_data;
778 g_free(transfer->buffer);
779 transfer->buffer = NULL;
780 libusb_free_transfer(transfer);
782 for (i = 0; i < devc->num_transfers; i++) {
783 if (devc->transfers[i] == transfer) {
784 devc->transfers[i] = NULL;
789 devc->submitted_transfers--;
790 if (devc->submitted_transfers == 0)
791 finish_acquisition(sdi);
794 static void resubmit_transfer(struct libusb_transfer *transfer)
798 if ((ret = libusb_submit_transfer(transfer)) == LIBUSB_SUCCESS)
801 free_transfer(transfer);
802 /* TODO: Stop session? */
804 sr_err("%s: %s", __func__, libusb_error_name(ret));
807 static size_t convert_sample_data(struct dev_context *devc,
808 uint8_t *dest, size_t destcnt, const uint8_t *src, size_t srccnt)
810 uint16_t *channel_data;
813 uint16_t sample, channel_mask;
817 channel_data = devc->channel_data;
818 cur_channel = devc->cur_channel;
821 sample = src[0] | (src[1] << 8);
824 channel_mask = devc->channel_masks[cur_channel];
826 for (i = 15; i >= 0; --i, sample >>= 1)
828 channel_data[i] |= channel_mask;
830 if (++cur_channel == devc->num_channels) {
832 if (destcnt < 16 * 2) {
833 sr_err("Conversion buffer too small!");
836 memcpy(dest, channel_data, 16 * 2);
837 memset(channel_data, 0, 16 * 2);
844 devc->cur_channel = cur_channel;
849 SR_PRIV void LIBUSB_CALL logic16_receive_transfer(struct libusb_transfer *transfer)
851 gboolean packet_has_error = FALSE;
852 struct sr_datafeed_packet packet;
853 struct sr_datafeed_logic logic;
854 struct sr_dev_inst *sdi;
855 struct dev_context *devc;
856 size_t new_samples, num_samples;
858 int pre_trigger_samples;
860 sdi = transfer->user_data;
864 * If acquisition has already ended, just free any queued up
865 * transfer that come in.
867 if (devc->sent_samples < 0) {
868 free_transfer(transfer);
872 sr_info("receive_transfer(): status %s received %d bytes.",
873 libusb_error_name(transfer->status), transfer->actual_length);
875 switch (transfer->status) {
876 case LIBUSB_TRANSFER_NO_DEVICE:
877 devc->sent_samples = -2;
878 free_transfer(transfer);
880 case LIBUSB_TRANSFER_COMPLETED:
881 case LIBUSB_TRANSFER_TIMED_OUT: /* We may have received some data though. */
884 packet_has_error = TRUE;
888 if (transfer->actual_length & 1) {
889 sr_err("Got an odd number of bytes from the device. "
890 "This should not happen.");
891 /* Bail out right away. */
892 packet_has_error = TRUE;
893 devc->empty_transfer_count = MAX_EMPTY_TRANSFERS;
896 if (transfer->actual_length == 0 || packet_has_error) {
897 devc->empty_transfer_count++;
898 if (devc->empty_transfer_count > MAX_EMPTY_TRANSFERS) {
900 * The FX2 gave up. End the acquisition, the frontend
901 * will work out that the samplecount is short.
903 devc->sent_samples = -2;
904 free_transfer(transfer);
906 resubmit_transfer(transfer);
910 devc->empty_transfer_count = 0;
913 new_samples = convert_sample_data(devc, devc->convbuffer,
914 devc->convbuffer_size, transfer->buffer, transfer->actual_length);
916 if (new_samples > 0) {
917 if (devc->trigger_fired) {
918 /* Send the incoming transfer to the session bus. */
919 packet.type = SR_DF_LOGIC;
920 packet.payload = &logic;
921 if (devc->limit_samples &&
922 new_samples > devc->limit_samples - devc->sent_samples)
923 new_samples = devc->limit_samples - devc->sent_samples;
924 logic.length = new_samples * 2;
926 logic.data = devc->convbuffer;
927 sr_session_send(sdi, &packet);
928 devc->sent_samples += new_samples;
930 trigger_offset = soft_trigger_logic_check(devc->stl,
931 devc->convbuffer, new_samples * 2, &pre_trigger_samples);
932 if (trigger_offset > -1) {
933 devc->sent_samples += pre_trigger_samples;
934 packet.type = SR_DF_LOGIC;
935 packet.payload = &logic;
936 num_samples = new_samples - trigger_offset;
937 if (devc->limit_samples &&
938 num_samples > devc->limit_samples - devc->sent_samples)
939 num_samples = devc->limit_samples - devc->sent_samples;
940 logic.length = num_samples * 2;
942 logic.data = devc->convbuffer + trigger_offset * 2;
943 sr_session_send(sdi, &packet);
944 devc->sent_samples += num_samples;
946 devc->trigger_fired = TRUE;
950 if (devc->limit_samples &&
951 (uint64_t)devc->sent_samples >= devc->limit_samples) {
952 devc->sent_samples = -2;
953 free_transfer(transfer);
958 resubmit_transfer(transfer);