2 * This file is part of the sigrok project.
4 * Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com>
5 * Copyright (C) 2012 Renato Caldas <rmsc@fe.up.pt>
6 * Copyright (C) 2013 Lior Elazary <lelazary@yahoo.com>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
25 #define mso_trans(a, v) \
26 (((v) & 0x3f) | (((v) & 0xc0) << 6) | (((a) & 0xf) << 8) | \
27 ((~(v) & 0x20) << 1) | ((~(v) & 0x80) << 7))
29 static const char mso_head[] = { 0x40, 0x4c, 0x44, 0x53, 0x7e };
30 static const char mso_foot[] = { 0x7e };
32 extern SR_PRIV struct sr_dev_driver link_mso19_driver_info;
33 static struct sr_dev_driver *di = &link_mso19_driver_info;
35 SR_PRIV int mso_send_control_message(struct sr_serial_dev_inst *serial,
36 uint16_t payload[], int n)
38 int i, w, ret, s = n * 2 + sizeof(mso_head) + sizeof(mso_foot);
46 if (!(buf = g_try_malloc(s))) {
47 sr_err("Failed to malloc message buffer.");
53 memcpy(p, mso_head, sizeof(mso_head));
54 p += sizeof(mso_head);
56 for (i = 0; i < n; i++) {
57 *(uint16_t *) p = g_htons(payload[i]);
60 memcpy(p, mso_foot, sizeof(mso_foot));
64 ret = serial_write(serial, buf + w, s - w);
78 SR_PRIV int mso_configure_trigger(const struct sr_dev_inst *sdi)
80 struct dev_context *devc = sdi->priv;
81 uint16_t threshold_value = mso_calc_raw_from_mv(devc);
83 threshold_value = 0x153C;
84 uint8_t trigger_config = 0;
86 if (devc->trigger_slope)
87 trigger_config |= 0x04; //Trigger on falling edge
89 switch (devc->trigger_outsrc) {
91 trigger_config |= 0x00; //Trigger pulse output
94 trigger_config |= 0x08; //PWM DAC from the pattern generator buffer
97 trigger_config |= 0x18; //White noise
101 switch (devc->trigger_chan) {
103 trigger_config |= 0x00; //DSO level trigger //b00000000
106 trigger_config |= 0x20; //DSO level trigger & width < trigger_width
109 trigger_config |= 0x40; //DSO level trigger & width >= trigger_width
112 trigger_config |= 0x60; //LA combination trigger
116 //Last bit of trigger config reg 4 needs to be 1 for trigger enable,
117 //otherwise the trigger is not enabled
118 if (devc->use_trigger)
119 trigger_config |= 0x80;
122 ops[0] = mso_trans(3, threshold_value & 0xff);
123 //The trigger_config also holds the 2 MSB bits from the threshold value
124 ops[1] = mso_trans(4, trigger_config | (threshold_value >> 8) & 0x03);
125 ops[2] = mso_trans(5, devc->la_trigger);
126 ops[3] = mso_trans(6, devc->la_trigger_mask);
127 ops[4] = mso_trans(7, devc->trigger_holdoff[0]);
128 ops[5] = mso_trans(8, devc->trigger_holdoff[1]);
130 ops[6] = mso_trans(11,
131 devc->dso_trigger_width /
132 SR_HZ_TO_NS(devc->cur_rate));
134 /* Select the SPI/I2C trigger config bank */
135 ops[7] = mso_trans(REG_CTL2, (devc->ctlbase2 | BITS_CTL2_BANK(2)));
136 /* Configure the SPI/I2C protocol trigger */
137 ops[8] = mso_trans(REG_PT_WORD(0), devc->protocol_trigger.word[0]);
138 ops[9] = mso_trans(REG_PT_WORD(1), devc->protocol_trigger.word[1]);
139 ops[10] = mso_trans(REG_PT_WORD(2), devc->protocol_trigger.word[2]);
140 ops[11] = mso_trans(REG_PT_WORD(3), devc->protocol_trigger.word[3]);
141 ops[12] = mso_trans(REG_PT_MASK(0), devc->protocol_trigger.mask[0]);
142 ops[13] = mso_trans(REG_PT_MASK(1), devc->protocol_trigger.mask[1]);
143 ops[14] = mso_trans(REG_PT_MASK(2), devc->protocol_trigger.mask[2]);
144 ops[15] = mso_trans(REG_PT_MASK(3), devc->protocol_trigger.mask[3]);
145 ops[16] = mso_trans(REG_PT_SPIMODE, devc->protocol_trigger.spimode);
146 /* Select the default config bank */
147 ops[17] = mso_trans(REG_CTL2, devc->ctlbase2);
149 return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
152 SR_PRIV int mso_configure_threshold_level(const struct sr_dev_inst *sdi)
154 struct dev_context *devc = sdi->priv;
156 return mso_dac_out(sdi, la_threshold_map[devc->la_threshold]);
159 SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi)
161 uint16_t ops[] = { mso_trans(REG_BUFFER, 0) };
162 struct dev_context *devc = sdi->priv;
164 sr_dbg("Requesting buffer dump.");
165 return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
168 SR_PRIV int mso_arm(const struct sr_dev_inst *sdi)
170 struct dev_context *devc = sdi->priv;
172 mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETFSM),
173 mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_ARM),
174 mso_trans(REG_CTL1, devc->ctlbase1),
177 sr_dbg("Requesting trigger arm.");
178 return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
181 SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi)
183 struct dev_context *devc = sdi->priv;
185 mso_trans(REG_CTL1, devc->ctlbase1 | 8),
186 mso_trans(REG_CTL1, devc->ctlbase1),
189 sr_dbg("Requesting forced capture.");
190 return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
193 SR_PRIV int mso_dac_out(const struct sr_dev_inst *sdi, uint16_t val)
195 struct dev_context *devc = sdi->priv;
197 mso_trans(REG_DAC1, (val >> 8) & 0xff),
198 mso_trans(REG_DAC2, val & 0xff),
199 mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETADC),
202 sr_dbg("Setting dac word to 0x%x.", val);
203 return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
206 SR_PRIV inline uint16_t mso_calc_raw_from_mv(struct dev_context * devc)
208 return (uint16_t) (0x200 -
209 ((devc->dso_trigger_voltage / devc->dso_probe_attn) /
213 SR_PRIV int mso_parse_serial(const char *iSerial, const char *iProduct,
214 struct dev_context *devc)
216 unsigned int u1, u2, u3, u4, u5, u6;
219 /* FIXME: This code is in the original app, but I think its
220 * used only for the GUI */
221 /* if (strstr(iProduct, "REV_02") || strstr(iProduct, "REV_03"))
222 devc->num_sample_rates = 0x16;
224 devc->num_sample_rates = 0x10; */
227 if (iSerial[0] != '4' || sscanf(iSerial, "%5u%3u%3u%1u%1u%6u",
228 &u1, &u2, &u3, &u4, &u5, &u6) != 6)
232 devc->vbit = u1 / 10000;
234 devc->vbit = 4.19195;
235 devc->dac_offset = u2;
236 if (devc->dac_offset == 0)
237 devc->dac_offset = 0x1ff;
238 devc->offset_range = u3;
239 if (devc->offset_range == 0)
240 devc->offset_range = 0x17d;
243 * FIXME: There is more code on the original software to handle
244 * bigger iSerial strings, but as I can't test on my device
245 * I will not implement it yet
251 SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi)
253 struct dev_context *devc = sdi->priv;
256 ops[0] = mso_trans(REG_CTL1, (devc->ctlbase1 | BIT_CTL1_RESETADC));
257 ops[1] = mso_trans(REG_CTL1, devc->ctlbase1);
258 devc->ctlbase1 |= BIT_CTL1_ADC_UNKNOWN4;
260 sr_dbg("Requesting ADC reset.");
261 return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
264 SR_PRIV int mso_reset_fsm(struct sr_dev_inst *sdi)
266 struct dev_context *devc = sdi->priv;
269 devc->ctlbase1 |= BIT_CTL1_RESETFSM;
270 ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);
272 sr_dbg("Requesting ADC reset.");
273 return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
276 SR_PRIV int mso_toggle_led(struct sr_dev_inst *sdi, int state)
278 struct dev_context *devc = sdi->priv;
281 devc->ctlbase1 &= ~BIT_CTL1_LED;
283 devc->ctlbase1 |= BIT_CTL1_LED;
284 ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);
286 sr_dbg("Requesting LED toggle.");
287 return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
290 SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi)
292 struct sr_datafeed_packet packet;
293 struct dev_context *devc;
296 sr_source_remove(devc->serial->fd);
298 /* Terminate session */
299 packet.type = SR_DF_END;
300 sr_session_send(sdi, &packet);
303 SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val)
306 mso_trans(REG_CLKRATE1, (val >> 8) & 0xff),
307 mso_trans(REG_CLKRATE2, val & 0xff),
310 sr_dbg("Setting clkrate word to 0x%x.", val);
311 return mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
314 SR_PRIV int mso_configure_rate(const struct sr_dev_inst *sdi, uint32_t rate)
316 struct dev_context *devc = sdi->priv;
320 for (i = 0; i < ARRAY_SIZE(rate_map); i++) {
321 if (rate_map[i].rate == rate) {
322 devc->ctlbase2 = rate_map[i].slowmode;
323 ret = mso_clkrate_out(devc->serial, rate_map[i].val);
325 devc->cur_rate = rate;
331 sr_err("Unsupported rate.");
336 SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst *serial, uint8_t * info)
338 uint16_t ops[] = { mso_trans(REG_TRIGGER, 0) };
341 sr_dbg("Requesting trigger state.");
342 ret = mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
343 if (info == NULL || ret != SR_OK)
347 if (serial_read(serial, &buf, 1) != 1) /* FIXME: Need timeout */
351 sr_dbg("Trigger state is: 0x%x.", *info);
355 SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data)
357 struct sr_datafeed_packet packet;
358 struct sr_datafeed_logic logic;
359 struct sr_dev_inst *sdi;
363 struct drv_context *drvc = di->priv;
365 /* Find this device's devc struct by its fd. */
366 struct dev_context *devc = NULL;
367 for (l = drvc->instances; l; l = l->next) {
370 if (devc->serial->fd == fd)
375 /* Shouldn't happen. */
381 size_t s = serial_read(devc->serial, in, sizeof(in));
386 /* Check if we triggered, then send a command that we are ready
387 * to read the data */
388 if (devc->trigger_state != MSO_TRIGGER_DATAREADY) {
389 devc->trigger_state = in[0];
390 if (devc->trigger_state == MSO_TRIGGER_DATAREADY) {
391 mso_read_buffer(sdi);
394 mso_check_trigger(devc->serial, NULL);
399 /* the hardware always dumps 1024 samples, 24bits each */
400 if (devc->buffer_n < 3072) {
401 memcpy(devc->buffer + devc->buffer_n, in, s);
404 if (devc->buffer_n < 3072)
407 /* do the conversion */
408 uint8_t logic_out[1024];
409 double analog_out[1024];
410 for (i = 0; i < 1024; i++) {
411 /* FIXME: Need to do conversion to mV */
412 analog_out[i] = (devc->buffer[i * 3] & 0x3f) |
413 ((devc->buffer[i * 3 + 1] & 0xf) << 6);
414 logic_out[i] = ((devc->buffer[i * 3 + 1] & 0x30) >> 4) |
415 ((devc->buffer[i * 3 + 2] & 0x3f) << 2);
418 packet.type = SR_DF_LOGIC;
419 packet.payload = &logic;
422 logic.data = logic_out;
423 sr_session_send(cb_data, &packet);
425 devc->num_samples += 1024;
427 if (devc->limit_samples && devc->num_samples >= devc->limit_samples) {
428 sr_info("Requested number of samples reached.");
429 sdi->driver->dev_acquisition_stop(sdi, cb_data);
435 SR_PRIV int mso_configure_probes(const struct sr_dev_inst *sdi)
437 struct dev_context *devc;
438 struct sr_probe *probe;
444 devc->la_trigger_mask = 0xFF; //the mask for the LA_TRIGGER (bits set to 0 matter, those set to 1 are ignored).
445 devc->la_trigger = 0x00; //The value of the LA byte that generates a trigger event (in that mode).
446 devc->dso_trigger_voltage = 3;
447 devc->dso_probe_attn = 1;
448 devc->trigger_outsrc = 0;
449 devc->trigger_chan = 3; //LA combination trigger
450 devc->use_trigger = FALSE;
452 for (l = sdi->probes; l; l = l->next) {
453 probe = (struct sr_probe *)l->data;
454 if (probe->enabled == FALSE)
457 int probe_bit = 1 << (probe->index);
458 if (!(probe->trigger))
461 devc->use_trigger = TRUE;
462 //Configure trigger mask and value.
463 for (tc = probe->trigger; *tc; tc++) {
464 devc->la_trigger_mask &= ~probe_bit;
466 devc->la_trigger |= probe_bit;