2 * This file is part of the libsigrok project.
4 * Copyright (C) 2012 Bert Vermeulen <bert@biot.com>
5 * With protocol information from the hantekdso project,
6 * Copyright (C) 2008 Oleg Khudyakov <prcoder@gmail.com>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #ifndef LIBSIGROK_HARDWARE_HANTEK_DSO_DSO_H
23 #define LIBSIGROK_HARDWARE_HANTEK_DSO_DSO_H
25 #define LOG_PREFIX "hantek-dso"
27 #define USB_INTERFACE 0
28 #define USB_CONFIGURATION 1
29 #define DSO_EP_IN 0x86
30 #define DSO_EP_OUT 0x02
32 /* FX2 renumeration delay in ms */
33 #define MAX_RENUM_DELAY_MS 3000
35 #define MAX_CAPTURE_EMPTY 3
37 #define DEFAULT_VOLTAGE VDIV_500MV
38 #define DEFAULT_FRAMESIZE FRAMESIZE_SMALL
39 #define DEFAULT_TIMEBASE TIME_100us
40 #define DEFAULT_TRIGGER_SOURCE "CH1"
41 #define DEFAULT_COUPLING COUPLING_DC
42 #define DEFAULT_HORIZ_TRIGGERPOS 0.5
43 #define DEFAULT_VERT_OFFSET 0.5
44 #define DEFAULT_VERT_TRIGGERPOS 0.5
46 #define MAX_VERT_TRIGGER 0xfe
48 /* Hantek DSO-specific protocol values */
49 #define EEPROM_CHANNEL_OFFSETS 0x08
51 /* All models have this for their "fast" mode. */
52 #define FRAMESIZE_SMALL (10 * 1024)
54 enum control_requests {
55 CTRL_READ_EEPROM = 0xa2,
57 CTRL_BEGINCOMMAND = 0xb3,
58 CTRL_SETOFFSET = 0xb4,
59 CTRL_SETRELAYS = 0xb5,
64 CMD_SET_TRIGGER_SAMPLERATE,
76 /* Must match the coupling table. */
80 /* TODO not used, how to enable? */
84 /* Must match the timebases table. */
103 /* Must match the vdivs table. */
116 enum trigger_slopes {
121 enum trigger_sources {
130 CAPTURE_READY_8BIT = 2,
131 CAPTURE_READY_9BIT = 7,
132 CAPTURE_TIMEOUT = 127,
133 CAPTURE_UNKNOWN = 255,
151 /* VID/PID after cold boot */
154 /* VID/PID after firmware upload */
159 const uint64_t *buffersizes;
160 const char *firmware;
164 const struct dso_profile *profile;
165 uint64_t limit_frames;
167 GSList *enabled_channels;
168 /* We can't keep track of an FX2-based device after upgrading
169 * the firmware (it re-enumerates into a different device address
170 * after the upgrade) this is like a global lock. No device will open
171 * until a proper delay after the last device was upgraded.
174 int epin_maxpacketsize;
175 int capture_empty_count;
178 /* Oscilloscope settings. */
180 gboolean ch1_enabled;
181 gboolean ch2_enabled;
184 // voltage offset (vertical position)
187 float voffset_trigger;
188 uint16_t channel_levels[2][9][2];
189 unsigned int framesize;
193 float triggerposition;
197 unsigned int samp_received;
198 unsigned int samp_buffered;
199 unsigned int trigger_offset;
200 unsigned char *framebuf;
203 SR_PRIV int dso_open(struct sr_dev_inst *sdi);
204 SR_PRIV void dso_close(struct sr_dev_inst *sdi);
205 SR_PRIV int dso_enable_trigger(const struct sr_dev_inst *sdi);
206 SR_PRIV int dso_force_trigger(const struct sr_dev_inst *sdi);
207 SR_PRIV int dso_init(const struct sr_dev_inst *sdi);
208 SR_PRIV int dso_get_capturestate(const struct sr_dev_inst *sdi,
209 uint8_t *capturestate, uint32_t *trigger_offset);
210 SR_PRIV int dso_capture_start(const struct sr_dev_inst *sdi);
211 SR_PRIV int dso_get_channeldata(const struct sr_dev_inst *sdi,
212 libusb_transfer_cb_fn cb);