2 * This file is part of the sigrok project.
4 * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX SIGMA Logic Analyzer Driver
27 #include <glib/gstdio.h>
32 #include "sigrok-internal.h"
33 #include "asix-sigma.h"
35 #define USB_VENDOR 0xa600
36 #define USB_PRODUCT 0xa000
37 #define USB_DESCRIPTION "ASIX SIGMA"
38 #define USB_VENDOR_NAME "ASIX"
39 #define USB_MODEL_NAME "SIGMA"
40 #define USB_MODEL_VERSION ""
41 #define TRIGGER_TYPES "rf10"
44 static GSList *dev_insts = NULL;
46 static uint64_t supported_samplerates[] = {
61 * Probe numbers seem to go from 1-16, according to this image:
62 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
63 * (the cable has two additional GND pins, and a TI and TO pin)
65 static const char *probe_names[NUM_PROBES + 1] = {
85 static struct sr_samplerates samplerates = {
89 supported_samplerates,
92 static int hwcaps[] = {
93 SR_HWCAP_LOGIC_ANALYZER,
95 SR_HWCAP_CAPTURE_RATIO,
102 /* Force the FPGA to reboot. */
103 static uint8_t suicide[] = {
104 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
107 /* Prepare to upload firmware (FPGA specific). */
108 static uint8_t init[] = {
109 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
112 /* Initialize the logic analyzer mode. */
113 static uint8_t logic_mode_start[] = {
114 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
115 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
118 static const char *firmware_files[] = {
119 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
120 "asix-sigma-100.fw", /* 100 MHz */
121 "asix-sigma-200.fw", /* 200 MHz */
122 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
123 "asix-sigma-phasor.fw", /* Frequency counter */
126 static int hw_dev_acquisition_stop(int dev_index, void *cb_data);
128 static int sigma_read(void *buf, size_t size, struct context *ctx)
132 ret = ftdi_read_data(&ctx->ftdic, (unsigned char *)buf, size);
134 sr_err("sigma: ftdi_read_data failed: %s",
135 ftdi_get_error_string(&ctx->ftdic));
141 static int sigma_write(void *buf, size_t size, struct context *ctx)
145 ret = ftdi_write_data(&ctx->ftdic, (unsigned char *)buf, size);
147 sr_err("sigma: ftdi_write_data failed: %s",
148 ftdi_get_error_string(&ctx->ftdic));
149 } else if ((size_t) ret != size) {
150 sr_err("sigma: ftdi_write_data did not complete write.");
156 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
160 uint8_t buf[len + 2];
163 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
164 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
166 for (i = 0; i < len; ++i) {
167 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
168 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
171 return sigma_write(buf, idx, ctx);
174 static int sigma_set_register(uint8_t reg, uint8_t value, struct context *ctx)
176 return sigma_write_register(reg, &value, 1, ctx);
179 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
184 buf[0] = REG_ADDR_LOW | (reg & 0xf);
185 buf[1] = REG_ADDR_HIGH | (reg >> 4);
186 buf[2] = REG_READ_ADDR;
188 sigma_write(buf, sizeof(buf), ctx);
190 return sigma_read(data, len, ctx);
193 static uint8_t sigma_get_register(uint8_t reg, struct context *ctx)
197 if (1 != sigma_read_register(reg, &value, 1, ctx)) {
198 sr_err("sigma: sigma_get_register: 1 byte expected");
205 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
209 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
211 REG_READ_ADDR | NEXT_REG,
212 REG_READ_ADDR | NEXT_REG,
213 REG_READ_ADDR | NEXT_REG,
214 REG_READ_ADDR | NEXT_REG,
215 REG_READ_ADDR | NEXT_REG,
216 REG_READ_ADDR | NEXT_REG,
220 sigma_write(buf, sizeof(buf), ctx);
222 sigma_read(result, sizeof(result), ctx);
224 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
225 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
227 /* Not really sure why this must be done, but according to spec. */
228 if ((--*stoppos & 0x1ff) == 0x1ff)
231 if ((*--triggerpos & 0x1ff) == 0x1ff)
237 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
238 uint8_t *data, struct context *ctx)
244 /* Send the startchunk. Index start with 1. */
245 buf[0] = startchunk >> 8;
246 buf[1] = startchunk & 0xff;
247 sigma_write_register(WRITE_MEMROW, buf, 2, ctx);
250 buf[idx++] = REG_DRAM_BLOCK;
251 buf[idx++] = REG_DRAM_WAIT_ACK;
253 for (i = 0; i < numchunks; ++i) {
254 /* Alternate bit to copy from DRAM to cache. */
255 if (i != (numchunks - 1))
256 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
258 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
260 if (i != (numchunks - 1))
261 buf[idx++] = REG_DRAM_WAIT_ACK;
264 sigma_write(buf, idx, ctx);
266 return sigma_read(data, numchunks * CHUNK_SIZE, ctx);
269 /* Upload trigger look-up tables to Sigma. */
270 static int sigma_write_trigger_lut(struct triggerlut *lut, struct context *ctx)
276 /* Transpose the table and send to Sigma. */
277 for (i = 0; i < 16; ++i) {
282 if (lut->m2d[0] & bit)
284 if (lut->m2d[1] & bit)
286 if (lut->m2d[2] & bit)
288 if (lut->m2d[3] & bit)
298 if (lut->m0d[0] & bit)
300 if (lut->m0d[1] & bit)
302 if (lut->m0d[2] & bit)
304 if (lut->m0d[3] & bit)
307 if (lut->m1d[0] & bit)
309 if (lut->m1d[1] & bit)
311 if (lut->m1d[2] & bit)
313 if (lut->m1d[3] & bit)
316 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
318 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, ctx);
321 /* Send the parameters */
322 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
323 sizeof(lut->params), ctx);
328 /* Generate the bitbang stream for programming the FPGA. */
329 static int bin2bitbang(const char *filename,
330 unsigned char **buf, size_t *buf_size)
333 unsigned long file_size;
334 unsigned long offset = 0;
337 unsigned long fwsize = 0;
338 const int buffer_size = 65536;
341 uint32_t imm = 0x3f6df2ab;
343 f = g_fopen(filename, "rb");
345 sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename);
349 if (-1 == fseek(f, 0, SEEK_END)) {
350 sr_err("sigma: fseek on %s failed", filename);
355 file_size = ftell(f);
357 fseek(f, 0, SEEK_SET);
359 if (!(firmware = g_try_malloc(buffer_size))) {
360 sr_err("sigma: %s: firmware malloc failed", __func__);
362 return SR_ERR_MALLOC;
365 while ((c = getc(f)) != EOF) {
366 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
367 firmware[fwsize++] = c ^ imm;
371 if(fwsize != file_size) {
372 sr_err("sigma: %s: Error reading firmware", filename);
378 *buf_size = fwsize * 2 * 8;
380 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
382 sr_err("sigma: %s: buf/p malloc failed", __func__);
384 return SR_ERR_MALLOC;
387 for (i = 0; i < fwsize; ++i) {
388 for (bit = 7; bit >= 0; --bit) {
389 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
390 p[offset++] = v | 0x01;
397 if (offset != *buf_size) {
399 sr_err("sigma: Error reading firmware %s "
400 "offset=%ld, file_size=%ld, buf_size=%zd.",
401 filename, offset, file_size, *buf_size);
409 static int hw_init(const char *devinfo)
411 struct sr_dev_inst *sdi;
413 struct ftdi_device_list *devlist;
417 /* Avoid compiler warnings. */
420 if (!(ctx = g_try_malloc(sizeof(struct context)))) {
421 sr_err("sigma: %s: ctx malloc failed", __func__);
422 return SR_ERR_MALLOC;
425 ftdi_init(&ctx->ftdic);
427 /* Look for SIGMAs. */
429 if (ftdi_usb_find_all(&ctx->ftdic, &devlist,
430 USB_VENDOR, USB_PRODUCT) < 0)
433 /* Make sure it's a version 1 or 2 SIGMA. */
434 ftdi_usb_get_strings(&ctx->ftdic, devlist->dev, NULL, 0, NULL, 0,
435 serial_txt, sizeof(serial_txt));
436 sscanf(serial_txt, "%x", &serial);
438 if (serial < 0xa6010000 || serial > 0xa602ffff ) {
439 sr_err("sigma: Only SIGMA and SIGMA2 are supported "
440 "in this version of Sigrok.");
444 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
446 ctx->cur_samplerate = 0;
449 ctx->cur_firmware = -1;
451 ctx->samples_per_event = 0;
452 ctx->capture_ratio = 50;
453 ctx->use_triggers = 0;
455 /* Register SIGMA device. */
456 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
457 USB_MODEL_NAME, USB_MODEL_VERSION))) {
458 sr_err("sigma: %s: sdi was NULL", __func__);
464 dev_insts = g_slist_append(dev_insts, sdi);
466 /* We will open the device again when we need it. */
467 ftdi_list_free(&devlist);
476 static int upload_firmware(int firmware_idx, struct context *ctx)
482 unsigned char result[32];
483 char firmware_path[128];
485 /* Make sure it's an ASIX SIGMA. */
486 if ((ret = ftdi_usb_open_desc(&ctx->ftdic,
487 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
488 sr_err("sigma: ftdi_usb_open failed: %s",
489 ftdi_get_error_string(&ctx->ftdic));
493 if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
494 sr_err("sigma: ftdi_set_bitmode failed: %s",
495 ftdi_get_error_string(&ctx->ftdic));
499 /* Four times the speed of sigmalogan - Works well. */
500 if ((ret = ftdi_set_baudrate(&ctx->ftdic, 750000)) < 0) {
501 sr_err("sigma: ftdi_set_baudrate failed: %s",
502 ftdi_get_error_string(&ctx->ftdic));
506 /* Force the FPGA to reboot. */
507 sigma_write(suicide, sizeof(suicide), ctx);
508 sigma_write(suicide, sizeof(suicide), ctx);
509 sigma_write(suicide, sizeof(suicide), ctx);
510 sigma_write(suicide, sizeof(suicide), ctx);
512 /* Prepare to upload firmware (FPGA specific). */
513 sigma_write(init, sizeof(init), ctx);
515 ftdi_usb_purge_buffers(&ctx->ftdic);
517 /* Wait until the FPGA asserts INIT_B. */
519 ret = sigma_read(result, 1, ctx);
520 if (result[0] & 0x20)
524 /* Prepare firmware. */
525 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
526 firmware_files[firmware_idx]);
528 if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
529 sr_err("sigma: An error occured while reading the firmware: %s",
534 /* Upload firmare. */
535 sr_info("sigma: Uploading firmware %s", firmware_files[firmware_idx]);
536 sigma_write(buf, buf_size, ctx);
540 if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0x00, BITMODE_RESET)) < 0) {
541 sr_err("sigma: ftdi_set_bitmode failed: %s",
542 ftdi_get_error_string(&ctx->ftdic));
546 ftdi_usb_purge_buffers(&ctx->ftdic);
548 /* Discard garbage. */
549 while (1 == sigma_read(&pins, 1, ctx))
552 /* Initialize the logic analyzer mode. */
553 sigma_write(logic_mode_start, sizeof(logic_mode_start), ctx);
555 /* Expect a 3 byte reply. */
556 ret = sigma_read(result, 3, ctx);
558 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
559 sr_err("sigma: Configuration failed. Invalid reply received.");
563 ctx->cur_firmware = firmware_idx;
565 sr_info("sigma: Firmware uploaded");
570 static int hw_dev_open(int dev_index)
572 struct sr_dev_inst *sdi;
576 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
581 /* Make sure it's an ASIX SIGMA. */
582 if ((ret = ftdi_usb_open_desc(&ctx->ftdic,
583 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
585 sr_err("sigma: ftdi_usb_open failed: %s",
586 ftdi_get_error_string(&ctx->ftdic));
591 sdi->status = SR_ST_ACTIVE;
596 static int set_samplerate(struct sr_dev_inst *sdi, uint64_t samplerate)
599 struct context *ctx = sdi->priv;
601 for (i = 0; supported_samplerates[i]; i++) {
602 if (supported_samplerates[i] == samplerate)
605 if (supported_samplerates[i] == 0)
606 return SR_ERR_SAMPLERATE;
608 if (samplerate <= SR_MHZ(50)) {
609 ret = upload_firmware(0, ctx);
610 ctx->num_probes = 16;
612 if (samplerate == SR_MHZ(100)) {
613 ret = upload_firmware(1, ctx);
616 else if (samplerate == SR_MHZ(200)) {
617 ret = upload_firmware(2, ctx);
621 ctx->cur_samplerate = samplerate;
622 ctx->period_ps = 1000000000000 / samplerate;
623 ctx->samples_per_event = 16 / ctx->num_probes;
624 ctx->state.state = SIGMA_IDLE;
630 * In 100 and 200 MHz mode, only a single pin rising/falling can be
631 * set as trigger. In other modes, two rising/falling triggers can be set,
632 * in addition to value/mask trigger for any number of probes.
634 * The Sigma supports complex triggers using boolean expressions, but this
635 * has not been implemented yet.
637 static int configure_probes(struct sr_dev_inst *sdi, GSList *probes)
639 struct context *ctx = sdi->priv;
640 struct sr_probe *probe;
645 memset(&ctx->trigger, 0, sizeof(struct sigma_trigger));
647 for (l = probes; l; l = l->next) {
648 probe = (struct sr_probe *)l->data;
649 probebit = 1 << (probe->index - 1);
651 if (!probe->enabled || !probe->trigger)
654 if (ctx->cur_samplerate >= SR_MHZ(100)) {
655 /* Fast trigger support. */
657 sr_err("sigma: ASIX SIGMA only supports a single "
658 "pin trigger in 100 and 200MHz mode.");
661 if (probe->trigger[0] == 'f')
662 ctx->trigger.fallingmask |= probebit;
663 else if (probe->trigger[0] == 'r')
664 ctx->trigger.risingmask |= probebit;
666 sr_err("sigma: ASIX SIGMA only supports "
667 "rising/falling trigger in 100 "
674 /* Simple trigger support (event). */
675 if (probe->trigger[0] == '1') {
676 ctx->trigger.simplevalue |= probebit;
677 ctx->trigger.simplemask |= probebit;
679 else if (probe->trigger[0] == '0') {
680 ctx->trigger.simplevalue &= ~probebit;
681 ctx->trigger.simplemask |= probebit;
683 else if (probe->trigger[0] == 'f') {
684 ctx->trigger.fallingmask |= probebit;
687 else if (probe->trigger[0] == 'r') {
688 ctx->trigger.risingmask |= probebit;
693 * Actually, Sigma supports 2 rising/falling triggers,
694 * but they are ORed and the current trigger syntax
695 * does not permit ORed triggers.
697 if (trigger_set > 1) {
698 sr_err("sigma: ASIX SIGMA only supports 1 "
699 "rising/falling triggers.");
705 ctx->use_triggers = 1;
711 static int hw_dev_close(int dev_index)
713 struct sr_dev_inst *sdi;
716 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) {
717 sr_err("sigma: %s: sdi was NULL", __func__);
721 if (!(ctx = sdi->priv)) {
722 sr_err("sigma: %s: sdi->priv was NULL", __func__);
727 if (sdi->status == SR_ST_ACTIVE)
728 ftdi_usb_close(&ctx->ftdic);
730 sdi->status = SR_ST_INACTIVE;
735 static int hw_cleanup(void)
738 struct sr_dev_inst *sdi;
741 /* Properly close all devices. */
742 for (l = dev_insts; l; l = l->next) {
743 if (!(sdi = l->data)) {
744 /* Log error, but continue cleaning up the rest. */
745 sr_err("sigma: %s: sdi was NULL, continuing", __func__);
749 sr_dev_inst_free(sdi);
751 g_slist_free(dev_insts);
757 static void *hw_dev_info_get(int dev_index, int dev_info_id)
759 struct sr_dev_inst *sdi;
763 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) {
764 sr_err("sigma: %s: sdi was NULL", __func__);
770 switch (dev_info_id) {
774 case SR_DI_NUM_PROBES:
775 info = GINT_TO_POINTER(NUM_PROBES);
777 case SR_DI_PROBE_NAMES:
780 case SR_DI_SAMPLERATES:
783 case SR_DI_TRIGGER_TYPES:
784 info = (char *)TRIGGER_TYPES;
786 case SR_DI_CUR_SAMPLERATE:
787 info = &ctx->cur_samplerate;
794 static int hw_dev_status_get(int dev_index)
796 struct sr_dev_inst *sdi;
798 sdi = sr_dev_inst_get(dev_insts, dev_index);
802 return SR_ST_NOT_FOUND;
805 static int *hw_hwcap_get_all(void)
810 static int hw_dev_config_set(int dev_index, int hwcap, void *value)
812 struct sr_dev_inst *sdi;
816 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
821 if (hwcap == SR_HWCAP_SAMPLERATE) {
822 ret = set_samplerate(sdi, *(uint64_t *)value);
823 } else if (hwcap == SR_HWCAP_PROBECONFIG) {
824 ret = configure_probes(sdi, value);
825 } else if (hwcap == SR_HWCAP_LIMIT_MSEC) {
826 ctx->limit_msec = *(uint64_t *)value;
827 if (ctx->limit_msec > 0)
831 } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) {
832 ctx->capture_ratio = *(uint64_t *)value;
833 if (ctx->capture_ratio < 0 || ctx->capture_ratio > 100)
844 /* Software trigger to determine exact trigger position. */
845 static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
846 struct sigma_trigger *t)
850 for (i = 0; i < 8; ++i) {
852 last_sample = samples[i-1];
854 /* Simple triggers. */
855 if ((samples[i] & t->simplemask) != t->simplevalue)
859 if ((last_sample & t->risingmask) != 0 || (samples[i] &
860 t->risingmask) != t->risingmask)
864 if ((last_sample & t->fallingmask) != t->fallingmask ||
865 (samples[i] & t->fallingmask) != 0)
871 /* If we did not match, return original trigger pos. */
876 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
877 * Each event is 20ns apart, and can contain multiple samples.
879 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
880 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
881 * For 50 MHz and below, events contain one sample for each channel,
882 * spread 20 ns apart.
884 static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
885 uint16_t *lastsample, int triggerpos,
886 uint16_t limit_chunk, void *cb_data)
888 struct sr_dev_inst *sdi = cb_data;
889 struct context *ctx = sdi->priv;
891 uint16_t samples[65536 * ctx->samples_per_event];
892 struct sr_datafeed_packet packet;
893 struct sr_datafeed_logic logic;
894 int i, j, k, l, numpad, tosend;
895 size_t n = 0, sent = 0;
896 int clustersize = EVENTS_PER_CLUSTER * ctx->samples_per_event;
901 /* Check if trigger is in this chunk. */
902 if (triggerpos != -1) {
903 if (ctx->cur_samplerate <= SR_MHZ(50))
904 triggerpos -= EVENTS_PER_CLUSTER - 1;
909 /* Find in which cluster the trigger occured. */
910 triggerts = triggerpos / 7;
914 for (i = 0; i < 64; ++i) {
915 ts = *(uint16_t *) &buf[i * 16];
916 tsdiff = ts - *lastts;
919 /* Decode partial chunk. */
920 if (limit_chunk && ts > limit_chunk)
923 /* Pad last sample up to current point. */
924 numpad = tsdiff * ctx->samples_per_event - clustersize;
926 for (j = 0; j < numpad; ++j)
927 samples[j] = *lastsample;
932 /* Send samples between previous and this timestamp to sigrok. */
935 tosend = MIN(2048, n - sent);
937 packet.type = SR_DF_LOGIC;
938 packet.payload = &logic;
939 logic.length = tosend * sizeof(uint16_t);
941 logic.data = samples + sent;
942 sr_session_send(ctx->session_dev_id, &packet);
948 event = (uint16_t *) &buf[i * 16 + 2];
951 /* For each event in cluster. */
952 for (j = 0; j < 7; ++j) {
954 /* For each sample in event. */
955 for (k = 0; k < ctx->samples_per_event; ++k) {
958 /* For each probe. */
959 for (l = 0; l < ctx->num_probes; ++l)
960 cur_sample |= (!!(event[j] & (1 << (l *
961 ctx->samples_per_event + k)))) << l;
963 samples[n++] = cur_sample;
967 /* Send data up to trigger point (if triggered). */
969 if (i == triggerts) {
971 * Trigger is not always accurate to sample because of
972 * pipeline delay. However, it always triggers before
973 * the actual event. We therefore look at the next
974 * samples to pinpoint the exact position of the trigger.
976 tosend = get_trigger_offset(samples, *lastsample,
980 packet.type = SR_DF_LOGIC;
981 packet.payload = &logic;
982 logic.length = tosend * sizeof(uint16_t);
984 logic.data = samples;
985 sr_session_send(ctx->session_dev_id, &packet);
990 /* Only send trigger if explicitly enabled. */
991 if (ctx->use_triggers) {
992 packet.type = SR_DF_TRIGGER;
993 sr_session_send(ctx->session_dev_id, &packet);
997 /* Send rest of the chunk to sigrok. */
1001 packet.type = SR_DF_LOGIC;
1002 packet.payload = &logic;
1003 logic.length = tosend * sizeof(uint16_t);
1005 logic.data = samples + sent;
1006 sr_session_send(ctx->session_dev_id, &packet);
1009 *lastsample = samples[n - 1];
1015 static int receive_data(int fd, int revents, void *cb_data)
1017 struct sr_dev_inst *sdi = cb_data;
1018 struct context *ctx = sdi->priv;
1019 struct sr_datafeed_packet packet;
1020 const int chunks_per_read = 32;
1021 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1022 int bufsz, numchunks, i, newchunks;
1023 uint64_t running_msec;
1026 /* Avoid compiler warnings. */
1030 /* Get the current position. */
1031 sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx);
1033 numchunks = (ctx->state.stoppos + 511) / 512;
1035 if (ctx->state.state == SIGMA_IDLE)
1038 if (ctx->state.state == SIGMA_CAPTURE) {
1039 /* Check if the timer has expired, or memory is full. */
1040 gettimeofday(&tv, 0);
1041 running_msec = (tv.tv_sec - ctx->start_tv.tv_sec) * 1000 +
1042 (tv.tv_usec - ctx->start_tv.tv_usec) / 1000;
1044 if (running_msec < ctx->limit_msec && numchunks < 32767)
1045 return TRUE; /* While capturing... */
1047 hw_dev_acquisition_stop(sdi->index, sdi);
1049 } else if (ctx->state.state == SIGMA_DOWNLOAD) {
1050 if (ctx->state.chunks_downloaded >= numchunks) {
1051 /* End of samples. */
1052 packet.type = SR_DF_END;
1053 sr_session_send(ctx->session_dev_id, &packet);
1055 ctx->state.state = SIGMA_IDLE;
1060 newchunks = MIN(chunks_per_read,
1061 numchunks - ctx->state.chunks_downloaded);
1063 sr_info("sigma: Downloading sample data: %.0f %%",
1064 100.0 * ctx->state.chunks_downloaded / numchunks);
1066 bufsz = sigma_read_dram(ctx->state.chunks_downloaded,
1067 newchunks, buf, ctx);
1068 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1071 /* Find first ts. */
1072 if (ctx->state.chunks_downloaded == 0) {
1073 ctx->state.lastts = *(uint16_t *) buf - 1;
1074 ctx->state.lastsample = 0;
1077 /* Decode chunks and send them to sigrok. */
1078 for (i = 0; i < newchunks; ++i) {
1079 int limit_chunk = 0;
1081 /* The last chunk may potentially be only in part. */
1082 if (ctx->state.chunks_downloaded == numchunks - 1) {
1083 /* Find the last valid timestamp */
1084 limit_chunk = ctx->state.stoppos % 512 + ctx->state.lastts;
1087 if (ctx->state.chunks_downloaded + i == ctx->state.triggerchunk)
1088 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1090 &ctx->state.lastsample,
1091 ctx->state.triggerpos & 0x1ff,
1094 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1096 &ctx->state.lastsample,
1097 -1, limit_chunk, sdi);
1099 ++ctx->state.chunks_downloaded;
1106 /* Build a LUT entry used by the trigger functions. */
1107 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1111 /* For each quad probe. */
1112 for (i = 0; i < 4; ++i) {
1115 /* For each bit in LUT. */
1116 for (j = 0; j < 16; ++j)
1118 /* For each probe in quad. */
1119 for (k = 0; k < 4; ++k) {
1120 bit = 1 << (i * 4 + k);
1122 /* Set bit in entry */
1124 ((!(value & bit)) !=
1126 entry[i] &= ~(1 << j);
1131 /* Add a logical function to LUT mask. */
1132 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1133 int index, int neg, uint16_t *mask)
1136 int x[2][2], tmp, a, b, aset, bset, rset;
1138 memset(x, 0, 4 * sizeof(int));
1140 /* Trigger detect condition. */
1170 case OP_NOTRISEFALL:
1176 /* Transpose if neg is set. */
1178 for (i = 0; i < 2; ++i) {
1179 for (j = 0; j < 2; ++j) {
1181 x[i][j] = x[1-i][1-j];
1187 /* Update mask with function. */
1188 for (i = 0; i < 16; ++i) {
1189 a = (i >> (2 * index + 0)) & 1;
1190 b = (i >> (2 * index + 1)) & 1;
1192 aset = (*mask >> i) & 1;
1195 if (func == FUNC_AND || func == FUNC_NAND)
1197 else if (func == FUNC_OR || func == FUNC_NOR)
1199 else if (func == FUNC_XOR || func == FUNC_NXOR)
1202 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1213 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1214 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1215 * set at any time, but a full mask and value can be set (0/1).
1217 static int build_basic_trigger(struct triggerlut *lut, struct context *ctx)
1220 uint16_t masks[2] = { 0, 0 };
1222 memset(lut, 0, sizeof(struct triggerlut));
1224 /* Contant for simple triggers. */
1227 /* Value/mask trigger support. */
1228 build_lut_entry(ctx->trigger.simplevalue, ctx->trigger.simplemask,
1231 /* Rise/fall trigger support. */
1232 for (i = 0, j = 0; i < 16; ++i) {
1233 if (ctx->trigger.risingmask & (1 << i) ||
1234 ctx->trigger.fallingmask & (1 << i))
1235 masks[j++] = 1 << i;
1238 build_lut_entry(masks[0], masks[0], lut->m0d);
1239 build_lut_entry(masks[1], masks[1], lut->m1d);
1241 /* Add glue logic */
1242 if (masks[0] || masks[1]) {
1243 /* Transition trigger. */
1244 if (masks[0] & ctx->trigger.risingmask)
1245 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1246 if (masks[0] & ctx->trigger.fallingmask)
1247 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1248 if (masks[1] & ctx->trigger.risingmask)
1249 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1250 if (masks[1] & ctx->trigger.fallingmask)
1251 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1253 /* Only value/mask trigger. */
1257 /* Triggertype: event. */
1258 lut->params.selres = 3;
1263 static int hw_dev_acquisition_start(int dev_index, void *cb_data)
1265 struct sr_dev_inst *sdi;
1266 struct context *ctx;
1267 struct sr_datafeed_packet *packet;
1268 struct sr_datafeed_header *header;
1269 struct clockselect_50 clockselect;
1270 int frac, triggerpin, ret;
1271 uint8_t triggerselect;
1272 struct triggerinout triggerinout_conf;
1273 struct triggerlut lut;
1275 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
1280 /* If the samplerate has not been set, default to 200 kHz. */
1281 if (ctx->cur_firmware == -1) {
1282 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1286 /* Enter trigger programming mode. */
1287 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, ctx);
1289 /* 100 and 200 MHz mode. */
1290 if (ctx->cur_samplerate >= SR_MHZ(100)) {
1291 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, ctx);
1293 /* Find which pin to trigger on from mask. */
1294 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1295 if ((ctx->trigger.risingmask | ctx->trigger.fallingmask) &
1299 /* Set trigger pin and light LED on trigger. */
1300 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1302 /* Default rising edge. */
1303 if (ctx->trigger.fallingmask)
1304 triggerselect |= 1 << 3;
1306 /* All other modes. */
1307 } else if (ctx->cur_samplerate <= SR_MHZ(50)) {
1308 build_basic_trigger(&lut, ctx);
1310 sigma_write_trigger_lut(&lut, ctx);
1312 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1315 /* Setup trigger in and out pins to default values. */
1316 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1317 triggerinout_conf.trgout_bytrigger = 1;
1318 triggerinout_conf.trgout_enable = 1;
1320 sigma_write_register(WRITE_TRIGGER_OPTION,
1321 (uint8_t *) &triggerinout_conf,
1322 sizeof(struct triggerinout), ctx);
1324 /* Go back to normal mode. */
1325 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, ctx);
1327 /* Set clock select register. */
1328 if (ctx->cur_samplerate == SR_MHZ(200))
1329 /* Enable 4 probes. */
1330 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, ctx);
1331 else if (ctx->cur_samplerate == SR_MHZ(100))
1332 /* Enable 8 probes. */
1333 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, ctx);
1336 * 50 MHz mode (or fraction thereof). Any fraction down to
1337 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1339 frac = SR_MHZ(50) / ctx->cur_samplerate - 1;
1341 clockselect.async = 0;
1342 clockselect.fraction = frac;
1343 clockselect.disabled_probes = 0;
1345 sigma_write_register(WRITE_CLOCK_SELECT,
1346 (uint8_t *) &clockselect,
1347 sizeof(clockselect), ctx);
1350 /* Setup maximum post trigger time. */
1351 sigma_set_register(WRITE_POST_TRIGGER,
1352 (ctx->capture_ratio * 255) / 100, ctx);
1354 /* Start acqusition. */
1355 gettimeofday(&ctx->start_tv, 0);
1356 sigma_set_register(WRITE_MODE, 0x0d, ctx);
1358 ctx->session_dev_id = cb_data;
1360 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1361 sr_err("sigma: %s: packet malloc failed.", __func__);
1362 return SR_ERR_MALLOC;
1365 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1366 sr_err("sigma: %s: header malloc failed.", __func__);
1367 return SR_ERR_MALLOC;
1370 /* Add capture source. */
1371 sr_source_add(0, G_IO_IN, 10, receive_data, sdi);
1373 /* Send header packet to the session bus. */
1374 packet->type = SR_DF_HEADER;
1375 packet->payload = header;
1376 header->feed_version = 1;
1377 gettimeofday(&header->starttime, NULL);
1378 header->samplerate = ctx->cur_samplerate;
1379 header->num_logic_probes = ctx->num_probes;
1380 sr_session_send(ctx->session_dev_id, packet);
1384 ctx->state.state = SIGMA_CAPTURE;
1389 static int hw_dev_acquisition_stop(int dev_index, void *cb_data)
1391 struct sr_dev_inst *sdi;
1392 struct context *ctx;
1395 /* Avoid compiler warnings. */
1398 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) {
1399 sr_err("sigma: %s: sdi was NULL", __func__);
1403 if (!(ctx = sdi->priv)) {
1404 sr_err("sigma: %s: sdi->priv was NULL", __func__);
1408 /* Stop acquisition. */
1409 sigma_set_register(WRITE_MODE, 0x11, ctx);
1411 /* Set SDRAM Read Enable. */
1412 sigma_set_register(WRITE_MODE, 0x02, ctx);
1414 /* Get the current position. */
1415 sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx);
1417 /* Check if trigger has fired. */
1418 modestatus = sigma_get_register(READ_MODE, ctx);
1419 if (modestatus & 0x20)
1420 ctx->state.triggerchunk = ctx->state.triggerpos / 512;
1422 ctx->state.triggerchunk = -1;
1424 ctx->state.chunks_downloaded = 0;
1426 ctx->state.state = SIGMA_DOWNLOAD;
1431 SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1432 .name = "asix-sigma",
1433 .longname = "ASIX SIGMA",
1436 .cleanup = hw_cleanup,
1437 .dev_open = hw_dev_open,
1438 .dev_close = hw_dev_close,
1439 .dev_info_get = hw_dev_info_get,
1440 .dev_status_get = hw_dev_status_get,
1441 .hwcap_get_all = hw_hwcap_get_all,
1442 .dev_config_set = hw_dev_config_set,
1443 .dev_acquisition_start = hw_dev_acquisition_start,
1444 .dev_acquisition_stop = hw_dev_acquisition_stop,