2 * This file is part of the sigrok project.
4 * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX Sigma Logic Analyzer Driver
30 #include "asix-sigma.h"
32 #define USB_VENDOR 0xa600
33 #define USB_PRODUCT 0xa000
34 #define USB_DESCRIPTION "ASIX SIGMA"
35 #define USB_VENDOR_NAME "ASIX"
36 #define USB_MODEL_NAME "SIGMA"
37 #define USB_MODEL_VERSION ""
38 #define TRIGGER_TYPES "rf10"
40 static GSList *device_instances = NULL;
42 // XXX These should be per device
43 static struct ftdi_context ftdic;
44 static uint64_t cur_samplerate = 0;
45 static uint32_t limit_msec = 0;
46 static struct timeval start_tv;
47 static int cur_firmware = -1;
48 static int num_probes = 0;
49 static int samples_per_event = 0;
50 static int capture_ratio = 50;
51 static struct sigma_trigger trigger;
52 static struct sigma_state sigma;
54 static uint64_t supported_samplerates[] = {
68 static struct samplerates samplerates = {
72 supported_samplerates,
75 static int capabilities[] = {
85 /* Force the FPGA to reboot. */
86 static uint8_t suicide[] = {
87 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
90 /* Prepare to upload firmware (FPGA specific). */
91 static uint8_t init[] = {
92 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
95 /* Initialize the logic analyzer mode. */
96 static uint8_t logic_mode_start[] = {
97 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
98 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
101 static const char *firmware_files[] = {
102 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
103 "asix-sigma-100.fw", /* 100 MHz */
104 "asix-sigma-200.fw", /* 200 MHz */
105 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
106 "asix-sigma-phasor.fw", /* Frequency counter */
109 static void hw_stop_acquisition(int device_index, gpointer session_device_id);
111 static int sigma_read(void *buf, size_t size)
115 ret = ftdi_read_data(&ftdic, (unsigned char *)buf, size);
117 g_warning("ftdi_read_data failed: %s",
118 ftdi_get_error_string(&ftdic));
124 static int sigma_write(void *buf, size_t size)
128 ret = ftdi_write_data(&ftdic, (unsigned char *)buf, size);
130 g_warning("ftdi_write_data failed: %s",
131 ftdi_get_error_string(&ftdic));
132 } else if ((size_t) ret != size) {
133 g_warning("ftdi_write_data did not complete write\n");
139 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len)
142 uint8_t buf[len + 2];
145 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
146 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
148 for (i = 0; i < len; ++i) {
149 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
150 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
153 return sigma_write(buf, idx);
156 static int sigma_set_register(uint8_t reg, uint8_t value)
158 return sigma_write_register(reg, &value, 1);
161 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len)
165 buf[0] = REG_ADDR_LOW | (reg & 0xf);
166 buf[1] = REG_ADDR_HIGH | (reg >> 4);
167 buf[2] = REG_READ_ADDR;
169 sigma_write(buf, sizeof(buf));
171 return sigma_read(data, len);
174 static uint8_t sigma_get_register(uint8_t reg)
178 if (1 != sigma_read_register(reg, &value, 1)) {
179 g_warning("Sigma_get_register: 1 byte expected");
186 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos)
189 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
191 REG_READ_ADDR | NEXT_REG,
192 REG_READ_ADDR | NEXT_REG,
193 REG_READ_ADDR | NEXT_REG,
194 REG_READ_ADDR | NEXT_REG,
195 REG_READ_ADDR | NEXT_REG,
196 REG_READ_ADDR | NEXT_REG,
200 sigma_write(buf, sizeof(buf));
202 sigma_read(result, sizeof(result));
204 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
205 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
207 /* Not really sure why this must be done, but according to spec. */
208 if ((--*stoppos & 0x1ff) == 0x1ff)
211 if ((*--triggerpos & 0x1ff) == 0x1ff)
217 static int sigma_read_dram(uint16_t startchunk, size_t numchunks, uint8_t *data)
223 /* Send the startchunk. Index start with 1. */
224 buf[0] = startchunk >> 8;
225 buf[1] = startchunk & 0xff;
226 sigma_write_register(WRITE_MEMROW, buf, 2);
229 buf[idx++] = REG_DRAM_BLOCK;
230 buf[idx++] = REG_DRAM_WAIT_ACK;
232 for (i = 0; i < numchunks; ++i) {
233 /* Alternate bit to copy from DRAM to cache. */
234 if (i != (numchunks - 1))
235 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
237 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
239 if (i != (numchunks - 1))
240 buf[idx++] = REG_DRAM_WAIT_ACK;
243 sigma_write(buf, idx);
245 return sigma_read(data, numchunks * CHUNK_SIZE);
248 /* Upload trigger look-up tables to Sigma. */
249 static int sigma_write_trigger_lut(struct triggerlut *lut)
255 /* Transpose the table and send to Sigma. */
256 for (i = 0; i < 16; ++i) {
261 if (lut->m2d[0] & bit)
263 if (lut->m2d[1] & bit)
265 if (lut->m2d[2] & bit)
267 if (lut->m2d[3] & bit)
277 if (lut->m0d[0] & bit)
279 if (lut->m0d[1] & bit)
281 if (lut->m0d[2] & bit)
283 if (lut->m0d[3] & bit)
286 if (lut->m1d[0] & bit)
288 if (lut->m1d[1] & bit)
290 if (lut->m1d[2] & bit)
292 if (lut->m1d[3] & bit)
295 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp));
296 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i);
299 /* Send the parameters */
300 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
301 sizeof(lut->params));
306 /* Generate the bitbang stream for programming the FPGA. */
307 static int bin2bitbang(const char *filename,
308 unsigned char **buf, size_t *buf_size)
312 unsigned long offset = 0;
314 uint8_t *compressed_buf, *firmware;
315 uLongf csize, fwsize;
316 const int buffer_size = 65536;
319 uint32_t imm = 0x3f6df2ab;
321 f = fopen(filename, "r");
323 g_warning("fopen(\"%s\", \"r\")", filename);
327 if (-1 == fseek(f, 0, SEEK_END)) {
328 g_warning("fseek on %s failed", filename);
333 file_size = ftell(f);
335 fseek(f, 0, SEEK_SET);
337 compressed_buf = g_malloc(file_size);
338 firmware = g_malloc(buffer_size);
340 if (!compressed_buf || !firmware) {
341 g_warning("Error allocating buffers");
346 while ((c = getc(f)) != EOF) {
347 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
348 compressed_buf[csize++] = c ^ imm;
352 fwsize = buffer_size;
353 ret = uncompress(firmware, &fwsize, compressed_buf, csize);
355 g_free(compressed_buf);
357 g_warning("Could not unpack Sigma firmware. (Error %d)\n", ret);
361 g_free(compressed_buf);
363 *buf_size = fwsize * 2 * 8;
365 *buf = p = (unsigned char *)g_malloc(*buf_size);
368 g_warning("Error allocating buffers");
372 for (i = 0; i < fwsize; ++i) {
373 for (bit = 7; bit >= 0; --bit) {
374 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
375 p[offset++] = v | 0x01;
382 if (offset != *buf_size) {
384 g_warning("Error reading firmware %s "
385 "offset=%ld, file_size=%ld, buf_size=%zd\n",
386 filename, offset, file_size, *buf_size);
394 static int hw_init(char *deviceinfo)
396 struct sigrok_device_instance *sdi;
398 deviceinfo = deviceinfo;
402 /* Look for SIGMAs. */
403 if (ftdi_usb_open_desc(&ftdic, USB_VENDOR, USB_PRODUCT,
404 USB_DESCRIPTION, NULL) < 0)
407 /* Register SIGMA device. */
408 sdi = sigrok_device_instance_new(0, ST_INITIALIZING,
409 USB_VENDOR_NAME, USB_MODEL_NAME, USB_MODEL_VERSION);
413 device_instances = g_slist_append(device_instances, sdi);
415 /* We will open the device again when we need it. */
416 ftdi_usb_close(&ftdic);
421 static int upload_firmware(int firmware_idx)
427 unsigned char result[32];
428 char firmware_path[128];
430 /* Make sure it's an ASIX SIGMA. */
431 if ((ret = ftdi_usb_open_desc(&ftdic,
432 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
433 g_warning("ftdi_usb_open failed: %s",
434 ftdi_get_error_string(&ftdic));
438 if ((ret = ftdi_set_bitmode(&ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
439 g_warning("ftdi_set_bitmode failed: %s",
440 ftdi_get_error_string(&ftdic));
444 /* Four times the speed of sigmalogan - Works well. */
445 if ((ret = ftdi_set_baudrate(&ftdic, 750000)) < 0) {
446 g_warning("ftdi_set_baudrate failed: %s",
447 ftdi_get_error_string(&ftdic));
451 /* Force the FPGA to reboot. */
452 sigma_write(suicide, sizeof(suicide));
453 sigma_write(suicide, sizeof(suicide));
454 sigma_write(suicide, sizeof(suicide));
455 sigma_write(suicide, sizeof(suicide));
457 /* Prepare to upload firmware (FPGA specific). */
458 sigma_write(init, sizeof(init));
460 ftdi_usb_purge_buffers(&ftdic);
462 /* Wait until the FPGA asserts INIT_B. */
464 ret = sigma_read(result, 1);
465 if (result[0] & 0x20)
469 /* Prepare firmware. */
470 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
471 firmware_files[firmware_idx]);
473 if (-1 == bin2bitbang(firmware_path, &buf, &buf_size)) {
474 g_warning("An error occured while reading the firmware: %s",
479 /* Upload firmare. */
480 sigma_write(buf, buf_size);
484 if ((ret = ftdi_set_bitmode(&ftdic, 0x00, BITMODE_RESET)) < 0) {
485 g_warning("ftdi_set_bitmode failed: %s",
486 ftdi_get_error_string(&ftdic));
490 ftdi_usb_purge_buffers(&ftdic);
492 /* Discard garbage. */
493 while (1 == sigma_read(&pins, 1))
496 /* Initialize the logic analyzer mode. */
497 sigma_write(logic_mode_start, sizeof(logic_mode_start));
499 /* Expect a 3 byte reply. */
500 ret = sigma_read(result, 3);
502 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
503 g_warning("Configuration failed. Invalid reply received.");
507 cur_firmware = firmware_idx;
512 static int hw_opendev(int device_index)
514 struct sigrok_device_instance *sdi;
517 /* Make sure it's an ASIX SIGMA. */
518 if ((ret = ftdi_usb_open_desc(&ftdic,
519 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
521 g_warning("ftdi_usb_open failed: %s",
522 ftdi_get_error_string(&ftdic));
527 if (!(sdi = get_sigrok_device_instance(device_instances, device_index)))
530 sdi->status = ST_ACTIVE;
535 static int set_samplerate(struct sigrok_device_instance *sdi,
542 for (i = 0; supported_samplerates[i]; i++) {
543 if (supported_samplerates[i] == samplerate)
546 if (supported_samplerates[i] == 0)
547 return SIGROK_ERR_SAMPLERATE;
549 if (samplerate <= MHZ(50)) {
550 ret = upload_firmware(0);
553 if (samplerate == MHZ(100)) {
554 ret = upload_firmware(1);
557 else if (samplerate == MHZ(200)) {
558 ret = upload_firmware(2);
562 cur_samplerate = samplerate;
563 samples_per_event = 16 / num_probes;
564 sigma.state = SIGMA_IDLE;
566 g_message("Firmware uploaded");
572 * In 100 and 200 MHz mode, only a single pin rising/falling can be
573 * set as trigger. In other modes, two rising/falling triggers can be set,
574 * in addition to value/mask trigger for any number of probes.
576 * The Sigma supports complex triggers using boolean expressions, but this
577 * has not been implemented yet.
579 static int configure_probes(GSList *probes)
586 memset(&trigger, 0, sizeof(struct sigma_trigger));
588 for (l = probes; l; l = l->next) {
589 probe = (struct probe *)l->data;
590 probebit = 1 << (probe->index - 1);
592 if (!probe->enabled || !probe->trigger)
595 if (cur_samplerate >= MHZ(100)) {
596 /* Fast trigger support. */
598 g_warning("Asix Sigma only supports a single "
599 "pin trigger in 100 and 200 "
603 if (probe->trigger[0] == 'f')
604 trigger.fallingmask |= probebit;
605 else if (probe->trigger[0] == 'r')
606 trigger.risingmask |= probebit;
608 g_warning("Asix Sigma only supports "
609 "rising/falling trigger in 100 "
610 "and 200 MHz mode.");
616 /* Simple trigger support (event). */
617 if (probe->trigger[0] == '1') {
618 trigger.simplevalue |= probebit;
619 trigger.simplemask |= probebit;
621 else if (probe->trigger[0] == '0') {
622 trigger.simplevalue &= ~probebit;
623 trigger.simplemask |= probebit;
625 else if (probe->trigger[0] == 'f') {
626 trigger.fallingmask |= probebit;
629 else if (probe->trigger[0] == 'r') {
630 trigger.risingmask |= probebit;
634 if (trigger_set > 2) {
635 g_warning("Asix Sigma only supports 2 rising/"
636 "falling triggers.");
645 static void hw_closedev(int device_index)
647 struct sigrok_device_instance *sdi;
649 if ((sdi = get_sigrok_device_instance(device_instances, device_index)))
651 if (sdi->status == ST_ACTIVE)
652 ftdi_usb_close(&ftdic);
654 sdi->status = ST_INACTIVE;
658 static void hw_cleanup(void)
662 static void *hw_get_device_info(int device_index, int device_info_id)
664 struct sigrok_device_instance *sdi;
667 if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) {
668 fprintf(stderr, "It's NULL.\n");
672 switch (device_info_id) {
677 info = GINT_TO_POINTER(16);
682 case DI_TRIGGER_TYPES:
683 info = (char *)TRIGGER_TYPES;
685 case DI_CUR_SAMPLERATE:
686 info = &cur_samplerate;
693 static int hw_get_status(int device_index)
695 struct sigrok_device_instance *sdi;
697 sdi = get_sigrok_device_instance(device_instances, device_index);
704 static int *hw_get_capabilities(void)
709 static int hw_set_configuration(int device_index, int capability, void *value)
711 struct sigrok_device_instance *sdi;
714 if (!(sdi = get_sigrok_device_instance(device_instances, device_index)))
717 if (capability == HWCAP_SAMPLERATE) {
718 ret = set_samplerate(sdi, *(uint64_t*) value);
719 } else if (capability == HWCAP_PROBECONFIG) {
720 ret = configure_probes(value);
721 } else if (capability == HWCAP_LIMIT_MSEC) {
722 limit_msec = strtoull(value, NULL, 10);
724 } else if (capability == HWCAP_CAPTURE_RATIO) {
725 capture_ratio = strtoull(value, NULL, 10);
727 } else if (capability == HWCAP_PROBECONFIG) {
728 ret = configure_probes((GSList *) value);
736 /* Software trigger to determine exact trigger position. */
737 static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
738 struct sigma_trigger *t)
742 for (i = 0; i < 8; ++i) {
744 last_sample = samples[i-1];
746 /* Simple triggers. */
747 if ((samples[i] & t->simplemask) != t->simplevalue)
751 if ((last_sample & t->risingmask) != 0 || (samples[i] &
752 t->risingmask) != t->risingmask)
756 if ((last_sample & t->fallingmask) != t->fallingmask ||
757 (samples[i] & t->fallingmask) != 0)
763 /* If we did not match, return original trigger pos. */
768 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
769 * Each event is 20ns apart, and can contain multiple samples.
771 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
772 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
773 * For 50 MHz and below, events contain one sample for each channel,
774 * spread 20 ns apart.
776 static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
777 uint16_t *lastsample, int triggerpos, void *user_data)
780 uint16_t samples[65536 * samples_per_event];
781 struct datafeed_packet packet;
782 int i, j, k, l, numpad, tosend;
783 size_t n = 0, sent = 0;
784 int clustersize = EVENTS_PER_CLUSTER * samples_per_event;
789 /* Check if trigger is in this chunk. */
790 if (triggerpos != -1) {
791 if (cur_samplerate <= MHZ(50))
792 triggerpos -= EVENTS_PER_CLUSTER - 1;
797 /* Find in which cluster the trigger occured. */
798 triggerts = triggerpos / 7;
802 for (i = 0; i < 64; ++i) {
803 ts = *(uint16_t *) &buf[i * 16];
804 tsdiff = ts - *lastts;
807 /* Pad last sample up to current point. */
808 numpad = tsdiff * samples_per_event - clustersize;
810 for (j = 0; j < numpad; ++j)
811 samples[j] = *lastsample;
816 /* Send samples between previous and this timestamp to sigrok. */
819 tosend = MIN(2048, n - sent);
821 packet.type = DF_LOGIC;
822 packet.length = tosend * sizeof(uint16_t);
824 packet.payload = samples + sent;
825 session_bus(user_data, &packet);
831 event = (uint16_t *) &buf[i * 16 + 2];
834 /* For each event in cluster. */
835 for (j = 0; j < 7; ++j) {
837 /* For each sample in event. */
838 for (k = 0; k < samples_per_event; ++k) {
841 /* For each probe. */
842 for (l = 0; l < num_probes; ++l)
843 cur_sample |= (!!(event[j] & (1 << (l *
844 samples_per_event + k))))
847 samples[n++] = cur_sample;
851 /* Send data up to trigger point (if triggered). */
853 if (i == triggerts) {
855 * Trigger is not always accurate to sample because of
856 * pipeline delay. However, it always triggers before
857 * the actual event. We therefore look at the next
858 * samples to pinpoint the exact position of the trigger.
860 tosend = get_trigger_offset(samples, *lastsample,
864 packet.type = DF_LOGIC;
865 packet.length = tosend * sizeof(uint16_t);
867 packet.payload = samples;
868 session_bus(user_data, &packet);
873 packet.type = DF_TRIGGER;
876 session_bus(user_data, &packet);
879 /* Send rest of the chunk to sigrok. */
882 packet.type = DF_LOGIC;
883 packet.length = tosend * sizeof(uint16_t);
885 packet.payload = samples + sent;
886 session_bus(user_data, &packet);
888 *lastsample = samples[n - 1];
894 static int receive_data(int fd, int revents, void *user_data)
896 struct datafeed_packet packet;
897 const int chunks_per_read = 32;
898 unsigned char buf[chunks_per_read * CHUNK_SIZE];
899 int bufsz, numchunks, i, newchunks;
900 uint32_t running_msec;
906 numchunks = sigma.stoppos / 512;
908 if (sigma.state == SIGMA_IDLE)
911 if (sigma.state == SIGMA_CAPTURE) {
913 /* Check if the timer has expired, or memory is full. */
914 gettimeofday(&tv, 0);
915 running_msec = (tv.tv_sec - start_tv.tv_sec) * 1000 +
916 (tv.tv_usec - start_tv.tv_usec) / 1000;
918 if (running_msec < limit_msec && numchunks < 32767)
921 hw_stop_acquisition(-1, user_data);
925 } else if (sigma.state == SIGMA_DOWNLOAD) {
926 if (sigma.chunks_downloaded >= numchunks) {
927 /* End of samples. */
928 packet.type = DF_END;
930 session_bus(user_data, &packet);
932 sigma.state = SIGMA_IDLE;
937 newchunks = MIN(chunks_per_read,
938 numchunks - sigma.chunks_downloaded);
940 g_message("Downloading sample data: %.0f %%",
941 100.0 * sigma.chunks_downloaded / numchunks);
943 bufsz = sigma_read_dram(sigma.chunks_downloaded,
947 if (sigma.chunks_downloaded == 0) {
948 sigma.lastts = *(uint16_t *) buf - 1;
949 sigma.lastsample = 0;
952 /* Decode chunks and send them to sigrok. */
953 for (i = 0; i < newchunks; ++i) {
954 if (sigma.chunks_downloaded + i == sigma.triggerchunk)
955 decode_chunk_ts(buf + (i * CHUNK_SIZE),
956 &sigma.lastts, &sigma.lastsample,
957 sigma.triggerpos & 0x1ff,
960 decode_chunk_ts(buf + (i * CHUNK_SIZE),
961 &sigma.lastts, &sigma.lastsample,
965 sigma.chunks_downloaded += newchunks;
971 /* Build a LUT entry used by the trigger functions. */
972 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
976 /* For each quad probe. */
977 for (i = 0; i < 4; ++i) {
980 /* For each bit in LUT. */
981 for (j = 0; j < 16; ++j)
983 /* For each probe in quad. */
984 for (k = 0; k < 4; ++k) {
985 bit = 1 << (i * 4 + k);
987 /* Set bit in entry */
991 entry[i] &= ~(1 << j);
996 /* Add a logical function to LUT mask. */
997 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
998 int index, int neg, uint16_t *mask)
1001 int x[2][2], tmp, a, b, aset, bset, rset;
1003 memset(x, 0, 4 * sizeof(int));
1005 /* Trigger detect condition. */
1035 case OP_NOTRISEFALL:
1041 /* Transpose if neg is set. */
1043 for (i = 0; i < 2; ++i)
1044 for (j = 0; j < 2; ++j) {
1046 x[i][j] = x[1-i][1-j];
1051 /* Update mask with function. */
1052 for (i = 0; i < 16; ++i) {
1053 a = (i >> (2 * index + 0)) & 1;
1054 b = (i >> (2 * index + 1)) & 1;
1056 aset = (*mask >> i) & 1;
1059 if (func == FUNC_AND || func == FUNC_NAND)
1061 else if (func == FUNC_OR || func == FUNC_NOR)
1063 else if (func == FUNC_XOR || func == FUNC_NXOR)
1066 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1077 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1078 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1079 * set at any time, but a full mask and value can be set (0/1).
1081 static int build_basic_trigger(struct triggerlut *lut)
1084 uint16_t masks[2] = { 0, 0 };
1086 memset(lut, 0, sizeof(struct triggerlut));
1088 /* Contant for simple triggers. */
1091 /* Value/mask trigger support. */
1092 build_lut_entry(trigger.simplevalue, trigger.simplemask, lut->m2d);
1094 /* Rise/fall trigger support. */
1095 for (i = 0, j = 0; i < 16; ++i) {
1096 if (trigger.risingmask & (1 << i) ||
1097 trigger.fallingmask & (1 << i))
1098 masks[j++] = 1 << i;
1101 build_lut_entry(masks[0], masks[0], lut->m0d);
1102 build_lut_entry(masks[1], masks[1], lut->m1d);
1104 /* Add glue logic */
1105 if (masks[0] || masks[1]) {
1106 /* Transition trigger. */
1107 if (masks[0] & trigger.risingmask)
1108 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1109 if (masks[0] & trigger.fallingmask)
1110 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1111 if (masks[1] & trigger.risingmask)
1112 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1113 if (masks[1] & trigger.fallingmask)
1114 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1116 /* Only value/mask trigger. */
1120 /* Triggertype: event. */
1121 lut->params.selres = 3;
1126 static int hw_start_acquisition(int device_index, gpointer session_device_id)
1128 struct sigrok_device_instance *sdi;
1129 struct datafeed_packet packet;
1130 struct datafeed_header header;
1131 struct clockselect_50 clockselect;
1133 uint8_t triggerselect;
1134 struct triggerinout triggerinout_conf;
1135 struct triggerlut lut;
1138 session_device_id = session_device_id;
1140 if (!(sdi = get_sigrok_device_instance(device_instances, device_index)))
1143 device_index = device_index;
1145 /* If the samplerate has not been set, default to 50 MHz. */
1146 if (cur_firmware == -1)
1147 set_samplerate(sdi, MHZ(50));
1149 /* Enter trigger programming mode. */
1150 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20);
1152 /* 100 and 200 MHz mode. */
1153 if (cur_samplerate >= MHZ(100)) {
1154 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81);
1156 /* Find which pin to trigger on from mask. */
1157 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1158 if ((trigger.risingmask | trigger.fallingmask) &
1162 /* Set trigger pin and light LED on trigger. */
1163 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1165 /* Default rising edge. */
1166 if (trigger.fallingmask)
1167 triggerselect |= 1 << 3;
1169 /* All other modes. */
1170 } else if (cur_samplerate <= MHZ(50)) {
1171 build_basic_trigger(&lut);
1173 sigma_write_trigger_lut(&lut);
1175 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1178 /* Setup trigger in and out pins to default values. */
1179 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1180 triggerinout_conf.trgout_bytrigger = 1;
1181 triggerinout_conf.trgout_enable = 1;
1183 sigma_write_register(WRITE_TRIGGER_OPTION,
1184 (uint8_t *) &triggerinout_conf,
1185 sizeof(struct triggerinout));
1187 /* Go back to normal mode. */
1188 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect);
1190 /* Set clock select register. */
1191 if (cur_samplerate == MHZ(200))
1192 /* Enable 4 probes. */
1193 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0);
1194 else if (cur_samplerate == MHZ(100))
1195 /* Enable 8 probes. */
1196 sigma_set_register(WRITE_CLOCK_SELECT, 0x00);
1199 * 50 MHz mode (or fraction thereof). Any fraction down to
1200 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1202 frac = MHZ(50) / cur_samplerate - 1;
1204 clockselect.async = 0;
1205 clockselect.fraction = frac;
1206 clockselect.disabled_probes = 0;
1208 sigma_write_register(WRITE_CLOCK_SELECT,
1209 (uint8_t *) &clockselect,
1210 sizeof(clockselect));
1213 /* Setup maximum post trigger time. */
1214 sigma_set_register(WRITE_POST_TRIGGER, (capture_ratio * 255) / 100);
1216 /* Start acqusition. */
1217 gettimeofday(&start_tv, 0);
1218 sigma_set_register(WRITE_MODE, 0x0d);
1220 /* Send header packet to the session bus. */
1221 packet.type = DF_HEADER;
1222 packet.length = sizeof(struct datafeed_header);
1223 packet.payload = &header;
1224 header.feed_version = 1;
1225 gettimeofday(&header.starttime, NULL);
1226 header.samplerate = cur_samplerate;
1227 header.protocol_id = PROTO_RAW;
1228 header.num_logic_probes = num_probes;
1229 header.num_analog_probes = 0;
1230 session_bus(session_device_id, &packet);
1232 /* Add capture source. */
1233 source_add(0, G_IO_IN, 10, receive_data, session_device_id);
1235 sigma.state = SIGMA_CAPTURE;
1240 static void hw_stop_acquisition(int device_index, gpointer session_device_id)
1244 device_index = device_index;
1245 session_device_id = session_device_id;
1247 /* Stop acquisition. */
1248 sigma_set_register(WRITE_MODE, 0x11);
1250 /* Set SDRAM Read Enable. */
1251 sigma_set_register(WRITE_MODE, 0x02);
1253 /* Get the current position. */
1254 sigma_read_pos(&sigma.stoppos, &sigma.triggerpos);
1256 /* Check if trigger has fired. */
1257 modestatus = sigma_get_register(READ_MODE);
1258 if (modestatus & 0x20) {
1259 sigma.triggerchunk = sigma.triggerpos / 512;
1262 sigma.triggerchunk = -1;
1264 sigma.chunks_downloaded = 0;
1266 sigma.state = SIGMA_DOWNLOAD;
1269 struct device_plugin asix_sigma_plugin_info = {
1278 hw_get_capabilities,
1279 hw_set_configuration,
1280 hw_start_acquisition,
1281 hw_stop_acquisition,