2 * This file is part of the libsigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
27 #include <glib/gstdio.h>
30 #include "libsigrok.h"
31 #include "libsigrok-internal.h"
32 #include "asix-sigma.h"
34 #define USB_VENDOR 0xa600
35 #define USB_PRODUCT 0xa000
36 #define USB_DESCRIPTION "ASIX SIGMA"
37 #define USB_VENDOR_NAME "ASIX"
38 #define USB_MODEL_NAME "SIGMA"
39 #define TRIGGER_TYPE "rf10"
41 SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
42 static struct sr_dev_driver *di = &asix_sigma_driver_info;
43 static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
46 * The ASIX Sigma supports arbitrary integer frequency divider in
47 * the 50MHz mode. The divider is in range 1...256 , allowing for
48 * very precise sampling rate selection. This driver supports only
49 * a subset of the sampling rates.
51 static const uint64_t samplerates[] = {
52 SR_KHZ(200), /* div=250 */
53 SR_KHZ(250), /* div=200 */
54 SR_KHZ(500), /* div=100 */
55 SR_MHZ(1), /* div=50 */
56 SR_MHZ(5), /* div=10 */
57 SR_MHZ(10), /* div=5 */
58 SR_MHZ(25), /* div=2 */
59 SR_MHZ(50), /* div=1 */
60 SR_MHZ(100), /* Special FW needed */
61 SR_MHZ(200), /* Special FW needed */
65 * Channel numbers seem to go from 1-16, according to this image:
66 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
67 * (the cable has two additional GND pins, and a TI and TO pin)
69 static const char *channel_names[] = {
70 "1", "2", "3", "4", "5", "6", "7", "8",
71 "9", "10", "11", "12", "13", "14", "15", "16",
74 static const int32_t hwcaps[] = {
75 SR_CONF_LOGIC_ANALYZER,
78 SR_CONF_CAPTURE_RATIO,
80 SR_CONF_LIMIT_SAMPLES,
83 /* Initialize the logic analyzer mode. */
84 static uint8_t logic_mode_start[] = {
85 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
86 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
89 static const char *sigma_firmware_files[] = {
90 /* 50 MHz, supports 8 bit fractions */
91 FIRMWARE_DIR "/asix-sigma-50.fw",
93 FIRMWARE_DIR "/asix-sigma-100.fw",
95 FIRMWARE_DIR "/asix-sigma-200.fw",
96 /* Synchronous clock from pin */
97 FIRMWARE_DIR "/asix-sigma-50sync.fw",
98 /* Frequency counter */
99 FIRMWARE_DIR "/asix-sigma-phasor.fw",
102 static int sigma_read(void *buf, size_t size, struct dev_context *devc)
106 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
108 sr_err("ftdi_read_data failed: %s",
109 ftdi_get_error_string(&devc->ftdic));
115 static int sigma_write(void *buf, size_t size, struct dev_context *devc)
119 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
121 sr_err("ftdi_write_data failed: %s",
122 ftdi_get_error_string(&devc->ftdic));
123 } else if ((size_t) ret != size) {
124 sr_err("ftdi_write_data did not complete write.");
130 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
131 struct dev_context *devc)
134 uint8_t buf[len + 2];
137 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
138 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
140 for (i = 0; i < len; ++i) {
141 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
142 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
145 return sigma_write(buf, idx, devc);
148 static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
150 return sigma_write_register(reg, &value, 1, devc);
153 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
154 struct dev_context *devc)
158 buf[0] = REG_ADDR_LOW | (reg & 0xf);
159 buf[1] = REG_ADDR_HIGH | (reg >> 4);
160 buf[2] = REG_READ_ADDR;
162 sigma_write(buf, sizeof(buf), devc);
164 return sigma_read(data, len, devc);
167 static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
171 if (1 != sigma_read_register(reg, &value, 1, devc)) {
172 sr_err("sigma_get_register: 1 byte expected");
179 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
180 struct dev_context *devc)
183 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
185 REG_READ_ADDR | NEXT_REG,
186 REG_READ_ADDR | NEXT_REG,
187 REG_READ_ADDR | NEXT_REG,
188 REG_READ_ADDR | NEXT_REG,
189 REG_READ_ADDR | NEXT_REG,
190 REG_READ_ADDR | NEXT_REG,
194 sigma_write(buf, sizeof(buf), devc);
196 sigma_read(result, sizeof(result), devc);
198 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
199 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
201 /* Not really sure why this must be done, but according to spec. */
202 if ((--*stoppos & 0x1ff) == 0x1ff)
205 if ((*--triggerpos & 0x1ff) == 0x1ff)
211 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
212 uint8_t *data, struct dev_context *devc)
218 /* Send the startchunk. Index start with 1. */
219 buf[0] = startchunk >> 8;
220 buf[1] = startchunk & 0xff;
221 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
224 buf[idx++] = REG_DRAM_BLOCK;
225 buf[idx++] = REG_DRAM_WAIT_ACK;
227 for (i = 0; i < numchunks; ++i) {
228 /* Alternate bit to copy from DRAM to cache. */
229 if (i != (numchunks - 1))
230 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
232 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
234 if (i != (numchunks - 1))
235 buf[idx++] = REG_DRAM_WAIT_ACK;
238 sigma_write(buf, idx, devc);
240 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
243 /* Upload trigger look-up tables to Sigma. */
244 static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
250 /* Transpose the table and send to Sigma. */
251 for (i = 0; i < 16; ++i) {
256 if (lut->m2d[0] & bit)
258 if (lut->m2d[1] & bit)
260 if (lut->m2d[2] & bit)
262 if (lut->m2d[3] & bit)
272 if (lut->m0d[0] & bit)
274 if (lut->m0d[1] & bit)
276 if (lut->m0d[2] & bit)
278 if (lut->m0d[3] & bit)
281 if (lut->m1d[0] & bit)
283 if (lut->m1d[1] & bit)
285 if (lut->m1d[2] & bit)
287 if (lut->m1d[3] & bit)
290 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
292 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
295 /* Send the parameters */
296 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
297 sizeof(lut->params), devc);
302 /* Generate the bitbang stream for programming the FPGA. */
303 static int bin2bitbang(const char *filename,
304 unsigned char **buf, size_t *buf_size)
307 unsigned long file_size;
308 unsigned long offset = 0;
311 unsigned long fwsize = 0;
312 const int buffer_size = 65536;
315 uint32_t imm = 0x3f6df2ab;
317 f = g_fopen(filename, "rb");
319 sr_err("g_fopen(\"%s\", \"rb\")", filename);
323 if (-1 == fseek(f, 0, SEEK_END)) {
324 sr_err("fseek on %s failed", filename);
329 file_size = ftell(f);
331 fseek(f, 0, SEEK_SET);
333 if (!(firmware = g_try_malloc(buffer_size))) {
334 sr_err("%s: firmware malloc failed", __func__);
336 return SR_ERR_MALLOC;
339 while ((c = getc(f)) != EOF) {
340 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
341 firmware[fwsize++] = c ^ imm;
345 if(fwsize != file_size) {
346 sr_err("%s: Error reading firmware", filename);
352 *buf_size = fwsize * 2 * 8;
354 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
356 sr_err("%s: buf/p malloc failed", __func__);
358 return SR_ERR_MALLOC;
361 for (i = 0; i < fwsize; ++i) {
362 for (bit = 7; bit >= 0; --bit) {
363 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
364 p[offset++] = v | 0x01;
371 if (offset != *buf_size) {
373 sr_err("Error reading firmware %s "
374 "offset=%ld, file_size=%ld, buf_size=%zd.",
375 filename, offset, file_size, *buf_size);
383 static void clear_helper(void *priv)
385 struct dev_context *devc;
389 ftdi_deinit(&devc->ftdic);
392 static int dev_clear(void)
394 return std_dev_clear(di, clear_helper);
397 static int init(struct sr_context *sr_ctx)
399 return std_init(sr_ctx, di, LOG_PREFIX);
402 static GSList *scan(GSList *options)
404 struct sr_dev_inst *sdi;
405 struct sr_channel *ch;
406 struct drv_context *drvc;
407 struct dev_context *devc;
409 struct ftdi_device_list *devlist;
421 if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
422 sr_err("%s: devc malloc failed", __func__);
426 ftdi_init(&devc->ftdic);
428 /* Look for SIGMAs. */
430 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
431 USB_VENDOR, USB_PRODUCT)) <= 0) {
433 sr_err("ftdi_usb_find_all(): %d", ret);
437 /* Make sure it's a version 1 or 2 SIGMA. */
438 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
439 serial_txt, sizeof(serial_txt));
440 sscanf(serial_txt, "%x", &serial);
442 if (serial < 0xa6010000 || serial > 0xa602ffff) {
443 sr_err("Only SIGMA and SIGMA2 are supported "
444 "in this version of libsigrok.");
448 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
450 devc->cur_samplerate = 0;
452 devc->limit_msec = 0;
453 devc->cur_firmware = -1;
454 devc->num_channels = 0;
455 devc->samples_per_event = 0;
456 devc->capture_ratio = 50;
457 devc->use_triggers = 0;
459 /* Register SIGMA device. */
460 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
461 USB_MODEL_NAME, NULL))) {
462 sr_err("%s: sdi was NULL", __func__);
467 for (i = 0; i < ARRAY_SIZE(channel_names); i++) {
468 ch = sr_channel_new(i, SR_CHANNEL_LOGIC, TRUE,
472 sdi->channels = g_slist_append(sdi->channels, ch);
475 devices = g_slist_append(devices, sdi);
476 drvc->instances = g_slist_append(drvc->instances, sdi);
479 /* We will open the device again when we need it. */
480 ftdi_list_free(&devlist);
485 ftdi_deinit(&devc->ftdic);
490 static GSList *dev_list(void)
492 return ((struct drv_context *)(di->priv))->instances;
496 * Configure the FPGA for bitbang mode.
497 * This sequence is documented in section 2. of the ASIX Sigma programming
498 * manual. This sequence is necessary to configure the FPGA in the Sigma
499 * into Bitbang mode, in which it can be programmed with the firmware.
501 static int sigma_fpga_init_bitbang(struct dev_context *devc)
503 uint8_t suicide[] = {
504 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
506 uint8_t init_array[] = {
507 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
510 int i, ret, timeout = 10000;
513 /* Section 2. part 1), do the FPGA suicide. */
514 sigma_write(suicide, sizeof(suicide), devc);
515 sigma_write(suicide, sizeof(suicide), devc);
516 sigma_write(suicide, sizeof(suicide), devc);
517 sigma_write(suicide, sizeof(suicide), devc);
519 /* Section 2. part 2), do pulse on D1. */
520 sigma_write(init_array, sizeof(init_array), devc);
521 ftdi_usb_purge_buffers(&devc->ftdic);
523 /* Wait until the FPGA asserts D6/INIT_B. */
524 for (i = 0; i < timeout; i++) {
525 ret = sigma_read(&data, 1, devc);
528 /* Test if pin D6 got asserted. */
531 /* The D6 was not asserted yet, wait a bit. */
535 return SR_ERR_TIMEOUT;
538 static int upload_firmware(int firmware_idx, struct dev_context *devc)
544 unsigned char result[32];
545 const char *firmware = sigma_firmware_files[firmware_idx];
546 struct ftdi_context *ftdic = &devc->ftdic;
548 /* Make sure it's an ASIX SIGMA. */
549 ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT,
550 USB_DESCRIPTION, NULL);
552 sr_err("ftdi_usb_open failed: %s",
553 ftdi_get_error_string(ftdic));
557 ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG);
559 sr_err("ftdi_set_bitmode failed: %s",
560 ftdi_get_error_string(ftdic));
564 /* Four times the speed of sigmalogan - Works well. */
565 ret = ftdi_set_baudrate(ftdic, 750000);
567 sr_err("ftdi_set_baudrate failed: %s",
568 ftdi_get_error_string(ftdic));
572 /* Initialize the FPGA for firmware upload. */
573 ret = sigma_fpga_init_bitbang(devc);
577 /* Prepare firmware. */
578 ret = bin2bitbang(firmware, &buf, &buf_size);
580 sr_err("An error occured while reading the firmware: %s",
585 /* Upload firmare. */
586 sr_info("Uploading firmware file '%s'.", firmware);
587 sigma_write(buf, buf_size, devc);
591 ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET);
593 sr_err("ftdi_set_bitmode failed: %s",
594 ftdi_get_error_string(ftdic));
598 ftdi_usb_purge_buffers(ftdic);
600 /* Discard garbage. */
601 while (1 == sigma_read(&pins, 1, devc))
604 /* Initialize the logic analyzer mode. */
605 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
607 /* Expect a 3 byte reply. */
608 ret = sigma_read(result, 3, devc);
610 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
611 sr_err("Configuration failed. Invalid reply received.");
615 devc->cur_firmware = firmware_idx;
617 sr_info("Firmware uploaded.");
622 static int dev_open(struct sr_dev_inst *sdi)
624 struct dev_context *devc;
629 /* Make sure it's an ASIX SIGMA. */
630 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
631 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
633 sr_err("ftdi_usb_open failed: %s",
634 ftdi_get_error_string(&devc->ftdic));
639 sdi->status = SR_ST_ACTIVE;
644 static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
646 struct dev_context *devc;
653 for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
654 if (samplerates[i] == samplerate)
657 if (samplerates[i] == 0)
658 return SR_ERR_SAMPLERATE;
660 if (samplerate <= SR_MHZ(50)) {
661 ret = upload_firmware(0, devc);
662 devc->num_channels = 16;
664 if (samplerate == SR_MHZ(100)) {
665 ret = upload_firmware(1, devc);
666 devc->num_channels = 8;
668 else if (samplerate == SR_MHZ(200)) {
669 ret = upload_firmware(2, devc);
670 devc->num_channels = 4;
673 devc->cur_samplerate = samplerate;
674 devc->period_ps = 1000000000000ULL / samplerate;
675 devc->samples_per_event = 16 / devc->num_channels;
676 devc->state.state = SIGMA_IDLE;
682 * In 100 and 200 MHz mode, only a single pin rising/falling can be
683 * set as trigger. In other modes, two rising/falling triggers can be set,
684 * in addition to value/mask trigger for any number of channels.
686 * The Sigma supports complex triggers using boolean expressions, but this
687 * has not been implemented yet.
689 static int configure_channels(const struct sr_dev_inst *sdi)
691 struct dev_context *devc = sdi->priv;
692 const struct sr_channel *ch;
697 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
699 for (l = sdi->channels; l; l = l->next) {
700 ch = (struct sr_channel *)l->data;
701 channelbit = 1 << (ch->index);
703 if (!ch->enabled || !ch->trigger)
706 if (devc->cur_samplerate >= SR_MHZ(100)) {
707 /* Fast trigger support. */
709 sr_err("Only a single pin trigger in 100 and "
710 "200MHz mode is supported.");
713 if (ch->trigger[0] == 'f')
714 devc->trigger.fallingmask |= channelbit;
715 else if (ch->trigger[0] == 'r')
716 devc->trigger.risingmask |= channelbit;
718 sr_err("Only rising/falling trigger in 100 "
719 "and 200MHz mode is supported.");
725 /* Simple trigger support (event). */
726 if (ch->trigger[0] == '1') {
727 devc->trigger.simplevalue |= channelbit;
728 devc->trigger.simplemask |= channelbit;
730 else if (ch->trigger[0] == '0') {
731 devc->trigger.simplevalue &= ~channelbit;
732 devc->trigger.simplemask |= channelbit;
734 else if (ch->trigger[0] == 'f') {
735 devc->trigger.fallingmask |= channelbit;
738 else if (ch->trigger[0] == 'r') {
739 devc->trigger.risingmask |= channelbit;
744 * Actually, Sigma supports 2 rising/falling triggers,
745 * but they are ORed and the current trigger syntax
746 * does not permit ORed triggers.
748 if (trigger_set > 1) {
749 sr_err("Only 1 rising/falling trigger "
756 devc->use_triggers = 1;
762 static int dev_close(struct sr_dev_inst *sdi)
764 struct dev_context *devc;
769 if (sdi->status == SR_ST_ACTIVE)
770 ftdi_usb_close(&devc->ftdic);
772 sdi->status = SR_ST_INACTIVE;
777 static int cleanup(void)
782 static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi,
783 const struct sr_channel_group *cg)
785 struct dev_context *devc;
790 case SR_CONF_SAMPLERATE:
793 *data = g_variant_new_uint64(devc->cur_samplerate);
804 static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi,
805 const struct sr_channel_group *cg)
807 struct dev_context *devc;
808 uint64_t num_samples;
813 if (sdi->status != SR_ST_ACTIVE)
814 return SR_ERR_DEV_CLOSED;
819 case SR_CONF_SAMPLERATE:
820 ret = set_samplerate(sdi, g_variant_get_uint64(data));
822 case SR_CONF_LIMIT_MSEC:
823 devc->limit_msec = g_variant_get_uint64(data);
824 if (devc->limit_msec > 0)
829 case SR_CONF_LIMIT_SAMPLES:
830 num_samples = g_variant_get_uint64(data);
831 devc->limit_msec = num_samples * 1000 / devc->cur_samplerate;
833 case SR_CONF_CAPTURE_RATIO:
834 devc->capture_ratio = g_variant_get_uint64(data);
835 if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
847 static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi,
848 const struct sr_channel_group *cg)
857 case SR_CONF_DEVICE_OPTIONS:
858 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
859 hwcaps, ARRAY_SIZE(hwcaps), sizeof(int32_t));
861 case SR_CONF_SAMPLERATE:
862 g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
863 gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
864 ARRAY_SIZE(samplerates), sizeof(uint64_t));
865 g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
866 *data = g_variant_builder_end(&gvb);
868 case SR_CONF_TRIGGER_TYPE:
869 *data = g_variant_new_string(TRIGGER_TYPE);
878 /* Software trigger to determine exact trigger position. */
879 static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
880 struct sigma_trigger *t)
884 for (i = 0; i < 8; ++i) {
886 last_sample = samples[i-1];
888 /* Simple triggers. */
889 if ((samples[i] & t->simplemask) != t->simplevalue)
893 if ((last_sample & t->risingmask) != 0 || (samples[i] &
894 t->risingmask) != t->risingmask)
898 if ((last_sample & t->fallingmask) != t->fallingmask ||
899 (samples[i] & t->fallingmask) != 0)
905 /* If we did not match, return original trigger pos. */
910 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
911 * Each event is 20ns apart, and can contain multiple samples.
913 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
914 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
915 * For 50 MHz and below, events contain one sample for each channel,
916 * spread 20 ns apart.
918 static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
919 uint16_t *lastsample, int triggerpos,
920 uint16_t limit_chunk, void *cb_data)
922 struct sr_dev_inst *sdi = cb_data;
923 struct dev_context *devc = sdi->priv;
925 uint16_t samples[65536 * devc->samples_per_event];
926 struct sr_datafeed_packet packet;
927 struct sr_datafeed_logic logic;
928 int i, j, k, l, numpad, tosend;
929 size_t n = 0, sent = 0;
930 int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event;
935 /* Check if trigger is in this chunk. */
936 if (triggerpos != -1) {
937 if (devc->cur_samplerate <= SR_MHZ(50))
938 triggerpos -= EVENTS_PER_CLUSTER - 1;
943 /* Find in which cluster the trigger occured. */
944 triggerts = triggerpos / 7;
948 for (i = 0; i < 64; ++i) {
949 ts = *(uint16_t *) &buf[i * 16];
950 tsdiff = ts - *lastts;
953 /* Decode partial chunk. */
954 if (limit_chunk && ts > limit_chunk)
957 /* Pad last sample up to current point. */
958 numpad = tsdiff * devc->samples_per_event - clustersize;
960 for (j = 0; j < numpad; ++j)
961 samples[j] = *lastsample;
966 /* Send samples between previous and this timestamp to sigrok. */
969 tosend = MIN(2048, n - sent);
971 packet.type = SR_DF_LOGIC;
972 packet.payload = &logic;
973 logic.length = tosend * sizeof(uint16_t);
975 logic.data = samples + sent;
976 sr_session_send(devc->cb_data, &packet);
982 event = (uint16_t *) &buf[i * 16 + 2];
985 /* For each event in cluster. */
986 for (j = 0; j < 7; ++j) {
988 /* For each sample in event. */
989 for (k = 0; k < devc->samples_per_event; ++k) {
992 /* For each channel. */
993 for (l = 0; l < devc->num_channels; ++l)
994 cur_sample |= (!!(event[j] & (1 << (l *
995 devc->samples_per_event + k)))) << l;
997 samples[n++] = cur_sample;
1001 /* Send data up to trigger point (if triggered). */
1003 if (i == triggerts) {
1005 * Trigger is not always accurate to sample because of
1006 * pipeline delay. However, it always triggers before
1007 * the actual event. We therefore look at the next
1008 * samples to pinpoint the exact position of the trigger.
1010 tosend = get_trigger_offset(samples, *lastsample,
1014 packet.type = SR_DF_LOGIC;
1015 packet.payload = &logic;
1016 logic.length = tosend * sizeof(uint16_t);
1018 logic.data = samples;
1019 sr_session_send(devc->cb_data, &packet);
1024 /* Only send trigger if explicitly enabled. */
1025 if (devc->use_triggers) {
1026 packet.type = SR_DF_TRIGGER;
1027 sr_session_send(devc->cb_data, &packet);
1031 /* Send rest of the chunk to sigrok. */
1035 packet.type = SR_DF_LOGIC;
1036 packet.payload = &logic;
1037 logic.length = tosend * sizeof(uint16_t);
1039 logic.data = samples + sent;
1040 sr_session_send(devc->cb_data, &packet);
1043 *lastsample = samples[n - 1];
1049 static void download_capture(struct sr_dev_inst *sdi)
1051 struct dev_context *devc;
1052 const int chunks_per_read = 32;
1053 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1054 int bufsz, i, numchunks, newchunks;
1056 sr_info("Downloading sample data.");
1059 devc->state.chunks_downloaded = 0;
1060 numchunks = (devc->state.stoppos + 511) / 512;
1061 newchunks = MIN(chunks_per_read, numchunks - devc->state.chunks_downloaded);
1063 bufsz = sigma_read_dram(devc->state.chunks_downloaded, newchunks, buf, devc);
1064 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1067 /* Find first ts. */
1068 if (devc->state.chunks_downloaded == 0) {
1069 devc->state.lastts = RL16(buf) - 1;
1070 devc->state.lastsample = 0;
1073 /* Decode chunks and send them to sigrok. */
1074 for (i = 0; i < newchunks; ++i) {
1075 int limit_chunk = 0;
1077 /* The last chunk may potentially be only in part. */
1078 if (devc->state.chunks_downloaded == numchunks - 1) {
1079 /* Find the last valid timestamp */
1080 limit_chunk = devc->state.stoppos % 512 + devc->state.lastts;
1083 if (devc->state.chunks_downloaded + i == devc->state.triggerchunk)
1084 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1085 &devc->state.lastts,
1086 &devc->state.lastsample,
1087 devc->state.triggerpos & 0x1ff,
1090 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1091 &devc->state.lastts,
1092 &devc->state.lastsample,
1093 -1, limit_chunk, sdi);
1095 ++devc->state.chunks_downloaded;
1100 static int receive_data(int fd, int revents, void *cb_data)
1102 struct sr_dev_inst *sdi;
1103 struct dev_context *devc;
1104 struct sr_datafeed_packet packet;
1105 uint64_t running_msec;
1116 /* Get the current position. */
1117 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1119 if (devc->state.state == SIGMA_IDLE)
1122 if (devc->state.state == SIGMA_CAPTURE) {
1123 numchunks = (devc->state.stoppos + 511) / 512;
1125 /* Check if the timer has expired, or memory is full. */
1126 gettimeofday(&tv, 0);
1127 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1128 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1130 if (running_msec < devc->limit_msec && numchunks < 32767)
1131 /* Still capturing. */
1134 /* Stop acquisition. */
1135 sigma_set_register(WRITE_MODE, 0x11, devc);
1137 /* Set SDRAM Read Enable. */
1138 sigma_set_register(WRITE_MODE, 0x02, devc);
1140 /* Get the current position. */
1141 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1143 /* Check if trigger has fired. */
1144 modestatus = sigma_get_register(READ_MODE, devc);
1145 if (modestatus & 0x20)
1146 devc->state.triggerchunk = devc->state.triggerpos / 512;
1148 devc->state.triggerchunk = -1;
1150 /* Transfer captured data from device. */
1151 download_capture(sdi);
1154 packet.type = SR_DF_END;
1155 sr_session_send(sdi, &packet);
1157 dev_acquisition_stop(sdi, sdi);
1163 /* Build a LUT entry used by the trigger functions. */
1164 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1168 /* For each quad channel. */
1169 for (i = 0; i < 4; ++i) {
1172 /* For each bit in LUT. */
1173 for (j = 0; j < 16; ++j)
1175 /* For each channel in quad. */
1176 for (k = 0; k < 4; ++k) {
1177 bit = 1 << (i * 4 + k);
1179 /* Set bit in entry */
1181 ((!(value & bit)) !=
1183 entry[i] &= ~(1 << j);
1188 /* Add a logical function to LUT mask. */
1189 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1190 int index, int neg, uint16_t *mask)
1193 int x[2][2], tmp, a, b, aset, bset, rset;
1195 memset(x, 0, 4 * sizeof(int));
1197 /* Trigger detect condition. */
1227 case OP_NOTRISEFALL:
1233 /* Transpose if neg is set. */
1235 for (i = 0; i < 2; ++i) {
1236 for (j = 0; j < 2; ++j) {
1238 x[i][j] = x[1-i][1-j];
1244 /* Update mask with function. */
1245 for (i = 0; i < 16; ++i) {
1246 a = (i >> (2 * index + 0)) & 1;
1247 b = (i >> (2 * index + 1)) & 1;
1249 aset = (*mask >> i) & 1;
1252 if (func == FUNC_AND || func == FUNC_NAND)
1254 else if (func == FUNC_OR || func == FUNC_NOR)
1256 else if (func == FUNC_XOR || func == FUNC_NXOR)
1259 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1270 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1271 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1272 * set at any time, but a full mask and value can be set (0/1).
1274 static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1277 uint16_t masks[2] = { 0, 0 };
1279 memset(lut, 0, sizeof(struct triggerlut));
1281 /* Contant for simple triggers. */
1284 /* Value/mask trigger support. */
1285 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1288 /* Rise/fall trigger support. */
1289 for (i = 0, j = 0; i < 16; ++i) {
1290 if (devc->trigger.risingmask & (1 << i) ||
1291 devc->trigger.fallingmask & (1 << i))
1292 masks[j++] = 1 << i;
1295 build_lut_entry(masks[0], masks[0], lut->m0d);
1296 build_lut_entry(masks[1], masks[1], lut->m1d);
1298 /* Add glue logic */
1299 if (masks[0] || masks[1]) {
1300 /* Transition trigger. */
1301 if (masks[0] & devc->trigger.risingmask)
1302 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1303 if (masks[0] & devc->trigger.fallingmask)
1304 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1305 if (masks[1] & devc->trigger.risingmask)
1306 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1307 if (masks[1] & devc->trigger.fallingmask)
1308 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1310 /* Only value/mask trigger. */
1314 /* Triggertype: event. */
1315 lut->params.selres = 3;
1320 static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
1322 struct dev_context *devc;
1323 struct clockselect_50 clockselect;
1324 int frac, triggerpin, ret;
1325 uint8_t triggerselect = 0;
1326 struct triggerinout triggerinout_conf;
1327 struct triggerlut lut;
1329 if (sdi->status != SR_ST_ACTIVE)
1330 return SR_ERR_DEV_CLOSED;
1334 if (configure_channels(sdi) != SR_OK) {
1335 sr_err("Failed to configure channels.");
1339 /* If the samplerate has not been set, default to 200 kHz. */
1340 if (devc->cur_firmware == -1) {
1341 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1345 /* Enter trigger programming mode. */
1346 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1348 /* 100 and 200 MHz mode. */
1349 if (devc->cur_samplerate >= SR_MHZ(100)) {
1350 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1352 /* Find which pin to trigger on from mask. */
1353 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1354 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1358 /* Set trigger pin and light LED on trigger. */
1359 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1361 /* Default rising edge. */
1362 if (devc->trigger.fallingmask)
1363 triggerselect |= 1 << 3;
1365 /* All other modes. */
1366 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1367 build_basic_trigger(&lut, devc);
1369 sigma_write_trigger_lut(&lut, devc);
1371 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1374 /* Setup trigger in and out pins to default values. */
1375 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1376 triggerinout_conf.trgout_bytrigger = 1;
1377 triggerinout_conf.trgout_enable = 1;
1379 sigma_write_register(WRITE_TRIGGER_OPTION,
1380 (uint8_t *) &triggerinout_conf,
1381 sizeof(struct triggerinout), devc);
1383 /* Go back to normal mode. */
1384 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1386 /* Set clock select register. */
1387 if (devc->cur_samplerate == SR_MHZ(200))
1388 /* Enable 4 channels. */
1389 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1390 else if (devc->cur_samplerate == SR_MHZ(100))
1391 /* Enable 8 channels. */
1392 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1395 * 50 MHz mode (or fraction thereof). Any fraction down to
1396 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1398 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1400 clockselect.async = 0;
1401 clockselect.fraction = frac;
1402 clockselect.disabled_channels = 0;
1404 sigma_write_register(WRITE_CLOCK_SELECT,
1405 (uint8_t *) &clockselect,
1406 sizeof(clockselect), devc);
1409 /* Setup maximum post trigger time. */
1410 sigma_set_register(WRITE_POST_TRIGGER,
1411 (devc->capture_ratio * 255) / 100, devc);
1413 /* Start acqusition. */
1414 gettimeofday(&devc->start_tv, 0);
1415 sigma_set_register(WRITE_MODE, 0x0d, devc);
1417 devc->cb_data = cb_data;
1419 /* Send header packet to the session bus. */
1420 std_session_send_df_header(cb_data, LOG_PREFIX);
1422 /* Add capture source. */
1423 sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
1425 devc->state.state = SIGMA_CAPTURE;
1430 static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1432 struct dev_context *devc;
1437 devc->state.state = SIGMA_IDLE;
1439 sr_source_remove(0);
1444 SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1445 .name = "asix-sigma",
1446 .longname = "ASIX SIGMA/SIGMA2",
1451 .dev_list = dev_list,
1452 .dev_clear = dev_clear,
1453 .config_get = config_get,
1454 .config_set = config_set,
1455 .config_list = config_list,
1456 .dev_open = dev_open,
1457 .dev_close = dev_close,
1458 .dev_acquisition_start = dev_acquisition_start,
1459 .dev_acquisition_stop = dev_acquisition_stop,