2 * This file is part of the libsigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
27 #include <glib/gstdio.h>
30 #include "libsigrok.h"
31 #include "libsigrok-internal.h"
32 #include "asix-sigma.h"
34 #define USB_VENDOR 0xa600
35 #define USB_PRODUCT 0xa000
36 #define USB_DESCRIPTION "ASIX SIGMA"
37 #define USB_VENDOR_NAME "ASIX"
38 #define USB_MODEL_NAME "SIGMA"
39 #define TRIGGER_TYPE "rf10"
41 SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
42 static struct sr_dev_driver *di = &asix_sigma_driver_info;
43 static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
46 * The ASIX Sigma supports arbitrary integer frequency divider in
47 * the 50MHz mode. The divider is in range 1...256 , allowing for
48 * very precise sampling rate selection. This driver supports only
49 * a subset of the sampling rates.
51 static const uint64_t samplerates[] = {
52 SR_KHZ(200), /* div=250 */
53 SR_KHZ(250), /* div=200 */
54 SR_KHZ(500), /* div=100 */
55 SR_MHZ(1), /* div=50 */
56 SR_MHZ(5), /* div=10 */
57 SR_MHZ(10), /* div=5 */
58 SR_MHZ(25), /* div=2 */
59 SR_MHZ(50), /* div=1 */
60 SR_MHZ(100), /* Special FW needed */
61 SR_MHZ(200), /* Special FW needed */
65 * Channel numbers seem to go from 1-16, according to this image:
66 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
67 * (the cable has two additional GND pins, and a TI and TO pin)
69 static const char *channel_names[] = {
70 "1", "2", "3", "4", "5", "6", "7", "8",
71 "9", "10", "11", "12", "13", "14", "15", "16",
74 static const int32_t hwcaps[] = {
75 SR_CONF_LOGIC_ANALYZER,
78 SR_CONF_CAPTURE_RATIO,
80 SR_CONF_LIMIT_SAMPLES,
83 static const char *sigma_firmware_files[] = {
84 /* 50 MHz, supports 8 bit fractions */
85 FIRMWARE_DIR "/asix-sigma-50.fw",
87 FIRMWARE_DIR "/asix-sigma-100.fw",
89 FIRMWARE_DIR "/asix-sigma-200.fw",
90 /* Synchronous clock from pin */
91 FIRMWARE_DIR "/asix-sigma-50sync.fw",
92 /* Frequency counter */
93 FIRMWARE_DIR "/asix-sigma-phasor.fw",
96 static int sigma_read(void *buf, size_t size, struct dev_context *devc)
100 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
102 sr_err("ftdi_read_data failed: %s",
103 ftdi_get_error_string(&devc->ftdic));
109 static int sigma_write(void *buf, size_t size, struct dev_context *devc)
113 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
115 sr_err("ftdi_write_data failed: %s",
116 ftdi_get_error_string(&devc->ftdic));
117 } else if ((size_t) ret != size) {
118 sr_err("ftdi_write_data did not complete write.");
124 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
125 struct dev_context *devc)
128 uint8_t buf[len + 2];
131 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
132 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
134 for (i = 0; i < len; ++i) {
135 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
136 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
139 return sigma_write(buf, idx, devc);
142 static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
144 return sigma_write_register(reg, &value, 1, devc);
147 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
148 struct dev_context *devc)
152 buf[0] = REG_ADDR_LOW | (reg & 0xf);
153 buf[1] = REG_ADDR_HIGH | (reg >> 4);
154 buf[2] = REG_READ_ADDR;
156 sigma_write(buf, sizeof(buf), devc);
158 return sigma_read(data, len, devc);
161 static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
165 if (1 != sigma_read_register(reg, &value, 1, devc)) {
166 sr_err("sigma_get_register: 1 byte expected");
173 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
174 struct dev_context *devc)
177 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
179 REG_READ_ADDR | NEXT_REG,
180 REG_READ_ADDR | NEXT_REG,
181 REG_READ_ADDR | NEXT_REG,
182 REG_READ_ADDR | NEXT_REG,
183 REG_READ_ADDR | NEXT_REG,
184 REG_READ_ADDR | NEXT_REG,
188 sigma_write(buf, sizeof(buf), devc);
190 sigma_read(result, sizeof(result), devc);
192 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
193 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
195 /* Not really sure why this must be done, but according to spec. */
196 if ((--*stoppos & 0x1ff) == 0x1ff)
199 if ((*--triggerpos & 0x1ff) == 0x1ff)
205 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
206 uint8_t *data, struct dev_context *devc)
212 /* Send the startchunk. Index start with 1. */
213 buf[0] = startchunk >> 8;
214 buf[1] = startchunk & 0xff;
215 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
218 buf[idx++] = REG_DRAM_BLOCK;
219 buf[idx++] = REG_DRAM_WAIT_ACK;
221 for (i = 0; i < numchunks; ++i) {
222 /* Alternate bit to copy from DRAM to cache. */
223 if (i != (numchunks - 1))
224 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
226 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
228 if (i != (numchunks - 1))
229 buf[idx++] = REG_DRAM_WAIT_ACK;
232 sigma_write(buf, idx, devc);
234 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
237 /* Upload trigger look-up tables to Sigma. */
238 static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
244 /* Transpose the table and send to Sigma. */
245 for (i = 0; i < 16; ++i) {
250 if (lut->m2d[0] & bit)
252 if (lut->m2d[1] & bit)
254 if (lut->m2d[2] & bit)
256 if (lut->m2d[3] & bit)
266 if (lut->m0d[0] & bit)
268 if (lut->m0d[1] & bit)
270 if (lut->m0d[2] & bit)
272 if (lut->m0d[3] & bit)
275 if (lut->m1d[0] & bit)
277 if (lut->m1d[1] & bit)
279 if (lut->m1d[2] & bit)
281 if (lut->m1d[3] & bit)
284 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
286 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
289 /* Send the parameters */
290 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
291 sizeof(lut->params), devc);
296 static void clear_helper(void *priv)
298 struct dev_context *devc;
302 ftdi_deinit(&devc->ftdic);
305 static int dev_clear(void)
307 return std_dev_clear(di, clear_helper);
310 static int init(struct sr_context *sr_ctx)
312 return std_init(sr_ctx, di, LOG_PREFIX);
315 static GSList *scan(GSList *options)
317 struct sr_dev_inst *sdi;
318 struct sr_channel *ch;
319 struct drv_context *drvc;
320 struct dev_context *devc;
322 struct ftdi_device_list *devlist;
334 if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
335 sr_err("%s: devc malloc failed", __func__);
339 ftdi_init(&devc->ftdic);
341 /* Look for SIGMAs. */
343 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
344 USB_VENDOR, USB_PRODUCT)) <= 0) {
346 sr_err("ftdi_usb_find_all(): %d", ret);
350 /* Make sure it's a version 1 or 2 SIGMA. */
351 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
352 serial_txt, sizeof(serial_txt));
353 sscanf(serial_txt, "%x", &serial);
355 if (serial < 0xa6010000 || serial > 0xa602ffff) {
356 sr_err("Only SIGMA and SIGMA2 are supported "
357 "in this version of libsigrok.");
361 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
363 devc->cur_samplerate = 0;
365 devc->limit_msec = 0;
366 devc->cur_firmware = -1;
367 devc->num_channels = 0;
368 devc->samples_per_event = 0;
369 devc->capture_ratio = 50;
370 devc->use_triggers = 0;
372 /* Register SIGMA device. */
373 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
374 USB_MODEL_NAME, NULL))) {
375 sr_err("%s: sdi was NULL", __func__);
380 for (i = 0; i < ARRAY_SIZE(channel_names); i++) {
381 ch = sr_channel_new(i, SR_CHANNEL_LOGIC, TRUE,
385 sdi->channels = g_slist_append(sdi->channels, ch);
388 devices = g_slist_append(devices, sdi);
389 drvc->instances = g_slist_append(drvc->instances, sdi);
392 /* We will open the device again when we need it. */
393 ftdi_list_free(&devlist);
398 ftdi_deinit(&devc->ftdic);
403 static GSList *dev_list(void)
405 return ((struct drv_context *)(di->priv))->instances;
409 * Configure the FPGA for bitbang mode.
410 * This sequence is documented in section 2. of the ASIX Sigma programming
411 * manual. This sequence is necessary to configure the FPGA in the Sigma
412 * into Bitbang mode, in which it can be programmed with the firmware.
414 static int sigma_fpga_init_bitbang(struct dev_context *devc)
416 uint8_t suicide[] = {
417 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
419 uint8_t init_array[] = {
420 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
423 int i, ret, timeout = 10000;
426 /* Section 2. part 1), do the FPGA suicide. */
427 sigma_write(suicide, sizeof(suicide), devc);
428 sigma_write(suicide, sizeof(suicide), devc);
429 sigma_write(suicide, sizeof(suicide), devc);
430 sigma_write(suicide, sizeof(suicide), devc);
432 /* Section 2. part 2), do pulse on D1. */
433 sigma_write(init_array, sizeof(init_array), devc);
434 ftdi_usb_purge_buffers(&devc->ftdic);
436 /* Wait until the FPGA asserts D6/INIT_B. */
437 for (i = 0; i < timeout; i++) {
438 ret = sigma_read(&data, 1, devc);
441 /* Test if pin D6 got asserted. */
444 /* The D6 was not asserted yet, wait a bit. */
448 return SR_ERR_TIMEOUT;
452 * Configure the FPGA for logic-analyzer mode.
454 static int sigma_fpga_init_la(struct dev_context *devc)
456 /* Initialize the logic analyzer mode. */
457 uint8_t logic_mode_start[] = {
458 REG_ADDR_LOW | (READ_ID & 0xf),
459 REG_ADDR_HIGH | (READ_ID >> 8),
460 REG_READ_ADDR, /* Read ID register. */
462 REG_ADDR_LOW | (WRITE_TEST & 0xf),
464 REG_DATA_HIGH_WRITE | 0x5,
465 REG_READ_ADDR, /* Read scratch register. */
468 REG_DATA_HIGH_WRITE | 0xa,
469 REG_READ_ADDR, /* Read scratch register. */
471 REG_ADDR_LOW | (WRITE_MODE & 0xf),
473 REG_DATA_HIGH_WRITE | 0x8,
479 /* Initialize the logic analyzer mode. */
480 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
482 /* Expect a 3 byte reply since we issued three READ requests. */
483 ret = sigma_read(result, 3, devc);
487 if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa)
492 sr_err("Configuration failed. Invalid reply received.");
497 * Read the firmware from a file and transform it into a series of bitbang
498 * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d
499 * by the caller of this function.
501 static int sigma_fw_2_bitbang(const char *filename,
502 uint8_t **bb_cmd, gsize *bb_cmd_size)
506 gsize i, file_size, bb_size;
508 uint8_t *bb_stream, *bbs;
514 * Map the file and make the mapped buffer writable.
515 * NOTE: Using writable=TRUE does _NOT_ mean that file that is mapped
516 * will be modified. It will not be modified until someone uses
517 * g_file_set_contents() on it.
520 file = g_mapped_file_new(filename, TRUE, &error);
521 g_assert_no_error(error);
523 file_size = g_mapped_file_get_length(file);
524 firmware = g_mapped_file_get_contents(file);
527 /* Weird magic transformation below, I have no idea what it does. */
529 for (i = 0; i < file_size; i++) {
530 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
531 firmware[i] ^= imm & 0xff;
535 * Now that the firmware is "transformed", we will transcribe the
536 * firmware blob into a sequence of toggles of the Dx wires. This
537 * sequence will be fed directly into the Sigma, which must be in
538 * the FPGA bitbang programming mode.
541 /* Each bit of firmware is transcribed as two toggles of Dx wires. */
542 bb_size = file_size * 8 * 2;
543 bb_stream = (uint8_t *)g_try_malloc(bb_size);
545 sr_err("%s: Failed to allocate bitbang stream", __func__);
551 for (i = 0; i < file_size; i++) {
552 for (bit = 7; bit >= 0; bit--) {
553 v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00;
559 /* The transformation completed successfully, return the result. */
561 *bb_cmd_size = bb_size;
564 g_mapped_file_unref(file);
568 static int upload_firmware(int firmware_idx, struct dev_context *devc)
574 const char *firmware = sigma_firmware_files[firmware_idx];
575 struct ftdi_context *ftdic = &devc->ftdic;
577 /* Make sure it's an ASIX SIGMA. */
578 ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT,
579 USB_DESCRIPTION, NULL);
581 sr_err("ftdi_usb_open failed: %s",
582 ftdi_get_error_string(ftdic));
586 ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG);
588 sr_err("ftdi_set_bitmode failed: %s",
589 ftdi_get_error_string(ftdic));
593 /* Four times the speed of sigmalogan - Works well. */
594 ret = ftdi_set_baudrate(ftdic, 750000);
596 sr_err("ftdi_set_baudrate failed: %s",
597 ftdi_get_error_string(ftdic));
601 /* Initialize the FPGA for firmware upload. */
602 ret = sigma_fpga_init_bitbang(devc);
606 /* Prepare firmware. */
607 ret = sigma_fw_2_bitbang(firmware, &buf, &buf_size);
609 sr_err("An error occured while reading the firmware: %s",
614 /* Upload firmare. */
615 sr_info("Uploading firmware file '%s'.", firmware);
616 sigma_write(buf, buf_size, devc);
620 ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET);
622 sr_err("ftdi_set_bitmode failed: %s",
623 ftdi_get_error_string(ftdic));
627 ftdi_usb_purge_buffers(ftdic);
629 /* Discard garbage. */
630 while (sigma_read(&pins, 1, devc) == 1)
633 /* Initialize the FPGA for logic-analyzer mode. */
634 ret = sigma_fpga_init_la(devc);
638 devc->cur_firmware = firmware_idx;
640 sr_info("Firmware uploaded.");
645 static int dev_open(struct sr_dev_inst *sdi)
647 struct dev_context *devc;
652 /* Make sure it's an ASIX SIGMA. */
653 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
654 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
656 sr_err("ftdi_usb_open failed: %s",
657 ftdi_get_error_string(&devc->ftdic));
662 sdi->status = SR_ST_ACTIVE;
667 static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
669 struct dev_context *devc;
676 for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
677 if (samplerates[i] == samplerate)
680 if (samplerates[i] == 0)
681 return SR_ERR_SAMPLERATE;
683 if (samplerate <= SR_MHZ(50)) {
684 ret = upload_firmware(0, devc);
685 devc->num_channels = 16;
687 if (samplerate == SR_MHZ(100)) {
688 ret = upload_firmware(1, devc);
689 devc->num_channels = 8;
691 else if (samplerate == SR_MHZ(200)) {
692 ret = upload_firmware(2, devc);
693 devc->num_channels = 4;
696 devc->cur_samplerate = samplerate;
697 devc->period_ps = 1000000000000ULL / samplerate;
698 devc->samples_per_event = 16 / devc->num_channels;
699 devc->state.state = SIGMA_IDLE;
705 * In 100 and 200 MHz mode, only a single pin rising/falling can be
706 * set as trigger. In other modes, two rising/falling triggers can be set,
707 * in addition to value/mask trigger for any number of channels.
709 * The Sigma supports complex triggers using boolean expressions, but this
710 * has not been implemented yet.
712 static int configure_channels(const struct sr_dev_inst *sdi)
714 struct dev_context *devc = sdi->priv;
715 const struct sr_channel *ch;
720 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
722 for (l = sdi->channels; l; l = l->next) {
723 ch = (struct sr_channel *)l->data;
724 channelbit = 1 << (ch->index);
726 if (!ch->enabled || !ch->trigger)
729 if (devc->cur_samplerate >= SR_MHZ(100)) {
730 /* Fast trigger support. */
732 sr_err("Only a single pin trigger in 100 and "
733 "200MHz mode is supported.");
736 if (ch->trigger[0] == 'f')
737 devc->trigger.fallingmask |= channelbit;
738 else if (ch->trigger[0] == 'r')
739 devc->trigger.risingmask |= channelbit;
741 sr_err("Only rising/falling trigger in 100 "
742 "and 200MHz mode is supported.");
748 /* Simple trigger support (event). */
749 if (ch->trigger[0] == '1') {
750 devc->trigger.simplevalue |= channelbit;
751 devc->trigger.simplemask |= channelbit;
753 else if (ch->trigger[0] == '0') {
754 devc->trigger.simplevalue &= ~channelbit;
755 devc->trigger.simplemask |= channelbit;
757 else if (ch->trigger[0] == 'f') {
758 devc->trigger.fallingmask |= channelbit;
761 else if (ch->trigger[0] == 'r') {
762 devc->trigger.risingmask |= channelbit;
767 * Actually, Sigma supports 2 rising/falling triggers,
768 * but they are ORed and the current trigger syntax
769 * does not permit ORed triggers.
771 if (trigger_set > 1) {
772 sr_err("Only 1 rising/falling trigger "
779 devc->use_triggers = 1;
785 static int dev_close(struct sr_dev_inst *sdi)
787 struct dev_context *devc;
792 if (sdi->status == SR_ST_ACTIVE)
793 ftdi_usb_close(&devc->ftdic);
795 sdi->status = SR_ST_INACTIVE;
800 static int cleanup(void)
805 static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi,
806 const struct sr_channel_group *cg)
808 struct dev_context *devc;
813 case SR_CONF_SAMPLERATE:
816 *data = g_variant_new_uint64(devc->cur_samplerate);
827 static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi,
828 const struct sr_channel_group *cg)
830 struct dev_context *devc;
831 uint64_t num_samples;
836 if (sdi->status != SR_ST_ACTIVE)
837 return SR_ERR_DEV_CLOSED;
842 case SR_CONF_SAMPLERATE:
843 ret = set_samplerate(sdi, g_variant_get_uint64(data));
845 case SR_CONF_LIMIT_MSEC:
846 devc->limit_msec = g_variant_get_uint64(data);
847 if (devc->limit_msec > 0)
852 case SR_CONF_LIMIT_SAMPLES:
853 num_samples = g_variant_get_uint64(data);
854 devc->limit_msec = num_samples * 1000 / devc->cur_samplerate;
856 case SR_CONF_CAPTURE_RATIO:
857 devc->capture_ratio = g_variant_get_uint64(data);
858 if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
870 static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi,
871 const struct sr_channel_group *cg)
880 case SR_CONF_DEVICE_OPTIONS:
881 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
882 hwcaps, ARRAY_SIZE(hwcaps), sizeof(int32_t));
884 case SR_CONF_SAMPLERATE:
885 g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
886 gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
887 ARRAY_SIZE(samplerates), sizeof(uint64_t));
888 g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
889 *data = g_variant_builder_end(&gvb);
891 case SR_CONF_TRIGGER_TYPE:
892 *data = g_variant_new_string(TRIGGER_TYPE);
901 /* Software trigger to determine exact trigger position. */
902 static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
903 struct sigma_trigger *t)
907 for (i = 0; i < 8; ++i) {
909 last_sample = samples[i-1];
911 /* Simple triggers. */
912 if ((samples[i] & t->simplemask) != t->simplevalue)
916 if ((last_sample & t->risingmask) != 0 || (samples[i] &
917 t->risingmask) != t->risingmask)
921 if ((last_sample & t->fallingmask) != t->fallingmask ||
922 (samples[i] & t->fallingmask) != 0)
928 /* If we did not match, return original trigger pos. */
934 * Return the timestamp of "DRAM cluster".
936 static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster)
938 return (cluster->timestamp_hi << 8) | cluster->timestamp_lo;
942 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
943 * Each event is 20ns apart, and can contain multiple samples.
945 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
946 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
947 * For 50 MHz and below, events contain one sample for each channel,
948 * spread 20 ns apart.
950 static int decode_chunk_ts(struct sigma_dram_line *dram_line, uint16_t *lastts,
951 uint16_t *lastsample, int triggerpos,
952 uint16_t events_in_line, void *cb_data)
954 uint8_t *buf = (uint8_t *)dram_line;
955 struct sigma_dram_cluster *dram_cluster;
956 struct sr_dev_inst *sdi = cb_data;
957 struct dev_context *devc = sdi->priv;
959 uint16_t samples[65536 * devc->samples_per_event];
960 struct sr_datafeed_packet packet;
961 struct sr_datafeed_logic logic;
962 int i, j, k, l, numpad, tosend;
963 size_t n = 0, sent = 0;
964 int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event;
969 /* Check if trigger is in this chunk. */
970 if (triggerpos != -1) {
971 if (devc->cur_samplerate <= SR_MHZ(50))
972 triggerpos -= EVENTS_PER_CLUSTER - 1;
977 /* Find in which cluster the trigger occured. */
978 triggerts = triggerpos / 7;
982 for (i = 0; i < (events_in_line / 7); i++) {
983 dram_cluster = &dram_line->cluster[i];
984 ts = sigma_dram_cluster_ts(dram_cluster);
985 tsdiff = ts - *lastts;
988 /* Pad last sample up to current point. */
989 numpad = tsdiff * devc->samples_per_event - clustersize;
991 for (j = 0; j < numpad; ++j)
992 samples[j] = *lastsample;
997 /* Send samples between previous and this timestamp to sigrok. */
1000 tosend = MIN(2048, n - sent);
1002 packet.type = SR_DF_LOGIC;
1003 packet.payload = &logic;
1004 logic.length = tosend * sizeof(uint16_t);
1006 logic.data = samples + sent;
1007 sr_session_send(devc->cb_data, &packet);
1013 event = (uint16_t *) &buf[i * 16 + 2];
1016 /* For each event in cluster. */
1017 for (j = 0; j < 7; ++j) {
1019 /* For each sample in event. */
1020 for (k = 0; k < devc->samples_per_event; ++k) {
1023 /* For each channel. */
1024 for (l = 0; l < devc->num_channels; ++l)
1025 cur_sample |= (!!(event[j] & (1 << (l *
1026 devc->samples_per_event + k)))) << l;
1028 samples[n++] = cur_sample;
1032 /* Send data up to trigger point (if triggered). */
1034 if (i == triggerts) {
1036 * Trigger is not always accurate to sample because of
1037 * pipeline delay. However, it always triggers before
1038 * the actual event. We therefore look at the next
1039 * samples to pinpoint the exact position of the trigger.
1041 tosend = get_trigger_offset(samples, *lastsample,
1045 packet.type = SR_DF_LOGIC;
1046 packet.payload = &logic;
1047 logic.length = tosend * sizeof(uint16_t);
1049 logic.data = samples;
1050 sr_session_send(devc->cb_data, &packet);
1055 /* Only send trigger if explicitly enabled. */
1056 if (devc->use_triggers) {
1057 packet.type = SR_DF_TRIGGER;
1058 sr_session_send(devc->cb_data, &packet);
1062 /* Send rest of the chunk to sigrok. */
1066 packet.type = SR_DF_LOGIC;
1067 packet.payload = &logic;
1068 logic.length = tosend * sizeof(uint16_t);
1070 logic.data = samples + sent;
1071 sr_session_send(devc->cb_data, &packet);
1074 *lastsample = samples[n - 1];
1080 static int download_capture(struct sr_dev_inst *sdi)
1082 struct dev_context *devc = sdi->priv;
1083 const int chunks_per_read = 32;
1084 struct sigma_dram_line *dram_line;
1086 uint32_t stoppos, triggerpos;
1087 struct sr_datafeed_packet packet;
1091 uint32_t dl_lines_total, dl_lines_curr, dl_lines_done;
1092 uint32_t dl_events_in_line = 64 * 7;
1093 uint32_t trg_line = ~0;
1095 dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line));
1099 sr_info("Downloading sample data.");
1101 /* Stop acquisition. */
1102 sigma_set_register(WRITE_MODE, 0x11, devc);
1104 /* Set SDRAM Read Enable. */
1105 sigma_set_register(WRITE_MODE, 0x02, devc);
1107 /* Get the current position. */
1108 sigma_read_pos(&stoppos, &triggerpos, devc);
1110 /* Check if trigger has fired. */
1111 modestatus = sigma_get_register(READ_MODE, devc);
1112 if (modestatus & 0x20)
1113 trg_line = triggerpos >> 9;
1116 * Determine how many 1024b "DRAM lines" do we need to read from the
1117 * Sigma so we have a complete set of samples. Note that the last
1118 * line can be only partial, containing less than 64 clusters.
1120 dl_lines_total = (stoppos >> 9) + 1;
1124 while (dl_lines_total > dl_lines_done) {
1125 /* We can download only up-to 32 DRAM lines in one go! */
1126 dl_lines_curr = MIN(chunks_per_read, dl_lines_total);
1128 bufsz = sigma_read_dram(dl_lines_done, dl_lines_curr,
1129 (uint8_t *)dram_line, devc);
1130 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1133 /* This is the first DRAM line, so find the initial timestamp. */
1134 if (dl_lines_done == 0) {
1135 devc->state.lastts =
1136 sigma_dram_cluster_ts(&dram_line[0].cluster[0]);
1137 devc->state.lastsample = 0;
1140 for (i = 0; i < dl_lines_curr; i++) {
1141 int trigger_line = -1;
1142 /* The last "DRAM line" can be only partially full. */
1143 if (dl_lines_done + i == dl_lines_total - 1)
1144 dl_events_in_line = stoppos & 0x1ff;
1146 /* Test if the trigger happened on this line. */
1147 if (dl_lines_done + i == trg_line)
1148 trigger_line = trg_line;
1150 decode_chunk_ts(dram_line + i,
1151 &devc->state.lastts,
1152 &devc->state.lastsample,
1154 dl_events_in_line, sdi);
1157 dl_lines_done += dl_lines_curr;
1161 packet.type = SR_DF_END;
1162 sr_session_send(sdi, &packet);
1164 dev_acquisition_stop(sdi, sdi);
1172 * Handle the Sigma when in CAPTURE mode. This function checks:
1173 * - Sampling time ended
1174 * - DRAM capacity overflow
1175 * This function triggers download of the samples from Sigma
1176 * in case either of the above conditions is true.
1178 static int sigma_capture_mode(struct sr_dev_inst *sdi)
1180 struct dev_context *devc = sdi->priv;
1182 uint64_t running_msec;
1185 uint32_t stoppos, triggerpos;
1187 /* Check if the selected sampling duration passed. */
1188 gettimeofday(&tv, 0);
1189 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1190 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1191 if (running_msec >= devc->limit_msec)
1192 return download_capture(sdi);
1194 /* Get the position in DRAM to which the FPGA is writing now. */
1195 sigma_read_pos(&stoppos, &triggerpos, devc);
1196 /* Test if DRAM is full and if so, download the data. */
1197 if ((stoppos >> 9) == 32767)
1198 return download_capture(sdi);
1203 static int receive_data(int fd, int revents, void *cb_data)
1205 struct sr_dev_inst *sdi;
1206 struct dev_context *devc;
1214 if (devc->state.state == SIGMA_IDLE)
1217 if (devc->state.state == SIGMA_CAPTURE)
1218 return sigma_capture_mode(sdi);
1223 /* Build a LUT entry used by the trigger functions. */
1224 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1228 /* For each quad channel. */
1229 for (i = 0; i < 4; ++i) {
1232 /* For each bit in LUT. */
1233 for (j = 0; j < 16; ++j)
1235 /* For each channel in quad. */
1236 for (k = 0; k < 4; ++k) {
1237 bit = 1 << (i * 4 + k);
1239 /* Set bit in entry */
1241 ((!(value & bit)) !=
1243 entry[i] &= ~(1 << j);
1248 /* Add a logical function to LUT mask. */
1249 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1250 int index, int neg, uint16_t *mask)
1253 int x[2][2], tmp, a, b, aset, bset, rset;
1255 memset(x, 0, 4 * sizeof(int));
1257 /* Trigger detect condition. */
1287 case OP_NOTRISEFALL:
1293 /* Transpose if neg is set. */
1295 for (i = 0; i < 2; ++i) {
1296 for (j = 0; j < 2; ++j) {
1298 x[i][j] = x[1-i][1-j];
1304 /* Update mask with function. */
1305 for (i = 0; i < 16; ++i) {
1306 a = (i >> (2 * index + 0)) & 1;
1307 b = (i >> (2 * index + 1)) & 1;
1309 aset = (*mask >> i) & 1;
1312 if (func == FUNC_AND || func == FUNC_NAND)
1314 else if (func == FUNC_OR || func == FUNC_NOR)
1316 else if (func == FUNC_XOR || func == FUNC_NXOR)
1319 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1330 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1331 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1332 * set at any time, but a full mask and value can be set (0/1).
1334 static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1337 uint16_t masks[2] = { 0, 0 };
1339 memset(lut, 0, sizeof(struct triggerlut));
1341 /* Contant for simple triggers. */
1344 /* Value/mask trigger support. */
1345 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1348 /* Rise/fall trigger support. */
1349 for (i = 0, j = 0; i < 16; ++i) {
1350 if (devc->trigger.risingmask & (1 << i) ||
1351 devc->trigger.fallingmask & (1 << i))
1352 masks[j++] = 1 << i;
1355 build_lut_entry(masks[0], masks[0], lut->m0d);
1356 build_lut_entry(masks[1], masks[1], lut->m1d);
1358 /* Add glue logic */
1359 if (masks[0] || masks[1]) {
1360 /* Transition trigger. */
1361 if (masks[0] & devc->trigger.risingmask)
1362 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1363 if (masks[0] & devc->trigger.fallingmask)
1364 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1365 if (masks[1] & devc->trigger.risingmask)
1366 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1367 if (masks[1] & devc->trigger.fallingmask)
1368 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1370 /* Only value/mask trigger. */
1374 /* Triggertype: event. */
1375 lut->params.selres = 3;
1380 static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
1382 struct dev_context *devc;
1383 struct clockselect_50 clockselect;
1384 int frac, triggerpin, ret;
1385 uint8_t triggerselect = 0;
1386 struct triggerinout triggerinout_conf;
1387 struct triggerlut lut;
1389 if (sdi->status != SR_ST_ACTIVE)
1390 return SR_ERR_DEV_CLOSED;
1394 if (configure_channels(sdi) != SR_OK) {
1395 sr_err("Failed to configure channels.");
1399 /* If the samplerate has not been set, default to 200 kHz. */
1400 if (devc->cur_firmware == -1) {
1401 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1405 /* Enter trigger programming mode. */
1406 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1408 /* 100 and 200 MHz mode. */
1409 if (devc->cur_samplerate >= SR_MHZ(100)) {
1410 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1412 /* Find which pin to trigger on from mask. */
1413 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1414 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1418 /* Set trigger pin and light LED on trigger. */
1419 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1421 /* Default rising edge. */
1422 if (devc->trigger.fallingmask)
1423 triggerselect |= 1 << 3;
1425 /* All other modes. */
1426 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1427 build_basic_trigger(&lut, devc);
1429 sigma_write_trigger_lut(&lut, devc);
1431 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1434 /* Setup trigger in and out pins to default values. */
1435 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1436 triggerinout_conf.trgout_bytrigger = 1;
1437 triggerinout_conf.trgout_enable = 1;
1439 sigma_write_register(WRITE_TRIGGER_OPTION,
1440 (uint8_t *) &triggerinout_conf,
1441 sizeof(struct triggerinout), devc);
1443 /* Go back to normal mode. */
1444 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1446 /* Set clock select register. */
1447 if (devc->cur_samplerate == SR_MHZ(200))
1448 /* Enable 4 channels. */
1449 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1450 else if (devc->cur_samplerate == SR_MHZ(100))
1451 /* Enable 8 channels. */
1452 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1455 * 50 MHz mode (or fraction thereof). Any fraction down to
1456 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1458 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1460 clockselect.async = 0;
1461 clockselect.fraction = frac;
1462 clockselect.disabled_channels = 0;
1464 sigma_write_register(WRITE_CLOCK_SELECT,
1465 (uint8_t *) &clockselect,
1466 sizeof(clockselect), devc);
1469 /* Setup maximum post trigger time. */
1470 sigma_set_register(WRITE_POST_TRIGGER,
1471 (devc->capture_ratio * 255) / 100, devc);
1473 /* Start acqusition. */
1474 gettimeofday(&devc->start_tv, 0);
1475 sigma_set_register(WRITE_MODE, 0x0d, devc);
1477 devc->cb_data = cb_data;
1479 /* Send header packet to the session bus. */
1480 std_session_send_df_header(cb_data, LOG_PREFIX);
1482 /* Add capture source. */
1483 sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
1485 devc->state.state = SIGMA_CAPTURE;
1490 static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1492 struct dev_context *devc;
1497 devc->state.state = SIGMA_IDLE;
1499 sr_source_remove(0);
1504 SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1505 .name = "asix-sigma",
1506 .longname = "ASIX SIGMA/SIGMA2",
1511 .dev_list = dev_list,
1512 .dev_clear = dev_clear,
1513 .config_get = config_get,
1514 .config_set = config_set,
1515 .config_list = config_list,
1516 .dev_open = dev_open,
1517 .dev_close = dev_close,
1518 .dev_acquisition_start = dev_acquisition_start,
1519 .dev_acquisition_stop = dev_acquisition_stop,