2 * This file is part of the sigrok project.
4 * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX SIGMA Logic Analyzer Driver
27 #include <glib/gstdio.h>
32 #include "sigrok-internal.h"
33 #include "asix-sigma.h"
35 #define USB_VENDOR 0xa600
36 #define USB_PRODUCT 0xa000
37 #define USB_DESCRIPTION "ASIX SIGMA"
38 #define USB_VENDOR_NAME "ASIX"
39 #define USB_MODEL_NAME "SIGMA"
40 #define USB_MODEL_VERSION ""
41 #define TRIGGER_TYPES "rf10"
44 static GSList *dev_insts = NULL;
46 static uint64_t supported_samplerates[] = {
61 * Probe numbers seem to go from 1-16, according to this image:
62 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
63 * (the cable has two additional GND pins, and a TI and TO pin)
65 static const char *probe_names[NUM_PROBES + 1] = {
85 static struct sr_samplerates samplerates = {
89 supported_samplerates,
92 static int hwcaps[] = {
93 SR_HWCAP_LOGIC_ANALYZER,
95 SR_HWCAP_CAPTURE_RATIO,
102 /* Force the FPGA to reboot. */
103 static uint8_t suicide[] = {
104 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
107 /* Prepare to upload firmware (FPGA specific). */
108 static uint8_t init[] = {
109 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
112 /* Initialize the logic analyzer mode. */
113 static uint8_t logic_mode_start[] = {
114 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
115 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
118 static const char *firmware_files[] = {
119 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
120 "asix-sigma-100.fw", /* 100 MHz */
121 "asix-sigma-200.fw", /* 200 MHz */
122 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
123 "asix-sigma-phasor.fw", /* Frequency counter */
126 static int hw_dev_acquisition_stop(int dev_index, void *cb_data);
128 static int sigma_read(void *buf, size_t size, struct context *ctx)
132 ret = ftdi_read_data(&ctx->ftdic, (unsigned char *)buf, size);
134 sr_err("sigma: ftdi_read_data failed: %s",
135 ftdi_get_error_string(&ctx->ftdic));
141 static int sigma_write(void *buf, size_t size, struct context *ctx)
145 ret = ftdi_write_data(&ctx->ftdic, (unsigned char *)buf, size);
147 sr_err("sigma: ftdi_write_data failed: %s",
148 ftdi_get_error_string(&ctx->ftdic));
149 } else if ((size_t) ret != size) {
150 sr_err("sigma: ftdi_write_data did not complete write\n");
156 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
160 uint8_t buf[len + 2];
163 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
164 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
166 for (i = 0; i < len; ++i) {
167 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
168 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
171 return sigma_write(buf, idx, ctx);
174 static int sigma_set_register(uint8_t reg, uint8_t value, struct context *ctx)
176 return sigma_write_register(reg, &value, 1, ctx);
179 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
184 buf[0] = REG_ADDR_LOW | (reg & 0xf);
185 buf[1] = REG_ADDR_HIGH | (reg >> 4);
186 buf[2] = REG_READ_ADDR;
188 sigma_write(buf, sizeof(buf), ctx);
190 return sigma_read(data, len, ctx);
193 static uint8_t sigma_get_register(uint8_t reg, struct context *ctx)
197 if (1 != sigma_read_register(reg, &value, 1, ctx)) {
198 sr_err("sigma: sigma_get_register: 1 byte expected");
205 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
209 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
211 REG_READ_ADDR | NEXT_REG,
212 REG_READ_ADDR | NEXT_REG,
213 REG_READ_ADDR | NEXT_REG,
214 REG_READ_ADDR | NEXT_REG,
215 REG_READ_ADDR | NEXT_REG,
216 REG_READ_ADDR | NEXT_REG,
220 sigma_write(buf, sizeof(buf), ctx);
222 sigma_read(result, sizeof(result), ctx);
224 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
225 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
227 /* Not really sure why this must be done, but according to spec. */
228 if ((--*stoppos & 0x1ff) == 0x1ff)
231 if ((*--triggerpos & 0x1ff) == 0x1ff)
237 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
238 uint8_t *data, struct context *ctx)
244 /* Send the startchunk. Index start with 1. */
245 buf[0] = startchunk >> 8;
246 buf[1] = startchunk & 0xff;
247 sigma_write_register(WRITE_MEMROW, buf, 2, ctx);
250 buf[idx++] = REG_DRAM_BLOCK;
251 buf[idx++] = REG_DRAM_WAIT_ACK;
253 for (i = 0; i < numchunks; ++i) {
254 /* Alternate bit to copy from DRAM to cache. */
255 if (i != (numchunks - 1))
256 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
258 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
260 if (i != (numchunks - 1))
261 buf[idx++] = REG_DRAM_WAIT_ACK;
264 sigma_write(buf, idx, ctx);
266 return sigma_read(data, numchunks * CHUNK_SIZE, ctx);
269 /* Upload trigger look-up tables to Sigma. */
270 static int sigma_write_trigger_lut(struct triggerlut *lut, struct context *ctx)
276 /* Transpose the table and send to Sigma. */
277 for (i = 0; i < 16; ++i) {
282 if (lut->m2d[0] & bit)
284 if (lut->m2d[1] & bit)
286 if (lut->m2d[2] & bit)
288 if (lut->m2d[3] & bit)
298 if (lut->m0d[0] & bit)
300 if (lut->m0d[1] & bit)
302 if (lut->m0d[2] & bit)
304 if (lut->m0d[3] & bit)
307 if (lut->m1d[0] & bit)
309 if (lut->m1d[1] & bit)
311 if (lut->m1d[2] & bit)
313 if (lut->m1d[3] & bit)
316 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
318 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, ctx);
321 /* Send the parameters */
322 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
323 sizeof(lut->params), ctx);
328 /* Generate the bitbang stream for programming the FPGA. */
329 static int bin2bitbang(const char *filename,
330 unsigned char **buf, size_t *buf_size)
334 unsigned long offset = 0;
336 uint8_t *compressed_buf, *firmware;
337 uLongf csize, fwsize;
338 const int buffer_size = 65536;
341 uint32_t imm = 0x3f6df2ab;
343 f = g_fopen(filename, "rb");
345 sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename);
349 if (-1 == fseek(f, 0, SEEK_END)) {
350 sr_err("sigma: fseek on %s failed", filename);
355 file_size = ftell(f);
357 fseek(f, 0, SEEK_SET);
359 if (!(compressed_buf = g_try_malloc(file_size))) {
360 sr_err("sigma: %s: compressed_buf malloc failed", __func__);
362 return SR_ERR_MALLOC;
365 if (!(firmware = g_try_malloc(buffer_size))) {
366 sr_err("sigma: %s: firmware malloc failed", __func__);
368 g_free(compressed_buf);
369 return SR_ERR_MALLOC;
373 while ((c = getc(f)) != EOF) {
374 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
375 compressed_buf[csize++] = c ^ imm;
379 fwsize = buffer_size;
380 ret = uncompress(firmware, &fwsize, compressed_buf, csize);
382 g_free(compressed_buf);
384 sr_err("sigma: Could not unpack Sigma firmware. "
385 "(Error %d)\n", ret);
389 g_free(compressed_buf);
391 *buf_size = fwsize * 2 * 8;
393 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
395 sr_err("sigma: %s: buf/p malloc failed", __func__);
396 g_free(compressed_buf);
398 return SR_ERR_MALLOC;
401 for (i = 0; i < fwsize; ++i) {
402 for (bit = 7; bit >= 0; --bit) {
403 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
404 p[offset++] = v | 0x01;
411 if (offset != *buf_size) {
413 sr_err("sigma: Error reading firmware %s "
414 "offset=%ld, file_size=%ld, buf_size=%zd\n",
415 filename, offset, file_size, *buf_size);
423 static int hw_init(const char *devinfo)
425 struct sr_dev_inst *sdi;
428 /* Avoid compiler warnings. */
431 if (!(ctx = g_try_malloc(sizeof(struct context)))) {
432 sr_err("sigma: %s: ctx malloc failed", __func__);
433 return 0; /* FIXME: Should be SR_ERR_MALLOC. */
436 ftdi_init(&ctx->ftdic);
438 /* Look for SIGMAs. */
439 if (ftdi_usb_open_desc(&ctx->ftdic, USB_VENDOR, USB_PRODUCT,
440 USB_DESCRIPTION, NULL) < 0)
443 ctx->cur_samplerate = 0;
446 ctx->cur_firmware = -1;
448 ctx->samples_per_event = 0;
449 ctx->capture_ratio = 50;
450 ctx->use_triggers = 0;
452 /* Register SIGMA device. */
453 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
454 USB_MODEL_NAME, USB_MODEL_VERSION))) {
455 sr_err("sigma: %s: sdi was NULL", __func__);
461 dev_insts = g_slist_append(dev_insts, sdi);
463 /* We will open the device again when we need it. */
464 ftdi_usb_close(&ctx->ftdic);
473 static int upload_firmware(int firmware_idx, struct context *ctx)
479 unsigned char result[32];
480 char firmware_path[128];
482 /* Make sure it's an ASIX SIGMA. */
483 if ((ret = ftdi_usb_open_desc(&ctx->ftdic,
484 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
485 sr_err("sigma: ftdi_usb_open failed: %s",
486 ftdi_get_error_string(&ctx->ftdic));
490 if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
491 sr_err("sigma: ftdi_set_bitmode failed: %s",
492 ftdi_get_error_string(&ctx->ftdic));
496 /* Four times the speed of sigmalogan - Works well. */
497 if ((ret = ftdi_set_baudrate(&ctx->ftdic, 750000)) < 0) {
498 sr_err("sigma: ftdi_set_baudrate failed: %s",
499 ftdi_get_error_string(&ctx->ftdic));
503 /* Force the FPGA to reboot. */
504 sigma_write(suicide, sizeof(suicide), ctx);
505 sigma_write(suicide, sizeof(suicide), ctx);
506 sigma_write(suicide, sizeof(suicide), ctx);
507 sigma_write(suicide, sizeof(suicide), ctx);
509 /* Prepare to upload firmware (FPGA specific). */
510 sigma_write(init, sizeof(init), ctx);
512 ftdi_usb_purge_buffers(&ctx->ftdic);
514 /* Wait until the FPGA asserts INIT_B. */
516 ret = sigma_read(result, 1, ctx);
517 if (result[0] & 0x20)
521 /* Prepare firmware. */
522 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
523 firmware_files[firmware_idx]);
525 if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
526 sr_err("sigma: An error occured while reading the firmware: %s",
531 /* Upload firmare. */
532 sigma_write(buf, buf_size, ctx);
536 if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0x00, BITMODE_RESET)) < 0) {
537 sr_err("sigma: ftdi_set_bitmode failed: %s",
538 ftdi_get_error_string(&ctx->ftdic));
542 ftdi_usb_purge_buffers(&ctx->ftdic);
544 /* Discard garbage. */
545 while (1 == sigma_read(&pins, 1, ctx))
548 /* Initialize the logic analyzer mode. */
549 sigma_write(logic_mode_start, sizeof(logic_mode_start), ctx);
551 /* Expect a 3 byte reply. */
552 ret = sigma_read(result, 3, ctx);
554 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
555 sr_err("sigma: Configuration failed. Invalid reply received.");
559 ctx->cur_firmware = firmware_idx;
564 static int hw_dev_open(int dev_index)
566 struct sr_dev_inst *sdi;
570 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
575 /* Make sure it's an ASIX SIGMA. */
576 if ((ret = ftdi_usb_open_desc(&ctx->ftdic,
577 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
579 sr_err("sigma: ftdi_usb_open failed: %s",
580 ftdi_get_error_string(&ctx->ftdic));
585 sdi->status = SR_ST_ACTIVE;
590 static int set_samplerate(struct sr_dev_inst *sdi, uint64_t samplerate)
593 struct context *ctx = sdi->priv;
595 for (i = 0; supported_samplerates[i]; i++) {
596 if (supported_samplerates[i] == samplerate)
599 if (supported_samplerates[i] == 0)
600 return SR_ERR_SAMPLERATE;
602 if (samplerate <= SR_MHZ(50)) {
603 ret = upload_firmware(0, ctx);
604 ctx->num_probes = 16;
606 if (samplerate == SR_MHZ(100)) {
607 ret = upload_firmware(1, ctx);
610 else if (samplerate == SR_MHZ(200)) {
611 ret = upload_firmware(2, ctx);
615 ctx->cur_samplerate = samplerate;
616 ctx->period_ps = 1000000000000 / samplerate;
617 ctx->samples_per_event = 16 / ctx->num_probes;
618 ctx->state.state = SIGMA_IDLE;
620 sr_info("sigma: Firmware uploaded");
626 * In 100 and 200 MHz mode, only a single pin rising/falling can be
627 * set as trigger. In other modes, two rising/falling triggers can be set,
628 * in addition to value/mask trigger for any number of probes.
630 * The Sigma supports complex triggers using boolean expressions, but this
631 * has not been implemented yet.
633 static int configure_probes(struct sr_dev_inst *sdi, GSList *probes)
635 struct context *ctx = sdi->priv;
636 struct sr_probe *probe;
641 memset(&ctx->trigger, 0, sizeof(struct sigma_trigger));
643 for (l = probes; l; l = l->next) {
644 probe = (struct sr_probe *)l->data;
645 probebit = 1 << (probe->index - 1);
647 if (!probe->enabled || !probe->trigger)
650 if (ctx->cur_samplerate >= SR_MHZ(100)) {
651 /* Fast trigger support. */
653 sr_err("sigma: ASIX SIGMA only supports a single "
654 "pin trigger in 100 and 200MHz mode.");
657 if (probe->trigger[0] == 'f')
658 ctx->trigger.fallingmask |= probebit;
659 else if (probe->trigger[0] == 'r')
660 ctx->trigger.risingmask |= probebit;
662 sr_err("sigma: ASIX SIGMA only supports "
663 "rising/falling trigger in 100 "
670 /* Simple trigger support (event). */
671 if (probe->trigger[0] == '1') {
672 ctx->trigger.simplevalue |= probebit;
673 ctx->trigger.simplemask |= probebit;
675 else if (probe->trigger[0] == '0') {
676 ctx->trigger.simplevalue &= ~probebit;
677 ctx->trigger.simplemask |= probebit;
679 else if (probe->trigger[0] == 'f') {
680 ctx->trigger.fallingmask |= probebit;
683 else if (probe->trigger[0] == 'r') {
684 ctx->trigger.risingmask |= probebit;
689 * Actually, Sigma supports 2 rising/falling triggers,
690 * but they are ORed and the current trigger syntax
691 * does not permit ORed triggers.
693 if (trigger_set > 1) {
694 sr_err("sigma: ASIX SIGMA only supports 1 "
695 "rising/falling triggers.");
701 ctx->use_triggers = 1;
707 static int hw_dev_close(int dev_index)
709 struct sr_dev_inst *sdi;
712 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) {
713 sr_err("sigma: %s: sdi was NULL", __func__);
717 if (!(ctx = sdi->priv)) {
718 sr_err("sigma: %s: sdi->priv was NULL", __func__);
723 if (sdi->status == SR_ST_ACTIVE)
724 ftdi_usb_close(&ctx->ftdic);
726 sdi->status = SR_ST_INACTIVE;
731 static int hw_cleanup(void)
734 struct sr_dev_inst *sdi;
737 /* Properly close all devices. */
738 for (l = dev_insts; l; l = l->next) {
739 if (!(sdi = l->data)) {
740 /* Log error, but continue cleaning up the rest. */
741 sr_err("sigma: %s: sdi was NULL, continuing", __func__);
745 sr_dev_inst_free(sdi);
747 g_slist_free(dev_insts);
753 static void *hw_dev_info_get(int dev_index, int dev_info_id)
755 struct sr_dev_inst *sdi;
759 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) {
760 sr_err("sigma: %s: sdi was NULL", __func__);
766 switch (dev_info_id) {
770 case SR_DI_NUM_PROBES:
771 info = GINT_TO_POINTER(NUM_PROBES);
773 case SR_DI_PROBE_NAMES:
776 case SR_DI_SAMPLERATES:
779 case SR_DI_TRIGGER_TYPES:
780 info = (char *)TRIGGER_TYPES;
782 case SR_DI_CUR_SAMPLERATE:
783 info = &ctx->cur_samplerate;
790 static int hw_dev_status_get(int dev_index)
792 struct sr_dev_inst *sdi;
794 sdi = sr_dev_inst_get(dev_insts, dev_index);
798 return SR_ST_NOT_FOUND;
801 static int *hw_hwcap_get_all(void)
806 static int hw_dev_config_set(int dev_index, int hwcap, void *value)
808 struct sr_dev_inst *sdi;
812 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
817 if (hwcap == SR_HWCAP_SAMPLERATE) {
818 ret = set_samplerate(sdi, *(uint64_t *)value);
819 } else if (hwcap == SR_HWCAP_PROBECONFIG) {
820 ret = configure_probes(sdi, value);
821 } else if (hwcap == SR_HWCAP_LIMIT_MSEC) {
822 ctx->limit_msec = *(uint64_t *)value;
823 if (ctx->limit_msec > 0)
827 } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) {
828 ctx->capture_ratio = *(uint64_t *)value;
829 if (ctx->capture_ratio < 0 || ctx->capture_ratio > 100)
840 /* Software trigger to determine exact trigger position. */
841 static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
842 struct sigma_trigger *t)
846 for (i = 0; i < 8; ++i) {
848 last_sample = samples[i-1];
850 /* Simple triggers. */
851 if ((samples[i] & t->simplemask) != t->simplevalue)
855 if ((last_sample & t->risingmask) != 0 || (samples[i] &
856 t->risingmask) != t->risingmask)
860 if ((last_sample & t->fallingmask) != t->fallingmask ||
861 (samples[i] & t->fallingmask) != 0)
867 /* If we did not match, return original trigger pos. */
872 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
873 * Each event is 20ns apart, and can contain multiple samples.
875 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
876 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
877 * For 50 MHz and below, events contain one sample for each channel,
878 * spread 20 ns apart.
880 static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
881 uint16_t *lastsample, int triggerpos,
882 uint16_t limit_chunk, void *cb_data)
884 struct sr_dev_inst *sdi = cb_data;
885 struct context *ctx = sdi->priv;
887 uint16_t samples[65536 * ctx->samples_per_event];
888 struct sr_datafeed_packet packet;
889 struct sr_datafeed_logic logic;
890 int i, j, k, l, numpad, tosend;
891 size_t n = 0, sent = 0;
892 int clustersize = EVENTS_PER_CLUSTER * ctx->samples_per_event;
897 /* Check if trigger is in this chunk. */
898 if (triggerpos != -1) {
899 if (ctx->cur_samplerate <= SR_MHZ(50))
900 triggerpos -= EVENTS_PER_CLUSTER - 1;
905 /* Find in which cluster the trigger occured. */
906 triggerts = triggerpos / 7;
910 for (i = 0; i < 64; ++i) {
911 ts = *(uint16_t *) &buf[i * 16];
912 tsdiff = ts - *lastts;
915 /* Decode partial chunk. */
916 if (limit_chunk && ts > limit_chunk)
919 /* Pad last sample up to current point. */
920 numpad = tsdiff * ctx->samples_per_event - clustersize;
922 for (j = 0; j < numpad; ++j)
923 samples[j] = *lastsample;
928 /* Send samples between previous and this timestamp to sigrok. */
931 tosend = MIN(2048, n - sent);
933 packet.type = SR_DF_LOGIC;
934 packet.payload = &logic;
935 logic.length = tosend * sizeof(uint16_t);
937 logic.data = samples + sent;
938 sr_session_send(ctx->session_dev_id, &packet);
944 event = (uint16_t *) &buf[i * 16 + 2];
947 /* For each event in cluster. */
948 for (j = 0; j < 7; ++j) {
950 /* For each sample in event. */
951 for (k = 0; k < ctx->samples_per_event; ++k) {
954 /* For each probe. */
955 for (l = 0; l < ctx->num_probes; ++l)
956 cur_sample |= (!!(event[j] & (1 << (l *
957 ctx->samples_per_event + k)))) << l;
959 samples[n++] = cur_sample;
963 /* Send data up to trigger point (if triggered). */
965 if (i == triggerts) {
967 * Trigger is not always accurate to sample because of
968 * pipeline delay. However, it always triggers before
969 * the actual event. We therefore look at the next
970 * samples to pinpoint the exact position of the trigger.
972 tosend = get_trigger_offset(samples, *lastsample,
976 packet.type = SR_DF_LOGIC;
977 packet.payload = &logic;
978 logic.length = tosend * sizeof(uint16_t);
980 logic.data = samples;
981 sr_session_send(ctx->session_dev_id, &packet);
986 /* Only send trigger if explicitly enabled. */
987 if (ctx->use_triggers) {
988 packet.type = SR_DF_TRIGGER;
989 sr_session_send(ctx->session_dev_id, &packet);
993 /* Send rest of the chunk to sigrok. */
997 packet.type = SR_DF_LOGIC;
998 packet.payload = &logic;
999 logic.length = tosend * sizeof(uint16_t);
1001 logic.data = samples + sent;
1002 sr_session_send(ctx->session_dev_id, &packet);
1005 *lastsample = samples[n - 1];
1011 static int receive_data(int fd, int revents, void *cb_data)
1013 struct sr_dev_inst *sdi = cb_data;
1014 struct context *ctx = sdi->priv;
1015 struct sr_datafeed_packet packet;
1016 const int chunks_per_read = 32;
1017 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1018 int bufsz, numchunks, i, newchunks;
1019 uint64_t running_msec;
1022 /* Avoid compiler warnings. */
1026 numchunks = (ctx->state.stoppos + 511) / 512;
1028 if (ctx->state.state == SIGMA_IDLE)
1031 if (ctx->state.state == SIGMA_CAPTURE) {
1032 /* Check if the timer has expired, or memory is full. */
1033 gettimeofday(&tv, 0);
1034 running_msec = (tv.tv_sec - ctx->start_tv.tv_sec) * 1000 +
1035 (tv.tv_usec - ctx->start_tv.tv_usec) / 1000;
1037 if (running_msec < ctx->limit_msec && numchunks < 32767)
1040 hw_dev_acquisition_stop(sdi->index, sdi);
1043 } else if (ctx->state.state == SIGMA_DOWNLOAD) {
1044 if (ctx->state.chunks_downloaded >= numchunks) {
1045 /* End of samples. */
1046 packet.type = SR_DF_END;
1047 sr_session_send(ctx->session_dev_id, &packet);
1049 ctx->state.state = SIGMA_IDLE;
1054 newchunks = MIN(chunks_per_read,
1055 numchunks - ctx->state.chunks_downloaded);
1057 sr_info("sigma: Downloading sample data: %.0f %%",
1058 100.0 * ctx->state.chunks_downloaded / numchunks);
1060 bufsz = sigma_read_dram(ctx->state.chunks_downloaded,
1061 newchunks, buf, ctx);
1062 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1065 /* Find first ts. */
1066 if (ctx->state.chunks_downloaded == 0) {
1067 ctx->state.lastts = *(uint16_t *) buf - 1;
1068 ctx->state.lastsample = 0;
1071 /* Decode chunks and send them to sigrok. */
1072 for (i = 0; i < newchunks; ++i) {
1073 int limit_chunk = 0;
1075 /* The last chunk may potentially be only in part. */
1076 if (ctx->state.chunks_downloaded == numchunks - 1) {
1077 /* Find the last valid timestamp */
1078 limit_chunk = ctx->state.stoppos % 512 + ctx->state.lastts;
1081 if (ctx->state.chunks_downloaded + i == ctx->state.triggerchunk)
1082 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1084 &ctx->state.lastsample,
1085 ctx->state.triggerpos & 0x1ff,
1088 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1090 &ctx->state.lastsample,
1091 -1, limit_chunk, sdi);
1093 ++ctx->state.chunks_downloaded;
1100 /* Build a LUT entry used by the trigger functions. */
1101 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1105 /* For each quad probe. */
1106 for (i = 0; i < 4; ++i) {
1109 /* For each bit in LUT. */
1110 for (j = 0; j < 16; ++j)
1112 /* For each probe in quad. */
1113 for (k = 0; k < 4; ++k) {
1114 bit = 1 << (i * 4 + k);
1116 /* Set bit in entry */
1118 ((!(value & bit)) !=
1120 entry[i] &= ~(1 << j);
1125 /* Add a logical function to LUT mask. */
1126 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1127 int index, int neg, uint16_t *mask)
1130 int x[2][2], tmp, a, b, aset, bset, rset;
1132 memset(x, 0, 4 * sizeof(int));
1134 /* Trigger detect condition. */
1164 case OP_NOTRISEFALL:
1170 /* Transpose if neg is set. */
1172 for (i = 0; i < 2; ++i) {
1173 for (j = 0; j < 2; ++j) {
1175 x[i][j] = x[1-i][1-j];
1181 /* Update mask with function. */
1182 for (i = 0; i < 16; ++i) {
1183 a = (i >> (2 * index + 0)) & 1;
1184 b = (i >> (2 * index + 1)) & 1;
1186 aset = (*mask >> i) & 1;
1189 if (func == FUNC_AND || func == FUNC_NAND)
1191 else if (func == FUNC_OR || func == FUNC_NOR)
1193 else if (func == FUNC_XOR || func == FUNC_NXOR)
1196 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1207 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1208 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1209 * set at any time, but a full mask and value can be set (0/1).
1211 static int build_basic_trigger(struct triggerlut *lut, struct context *ctx)
1214 uint16_t masks[2] = { 0, 0 };
1216 memset(lut, 0, sizeof(struct triggerlut));
1218 /* Contant for simple triggers. */
1221 /* Value/mask trigger support. */
1222 build_lut_entry(ctx->trigger.simplevalue, ctx->trigger.simplemask,
1225 /* Rise/fall trigger support. */
1226 for (i = 0, j = 0; i < 16; ++i) {
1227 if (ctx->trigger.risingmask & (1 << i) ||
1228 ctx->trigger.fallingmask & (1 << i))
1229 masks[j++] = 1 << i;
1232 build_lut_entry(masks[0], masks[0], lut->m0d);
1233 build_lut_entry(masks[1], masks[1], lut->m1d);
1235 /* Add glue logic */
1236 if (masks[0] || masks[1]) {
1237 /* Transition trigger. */
1238 if (masks[0] & ctx->trigger.risingmask)
1239 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1240 if (masks[0] & ctx->trigger.fallingmask)
1241 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1242 if (masks[1] & ctx->trigger.risingmask)
1243 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1244 if (masks[1] & ctx->trigger.fallingmask)
1245 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1247 /* Only value/mask trigger. */
1251 /* Triggertype: event. */
1252 lut->params.selres = 3;
1257 static int hw_dev_acquisition_start(int dev_index, void *cb_data)
1259 struct sr_dev_inst *sdi;
1260 struct context *ctx;
1261 struct sr_datafeed_packet packet;
1262 struct sr_datafeed_header header;
1263 struct clockselect_50 clockselect;
1264 int frac, triggerpin, ret;
1265 uint8_t triggerselect;
1266 struct triggerinout triggerinout_conf;
1267 struct triggerlut lut;
1269 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
1274 /* If the samplerate has not been set, default to 200 kHz. */
1275 if (ctx->cur_firmware == -1) {
1276 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1280 /* Enter trigger programming mode. */
1281 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, ctx);
1283 /* 100 and 200 MHz mode. */
1284 if (ctx->cur_samplerate >= SR_MHZ(100)) {
1285 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, ctx);
1287 /* Find which pin to trigger on from mask. */
1288 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1289 if ((ctx->trigger.risingmask | ctx->trigger.fallingmask) &
1293 /* Set trigger pin and light LED on trigger. */
1294 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1296 /* Default rising edge. */
1297 if (ctx->trigger.fallingmask)
1298 triggerselect |= 1 << 3;
1300 /* All other modes. */
1301 } else if (ctx->cur_samplerate <= SR_MHZ(50)) {
1302 build_basic_trigger(&lut, ctx);
1304 sigma_write_trigger_lut(&lut, ctx);
1306 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1309 /* Setup trigger in and out pins to default values. */
1310 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1311 triggerinout_conf.trgout_bytrigger = 1;
1312 triggerinout_conf.trgout_enable = 1;
1314 sigma_write_register(WRITE_TRIGGER_OPTION,
1315 (uint8_t *) &triggerinout_conf,
1316 sizeof(struct triggerinout), ctx);
1318 /* Go back to normal mode. */
1319 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, ctx);
1321 /* Set clock select register. */
1322 if (ctx->cur_samplerate == SR_MHZ(200))
1323 /* Enable 4 probes. */
1324 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, ctx);
1325 else if (ctx->cur_samplerate == SR_MHZ(100))
1326 /* Enable 8 probes. */
1327 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, ctx);
1330 * 50 MHz mode (or fraction thereof). Any fraction down to
1331 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1333 frac = SR_MHZ(50) / ctx->cur_samplerate - 1;
1335 clockselect.async = 0;
1336 clockselect.fraction = frac;
1337 clockselect.disabled_probes = 0;
1339 sigma_write_register(WRITE_CLOCK_SELECT,
1340 (uint8_t *) &clockselect,
1341 sizeof(clockselect), ctx);
1344 /* Setup maximum post trigger time. */
1345 sigma_set_register(WRITE_POST_TRIGGER,
1346 (ctx->capture_ratio * 255) / 100, ctx);
1348 /* Start acqusition. */
1349 gettimeofday(&ctx->start_tv, 0);
1350 sigma_set_register(WRITE_MODE, 0x0d, ctx);
1352 ctx->session_dev_id = cb_data;
1354 /* Send header packet to the session bus. */
1355 packet.type = SR_DF_HEADER;
1356 packet.payload = &header;
1357 header.feed_version = 1;
1358 gettimeofday(&header.starttime, NULL);
1359 header.samplerate = ctx->cur_samplerate;
1360 header.num_logic_probes = ctx->num_probes;
1361 sr_session_send(ctx->session_dev_id, &packet);
1363 /* Add capture source. */
1364 sr_source_add(0, G_IO_IN, 10, receive_data, sdi);
1366 ctx->state.state = SIGMA_CAPTURE;
1371 static int hw_dev_acquisition_stop(int dev_index, void *cb_data)
1373 struct sr_dev_inst *sdi;
1374 struct context *ctx;
1377 /* Avoid compiler warnings. */
1380 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) {
1381 sr_err("sigma: %s: sdi was NULL", __func__);
1385 if (!(ctx = sdi->priv)) {
1386 sr_err("sigma: %s: sdi->priv was NULL", __func__);
1390 /* Stop acquisition. */
1391 sigma_set_register(WRITE_MODE, 0x11, ctx);
1393 /* Set SDRAM Read Enable. */
1394 sigma_set_register(WRITE_MODE, 0x02, ctx);
1396 /* Get the current position. */
1397 sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx);
1399 /* Check if trigger has fired. */
1400 modestatus = sigma_get_register(READ_MODE, ctx);
1401 if (modestatus & 0x20)
1402 ctx->state.triggerchunk = ctx->state.triggerpos / 512;
1404 ctx->state.triggerchunk = -1;
1406 ctx->state.chunks_downloaded = 0;
1408 ctx->state.state = SIGMA_DOWNLOAD;
1413 SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1414 .name = "asix-sigma",
1415 .longname = "ASIX SIGMA",
1418 .cleanup = hw_cleanup,
1419 .dev_open = hw_dev_open,
1420 .dev_close = hw_dev_close,
1421 .dev_info_get = hw_dev_info_get,
1422 .dev_status_get = hw_dev_status_get,
1423 .hwcap_get_all = hw_hwcap_get_all,
1424 .dev_config_set = hw_dev_config_set,
1425 .dev_acquisition_start = hw_dev_acquisition_start,
1426 .dev_acquisition_stop = hw_dev_acquisition_stop,