2 * This file is part of the sigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
27 #include <glib/gstdio.h>
30 #include "libsigrok.h"
31 #include "libsigrok-internal.h"
32 #include "asix-sigma.h"
34 #define USB_VENDOR 0xa600
35 #define USB_PRODUCT 0xa000
36 #define USB_DESCRIPTION "ASIX SIGMA"
37 #define USB_VENDOR_NAME "ASIX"
38 #define USB_MODEL_NAME "SIGMA"
39 #define USB_MODEL_VERSION ""
40 #define TRIGGER_TYPES "rf10"
43 SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
44 static struct sr_dev_driver *adi = &asix_sigma_driver_info;
46 static const uint64_t supported_samplerates[] = {
61 * Probe numbers seem to go from 1-16, according to this image:
62 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
63 * (the cable has two additional GND pins, and a TI and TO pin)
65 static const char *probe_names[NUM_PROBES + 1] = {
85 static const struct sr_samplerates samplerates = {
89 supported_samplerates,
92 static const int hwcaps[] = {
93 SR_HWCAP_LOGIC_ANALYZER,
95 SR_HWCAP_CAPTURE_RATIO,
102 /* Force the FPGA to reboot. */
103 static uint8_t suicide[] = {
104 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
107 /* Prepare to upload firmware (FPGA specific). */
108 static uint8_t init[] = {
109 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
112 /* Initialize the logic analyzer mode. */
113 static uint8_t logic_mode_start[] = {
114 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
115 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
118 static const char *firmware_files[] = {
119 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
120 "asix-sigma-100.fw", /* 100 MHz */
121 "asix-sigma-200.fw", /* 200 MHz */
122 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
123 "asix-sigma-phasor.fw", /* Frequency counter */
126 static int hw_dev_acquisition_stop(const struct sr_dev_inst *sdi,
129 static int sigma_read(void *buf, size_t size, struct dev_context *devc)
133 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
135 sr_err("sigma: ftdi_read_data failed: %s",
136 ftdi_get_error_string(&devc->ftdic));
142 static int sigma_write(void *buf, size_t size, struct dev_context *devc)
146 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
148 sr_err("sigma: ftdi_write_data failed: %s",
149 ftdi_get_error_string(&devc->ftdic));
150 } else if ((size_t) ret != size) {
151 sr_err("sigma: ftdi_write_data did not complete write.");
157 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
158 struct dev_context *devc)
161 uint8_t buf[len + 2];
164 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
165 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
167 for (i = 0; i < len; ++i) {
168 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
169 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
172 return sigma_write(buf, idx, devc);
175 static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
177 return sigma_write_register(reg, &value, 1, devc);
180 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
181 struct dev_context *devc)
185 buf[0] = REG_ADDR_LOW | (reg & 0xf);
186 buf[1] = REG_ADDR_HIGH | (reg >> 4);
187 buf[2] = REG_READ_ADDR;
189 sigma_write(buf, sizeof(buf), devc);
191 return sigma_read(data, len, devc);
194 static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
198 if (1 != sigma_read_register(reg, &value, 1, devc)) {
199 sr_err("sigma: sigma_get_register: 1 byte expected");
206 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
207 struct dev_context *devc)
210 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
212 REG_READ_ADDR | NEXT_REG,
213 REG_READ_ADDR | NEXT_REG,
214 REG_READ_ADDR | NEXT_REG,
215 REG_READ_ADDR | NEXT_REG,
216 REG_READ_ADDR | NEXT_REG,
217 REG_READ_ADDR | NEXT_REG,
221 sigma_write(buf, sizeof(buf), devc);
223 sigma_read(result, sizeof(result), devc);
225 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
226 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
228 /* Not really sure why this must be done, but according to spec. */
229 if ((--*stoppos & 0x1ff) == 0x1ff)
232 if ((*--triggerpos & 0x1ff) == 0x1ff)
238 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
239 uint8_t *data, struct dev_context *devc)
245 /* Send the startchunk. Index start with 1. */
246 buf[0] = startchunk >> 8;
247 buf[1] = startchunk & 0xff;
248 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
251 buf[idx++] = REG_DRAM_BLOCK;
252 buf[idx++] = REG_DRAM_WAIT_ACK;
254 for (i = 0; i < numchunks; ++i) {
255 /* Alternate bit to copy from DRAM to cache. */
256 if (i != (numchunks - 1))
257 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
259 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
261 if (i != (numchunks - 1))
262 buf[idx++] = REG_DRAM_WAIT_ACK;
265 sigma_write(buf, idx, devc);
267 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
270 /* Upload trigger look-up tables to Sigma. */
271 static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
277 /* Transpose the table and send to Sigma. */
278 for (i = 0; i < 16; ++i) {
283 if (lut->m2d[0] & bit)
285 if (lut->m2d[1] & bit)
287 if (lut->m2d[2] & bit)
289 if (lut->m2d[3] & bit)
299 if (lut->m0d[0] & bit)
301 if (lut->m0d[1] & bit)
303 if (lut->m0d[2] & bit)
305 if (lut->m0d[3] & bit)
308 if (lut->m1d[0] & bit)
310 if (lut->m1d[1] & bit)
312 if (lut->m1d[2] & bit)
314 if (lut->m1d[3] & bit)
317 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
319 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
322 /* Send the parameters */
323 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
324 sizeof(lut->params), devc);
329 /* Generate the bitbang stream for programming the FPGA. */
330 static int bin2bitbang(const char *filename,
331 unsigned char **buf, size_t *buf_size)
334 unsigned long file_size;
335 unsigned long offset = 0;
338 unsigned long fwsize = 0;
339 const int buffer_size = 65536;
342 uint32_t imm = 0x3f6df2ab;
344 f = g_fopen(filename, "rb");
346 sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename);
350 if (-1 == fseek(f, 0, SEEK_END)) {
351 sr_err("sigma: fseek on %s failed", filename);
356 file_size = ftell(f);
358 fseek(f, 0, SEEK_SET);
360 if (!(firmware = g_try_malloc(buffer_size))) {
361 sr_err("sigma: %s: firmware malloc failed", __func__);
363 return SR_ERR_MALLOC;
366 while ((c = getc(f)) != EOF) {
367 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
368 firmware[fwsize++] = c ^ imm;
372 if(fwsize != file_size) {
373 sr_err("sigma: %s: Error reading firmware", filename);
379 *buf_size = fwsize * 2 * 8;
381 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
383 sr_err("sigma: %s: buf/p malloc failed", __func__);
385 return SR_ERR_MALLOC;
388 for (i = 0; i < fwsize; ++i) {
389 for (bit = 7; bit >= 0; --bit) {
390 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
391 p[offset++] = v | 0x01;
398 if (offset != *buf_size) {
400 sr_err("sigma: Error reading firmware %s "
401 "offset=%ld, file_size=%ld, buf_size=%zd.",
402 filename, offset, file_size, *buf_size);
410 static void clear_instances(void)
413 struct sr_dev_inst *sdi;
414 struct drv_context *drvc;
415 struct dev_context *devc;
419 /* Properly close all devices. */
420 for (l = drvc->instances; l; l = l->next) {
421 if (!(sdi = l->data)) {
422 /* Log error, but continue cleaning up the rest. */
423 sr_err("sigma: %s: sdi was NULL, continuing", __func__);
428 ftdi_free(&devc->ftdic);
431 sr_dev_inst_free(sdi);
433 g_slist_free(drvc->instances);
434 drvc->instances = NULL;
438 static int hw_init(void)
446 static GSList *hw_scan(GSList *options)
448 struct sr_dev_inst *sdi;
449 struct sr_probe *probe;
450 struct drv_context *drvc;
451 struct dev_context *devc;
453 struct ftdi_device_list *devlist;
463 if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
464 sr_err("sigma: %s: devc malloc failed", __func__);
468 ftdi_init(&devc->ftdic);
470 /* Look for SIGMAs. */
472 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
473 USB_VENDOR, USB_PRODUCT)) <= 0) {
475 sr_err("ftdi_usb_find_all(): %d", ret);
479 /* Make sure it's a version 1 or 2 SIGMA. */
480 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
481 serial_txt, sizeof(serial_txt));
482 sscanf(serial_txt, "%x", &serial);
484 if (serial < 0xa6010000 || serial > 0xa602ffff) {
485 sr_err("sigma: Only SIGMA and SIGMA2 are supported "
486 "in this version of sigrok.");
490 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
492 devc->cur_samplerate = 0;
494 devc->limit_msec = 0;
495 devc->cur_firmware = -1;
496 devc->num_probes = 0;
497 devc->samples_per_event = 0;
498 devc->capture_ratio = 50;
499 devc->use_triggers = 0;
501 /* Register SIGMA device. */
502 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
503 USB_MODEL_NAME, USB_MODEL_VERSION))) {
504 sr_err("sigma: %s: sdi was NULL", __func__);
509 for (i = 0; probe_names[i]; i++) {
510 if (!(probe = sr_probe_new(i, SR_PROBE_ANALOG, TRUE,
513 sdi->probes = g_slist_append(sdi->probes, probe);
516 devices = g_slist_append(devices, sdi);
517 drvc->instances = g_slist_append(drvc->instances, sdi);
520 /* We will open the device again when we need it. */
521 ftdi_list_free(&devlist);
526 ftdi_deinit(&devc->ftdic);
531 static int upload_firmware(int firmware_idx, struct dev_context *devc)
537 unsigned char result[32];
538 char firmware_path[128];
540 /* Make sure it's an ASIX SIGMA. */
541 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
542 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
543 sr_err("sigma: ftdi_usb_open failed: %s",
544 ftdi_get_error_string(&devc->ftdic));
548 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
549 sr_err("sigma: ftdi_set_bitmode failed: %s",
550 ftdi_get_error_string(&devc->ftdic));
554 /* Four times the speed of sigmalogan - Works well. */
555 if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) {
556 sr_err("sigma: ftdi_set_baudrate failed: %s",
557 ftdi_get_error_string(&devc->ftdic));
561 /* Force the FPGA to reboot. */
562 sigma_write(suicide, sizeof(suicide), devc);
563 sigma_write(suicide, sizeof(suicide), devc);
564 sigma_write(suicide, sizeof(suicide), devc);
565 sigma_write(suicide, sizeof(suicide), devc);
567 /* Prepare to upload firmware (FPGA specific). */
568 sigma_write(init, sizeof(init), devc);
570 ftdi_usb_purge_buffers(&devc->ftdic);
572 /* Wait until the FPGA asserts INIT_B. */
574 ret = sigma_read(result, 1, devc);
575 if (result[0] & 0x20)
579 /* Prepare firmware. */
580 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
581 firmware_files[firmware_idx]);
583 if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
584 sr_err("sigma: An error occured while reading the firmware: %s",
589 /* Upload firmare. */
590 sr_info("sigma: Uploading firmware %s", firmware_files[firmware_idx]);
591 sigma_write(buf, buf_size, devc);
595 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) {
596 sr_err("sigma: ftdi_set_bitmode failed: %s",
597 ftdi_get_error_string(&devc->ftdic));
601 ftdi_usb_purge_buffers(&devc->ftdic);
603 /* Discard garbage. */
604 while (1 == sigma_read(&pins, 1, devc))
607 /* Initialize the logic analyzer mode. */
608 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
610 /* Expect a 3 byte reply. */
611 ret = sigma_read(result, 3, devc);
613 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
614 sr_err("sigma: Configuration failed. Invalid reply received.");
618 devc->cur_firmware = firmware_idx;
620 sr_info("sigma: Firmware uploaded");
625 static int hw_dev_open(struct sr_dev_inst *sdi)
627 struct dev_context *devc;
632 /* Make sure it's an ASIX SIGMA. */
633 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
634 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
636 sr_err("sigma: ftdi_usb_open failed: %s",
637 ftdi_get_error_string(&devc->ftdic));
642 sdi->status = SR_ST_ACTIVE;
647 static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
650 struct dev_context *devc = sdi->priv;
652 for (i = 0; supported_samplerates[i]; i++) {
653 if (supported_samplerates[i] == samplerate)
656 if (supported_samplerates[i] == 0)
657 return SR_ERR_SAMPLERATE;
659 if (samplerate <= SR_MHZ(50)) {
660 ret = upload_firmware(0, devc);
661 devc->num_probes = 16;
663 if (samplerate == SR_MHZ(100)) {
664 ret = upload_firmware(1, devc);
665 devc->num_probes = 8;
667 else if (samplerate == SR_MHZ(200)) {
668 ret = upload_firmware(2, devc);
669 devc->num_probes = 4;
672 devc->cur_samplerate = samplerate;
673 devc->period_ps = 1000000000000 / samplerate;
674 devc->samples_per_event = 16 / devc->num_probes;
675 devc->state.state = SIGMA_IDLE;
681 * In 100 and 200 MHz mode, only a single pin rising/falling can be
682 * set as trigger. In other modes, two rising/falling triggers can be set,
683 * in addition to value/mask trigger for any number of probes.
685 * The Sigma supports complex triggers using boolean expressions, but this
686 * has not been implemented yet.
688 static int configure_probes(const struct sr_dev_inst *sdi, const GSList *probes)
690 struct dev_context *devc = sdi->priv;
691 const struct sr_probe *probe;
696 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
698 for (l = probes; l; l = l->next) {
699 probe = (struct sr_probe *)l->data;
700 probebit = 1 << (probe->index);
702 if (!probe->enabled || !probe->trigger)
705 if (devc->cur_samplerate >= SR_MHZ(100)) {
706 /* Fast trigger support. */
708 sr_err("sigma: ASIX SIGMA only supports a single "
709 "pin trigger in 100 and 200MHz mode.");
712 if (probe->trigger[0] == 'f')
713 devc->trigger.fallingmask |= probebit;
714 else if (probe->trigger[0] == 'r')
715 devc->trigger.risingmask |= probebit;
717 sr_err("sigma: ASIX SIGMA only supports "
718 "rising/falling trigger in 100 "
725 /* Simple trigger support (event). */
726 if (probe->trigger[0] == '1') {
727 devc->trigger.simplevalue |= probebit;
728 devc->trigger.simplemask |= probebit;
730 else if (probe->trigger[0] == '0') {
731 devc->trigger.simplevalue &= ~probebit;
732 devc->trigger.simplemask |= probebit;
734 else if (probe->trigger[0] == 'f') {
735 devc->trigger.fallingmask |= probebit;
738 else if (probe->trigger[0] == 'r') {
739 devc->trigger.risingmask |= probebit;
744 * Actually, Sigma supports 2 rising/falling triggers,
745 * but they are ORed and the current trigger syntax
746 * does not permit ORed triggers.
748 if (trigger_set > 1) {
749 sr_err("sigma: ASIX SIGMA only supports 1 "
750 "rising/falling triggers.");
756 devc->use_triggers = 1;
762 static int hw_dev_close(struct sr_dev_inst *sdi)
764 struct dev_context *devc;
766 if (!(devc = sdi->priv)) {
767 sr_err("sigma: %s: sdi->priv was NULL", __func__);
772 if (sdi->status == SR_ST_ACTIVE)
773 ftdi_usb_close(&devc->ftdic);
775 sdi->status = SR_ST_INACTIVE;
780 static int hw_cleanup(void)
788 static int hw_info_get(int info_id, const void **data,
789 const struct sr_dev_inst *sdi)
791 struct dev_context *devc;
797 case SR_DI_NUM_PROBES:
798 *data = GINT_TO_POINTER(NUM_PROBES);
800 case SR_DI_PROBE_NAMES:
803 case SR_DI_SAMPLERATES:
804 *data = &samplerates;
806 case SR_DI_TRIGGER_TYPES:
807 *data = (char *)TRIGGER_TYPES;
809 case SR_DI_CUR_SAMPLERATE:
812 *data = &devc->cur_samplerate;
823 static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap,
826 struct dev_context *devc;
831 if (hwcap == SR_HWCAP_SAMPLERATE) {
832 ret = set_samplerate(sdi, *(const uint64_t *)value);
833 } else if (hwcap == SR_HWCAP_PROBECONFIG) {
834 ret = configure_probes(sdi, value);
835 } else if (hwcap == SR_HWCAP_LIMIT_MSEC) {
836 devc->limit_msec = *(const uint64_t *)value;
837 if (devc->limit_msec > 0)
841 } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) {
842 devc->capture_ratio = *(const uint64_t *)value;
843 if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
854 /* Software trigger to determine exact trigger position. */
855 static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
856 struct sigma_trigger *t)
860 for (i = 0; i < 8; ++i) {
862 last_sample = samples[i-1];
864 /* Simple triggers. */
865 if ((samples[i] & t->simplemask) != t->simplevalue)
869 if ((last_sample & t->risingmask) != 0 || (samples[i] &
870 t->risingmask) != t->risingmask)
874 if ((last_sample & t->fallingmask) != t->fallingmask ||
875 (samples[i] & t->fallingmask) != 0)
881 /* If we did not match, return original trigger pos. */
886 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
887 * Each event is 20ns apart, and can contain multiple samples.
889 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
890 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
891 * For 50 MHz and below, events contain one sample for each channel,
892 * spread 20 ns apart.
894 static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
895 uint16_t *lastsample, int triggerpos,
896 uint16_t limit_chunk, void *cb_data)
898 struct sr_dev_inst *sdi = cb_data;
899 struct dev_context *devc = sdi->priv;
901 uint16_t samples[65536 * devc->samples_per_event];
902 struct sr_datafeed_packet packet;
903 struct sr_datafeed_logic logic;
904 int i, j, k, l, numpad, tosend;
905 size_t n = 0, sent = 0;
906 int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event;
911 /* Check if trigger is in this chunk. */
912 if (triggerpos != -1) {
913 if (devc->cur_samplerate <= SR_MHZ(50))
914 triggerpos -= EVENTS_PER_CLUSTER - 1;
919 /* Find in which cluster the trigger occured. */
920 triggerts = triggerpos / 7;
924 for (i = 0; i < 64; ++i) {
925 ts = *(uint16_t *) &buf[i * 16];
926 tsdiff = ts - *lastts;
929 /* Decode partial chunk. */
930 if (limit_chunk && ts > limit_chunk)
933 /* Pad last sample up to current point. */
934 numpad = tsdiff * devc->samples_per_event - clustersize;
936 for (j = 0; j < numpad; ++j)
937 samples[j] = *lastsample;
942 /* Send samples between previous and this timestamp to sigrok. */
945 tosend = MIN(2048, n - sent);
947 packet.type = SR_DF_LOGIC;
948 packet.payload = &logic;
949 logic.length = tosend * sizeof(uint16_t);
951 logic.data = samples + sent;
952 sr_session_send(devc->session_dev_id, &packet);
958 event = (uint16_t *) &buf[i * 16 + 2];
961 /* For each event in cluster. */
962 for (j = 0; j < 7; ++j) {
964 /* For each sample in event. */
965 for (k = 0; k < devc->samples_per_event; ++k) {
968 /* For each probe. */
969 for (l = 0; l < devc->num_probes; ++l)
970 cur_sample |= (!!(event[j] & (1 << (l *
971 devc->samples_per_event + k)))) << l;
973 samples[n++] = cur_sample;
977 /* Send data up to trigger point (if triggered). */
979 if (i == triggerts) {
981 * Trigger is not always accurate to sample because of
982 * pipeline delay. However, it always triggers before
983 * the actual event. We therefore look at the next
984 * samples to pinpoint the exact position of the trigger.
986 tosend = get_trigger_offset(samples, *lastsample,
990 packet.type = SR_DF_LOGIC;
991 packet.payload = &logic;
992 logic.length = tosend * sizeof(uint16_t);
994 logic.data = samples;
995 sr_session_send(devc->session_dev_id, &packet);
1000 /* Only send trigger if explicitly enabled. */
1001 if (devc->use_triggers) {
1002 packet.type = SR_DF_TRIGGER;
1003 sr_session_send(devc->session_dev_id, &packet);
1007 /* Send rest of the chunk to sigrok. */
1011 packet.type = SR_DF_LOGIC;
1012 packet.payload = &logic;
1013 logic.length = tosend * sizeof(uint16_t);
1015 logic.data = samples + sent;
1016 sr_session_send(devc->session_dev_id, &packet);
1019 *lastsample = samples[n - 1];
1025 static int receive_data(int fd, int revents, void *cb_data)
1027 struct sr_dev_inst *sdi = cb_data;
1028 struct dev_context *devc = sdi->priv;
1029 struct sr_datafeed_packet packet;
1030 const int chunks_per_read = 32;
1031 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1032 int bufsz, numchunks, i, newchunks;
1033 uint64_t running_msec;
1036 /* Avoid compiler warnings. */
1040 /* Get the current position. */
1041 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1043 numchunks = (devc->state.stoppos + 511) / 512;
1045 if (devc->state.state == SIGMA_IDLE)
1048 if (devc->state.state == SIGMA_CAPTURE) {
1049 /* Check if the timer has expired, or memory is full. */
1050 gettimeofday(&tv, 0);
1051 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1052 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1054 if (running_msec < devc->limit_msec && numchunks < 32767)
1055 return TRUE; /* While capturing... */
1057 hw_dev_acquisition_stop(sdi, sdi);
1059 } else if (devc->state.state == SIGMA_DOWNLOAD) {
1060 if (devc->state.chunks_downloaded >= numchunks) {
1061 /* End of samples. */
1062 packet.type = SR_DF_END;
1063 sr_session_send(devc->session_dev_id, &packet);
1065 devc->state.state = SIGMA_IDLE;
1070 newchunks = MIN(chunks_per_read,
1071 numchunks - devc->state.chunks_downloaded);
1073 sr_info("sigma: Downloading sample data: %.0f %%",
1074 100.0 * devc->state.chunks_downloaded / numchunks);
1076 bufsz = sigma_read_dram(devc->state.chunks_downloaded,
1077 newchunks, buf, devc);
1078 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1081 /* Find first ts. */
1082 if (devc->state.chunks_downloaded == 0) {
1083 devc->state.lastts = *(uint16_t *) buf - 1;
1084 devc->state.lastsample = 0;
1087 /* Decode chunks and send them to sigrok. */
1088 for (i = 0; i < newchunks; ++i) {
1089 int limit_chunk = 0;
1091 /* The last chunk may potentially be only in part. */
1092 if (devc->state.chunks_downloaded == numchunks - 1) {
1093 /* Find the last valid timestamp */
1094 limit_chunk = devc->state.stoppos % 512 + devc->state.lastts;
1097 if (devc->state.chunks_downloaded + i == devc->state.triggerchunk)
1098 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1099 &devc->state.lastts,
1100 &devc->state.lastsample,
1101 devc->state.triggerpos & 0x1ff,
1104 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1105 &devc->state.lastts,
1106 &devc->state.lastsample,
1107 -1, limit_chunk, sdi);
1109 ++devc->state.chunks_downloaded;
1116 /* Build a LUT entry used by the trigger functions. */
1117 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1121 /* For each quad probe. */
1122 for (i = 0; i < 4; ++i) {
1125 /* For each bit in LUT. */
1126 for (j = 0; j < 16; ++j)
1128 /* For each probe in quad. */
1129 for (k = 0; k < 4; ++k) {
1130 bit = 1 << (i * 4 + k);
1132 /* Set bit in entry */
1134 ((!(value & bit)) !=
1136 entry[i] &= ~(1 << j);
1141 /* Add a logical function to LUT mask. */
1142 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1143 int index, int neg, uint16_t *mask)
1146 int x[2][2], tmp, a, b, aset, bset, rset;
1148 memset(x, 0, 4 * sizeof(int));
1150 /* Trigger detect condition. */
1180 case OP_NOTRISEFALL:
1186 /* Transpose if neg is set. */
1188 for (i = 0; i < 2; ++i) {
1189 for (j = 0; j < 2; ++j) {
1191 x[i][j] = x[1-i][1-j];
1197 /* Update mask with function. */
1198 for (i = 0; i < 16; ++i) {
1199 a = (i >> (2 * index + 0)) & 1;
1200 b = (i >> (2 * index + 1)) & 1;
1202 aset = (*mask >> i) & 1;
1205 if (func == FUNC_AND || func == FUNC_NAND)
1207 else if (func == FUNC_OR || func == FUNC_NOR)
1209 else if (func == FUNC_XOR || func == FUNC_NXOR)
1212 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1223 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1224 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1225 * set at any time, but a full mask and value can be set (0/1).
1227 static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1230 uint16_t masks[2] = { 0, 0 };
1232 memset(lut, 0, sizeof(struct triggerlut));
1234 /* Contant for simple triggers. */
1237 /* Value/mask trigger support. */
1238 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1241 /* Rise/fall trigger support. */
1242 for (i = 0, j = 0; i < 16; ++i) {
1243 if (devc->trigger.risingmask & (1 << i) ||
1244 devc->trigger.fallingmask & (1 << i))
1245 masks[j++] = 1 << i;
1248 build_lut_entry(masks[0], masks[0], lut->m0d);
1249 build_lut_entry(masks[1], masks[1], lut->m1d);
1251 /* Add glue logic */
1252 if (masks[0] || masks[1]) {
1253 /* Transition trigger. */
1254 if (masks[0] & devc->trigger.risingmask)
1255 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1256 if (masks[0] & devc->trigger.fallingmask)
1257 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1258 if (masks[1] & devc->trigger.risingmask)
1259 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1260 if (masks[1] & devc->trigger.fallingmask)
1261 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1263 /* Only value/mask trigger. */
1267 /* Triggertype: event. */
1268 lut->params.selres = 3;
1273 static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
1276 struct dev_context *devc;
1277 struct sr_datafeed_packet *packet;
1278 struct sr_datafeed_header *header;
1279 struct sr_datafeed_meta_logic meta;
1280 struct clockselect_50 clockselect;
1281 int frac, triggerpin, ret;
1282 uint8_t triggerselect;
1283 struct triggerinout triggerinout_conf;
1284 struct triggerlut lut;
1288 /* If the samplerate has not been set, default to 200 kHz. */
1289 if (devc->cur_firmware == -1) {
1290 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1294 /* Enter trigger programming mode. */
1295 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1297 /* 100 and 200 MHz mode. */
1298 if (devc->cur_samplerate >= SR_MHZ(100)) {
1299 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1301 /* Find which pin to trigger on from mask. */
1302 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1303 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1307 /* Set trigger pin and light LED on trigger. */
1308 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1310 /* Default rising edge. */
1311 if (devc->trigger.fallingmask)
1312 triggerselect |= 1 << 3;
1314 /* All other modes. */
1315 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1316 build_basic_trigger(&lut, devc);
1318 sigma_write_trigger_lut(&lut, devc);
1320 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1323 /* Setup trigger in and out pins to default values. */
1324 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1325 triggerinout_conf.trgout_bytrigger = 1;
1326 triggerinout_conf.trgout_enable = 1;
1328 sigma_write_register(WRITE_TRIGGER_OPTION,
1329 (uint8_t *) &triggerinout_conf,
1330 sizeof(struct triggerinout), devc);
1332 /* Go back to normal mode. */
1333 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1335 /* Set clock select register. */
1336 if (devc->cur_samplerate == SR_MHZ(200))
1337 /* Enable 4 probes. */
1338 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1339 else if (devc->cur_samplerate == SR_MHZ(100))
1340 /* Enable 8 probes. */
1341 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1344 * 50 MHz mode (or fraction thereof). Any fraction down to
1345 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1347 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1349 clockselect.async = 0;
1350 clockselect.fraction = frac;
1351 clockselect.disabled_probes = 0;
1353 sigma_write_register(WRITE_CLOCK_SELECT,
1354 (uint8_t *) &clockselect,
1355 sizeof(clockselect), devc);
1358 /* Setup maximum post trigger time. */
1359 sigma_set_register(WRITE_POST_TRIGGER,
1360 (devc->capture_ratio * 255) / 100, devc);
1362 /* Start acqusition. */
1363 gettimeofday(&devc->start_tv, 0);
1364 sigma_set_register(WRITE_MODE, 0x0d, devc);
1366 devc->session_dev_id = cb_data;
1368 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1369 sr_err("sigma: %s: packet malloc failed.", __func__);
1370 return SR_ERR_MALLOC;
1373 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1374 sr_err("sigma: %s: header malloc failed.", __func__);
1375 return SR_ERR_MALLOC;
1378 /* Send header packet to the session bus. */
1379 packet->type = SR_DF_HEADER;
1380 packet->payload = header;
1381 header->feed_version = 1;
1382 gettimeofday(&header->starttime, NULL);
1383 sr_session_send(devc->session_dev_id, packet);
1385 /* Send metadata about the SR_DF_LOGIC packets to come. */
1386 packet->type = SR_DF_META_LOGIC;
1387 packet->payload = &meta;
1388 meta.samplerate = devc->cur_samplerate;
1389 meta.num_probes = devc->num_probes;
1390 sr_session_send(devc->session_dev_id, packet);
1392 /* Add capture source. */
1393 sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
1398 devc->state.state = SIGMA_CAPTURE;
1403 static int hw_dev_acquisition_stop(const struct sr_dev_inst *sdi,
1406 struct dev_context *devc;
1409 /* Avoid compiler warnings. */
1412 if (!(devc = sdi->priv)) {
1413 sr_err("sigma: %s: sdi->priv was NULL", __func__);
1417 /* Stop acquisition. */
1418 sigma_set_register(WRITE_MODE, 0x11, devc);
1420 /* Set SDRAM Read Enable. */
1421 sigma_set_register(WRITE_MODE, 0x02, devc);
1423 /* Get the current position. */
1424 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1426 /* Check if trigger has fired. */
1427 modestatus = sigma_get_register(READ_MODE, devc);
1428 if (modestatus & 0x20)
1429 devc->state.triggerchunk = devc->state.triggerpos / 512;
1431 devc->state.triggerchunk = -1;
1433 devc->state.chunks_downloaded = 0;
1435 devc->state.state = SIGMA_DOWNLOAD;
1440 SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1441 .name = "asix-sigma",
1442 .longname = "ASIX SIGMA/SIGMA2",
1445 .cleanup = hw_cleanup,
1447 .dev_open = hw_dev_open,
1448 .dev_close = hw_dev_close,
1449 .info_get = hw_info_get,
1450 .dev_config_set = hw_dev_config_set,
1451 .dev_acquisition_start = hw_dev_acquisition_start,
1452 .dev_acquisition_stop = hw_dev_acquisition_stop,