]> sigrok.org Git - libsigrok.git/blame_incremental - src/hardware/rigol-ds/api.c
projects / libsigrok.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
wav: Stricter check for valid chunk ID.
[libsigrok.git] / src / hardware / rigol-ds / api.c
... / ...
CommitLineData
1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2012 Martin Ling <martin-git@earth.li>
5 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
6 * Copyright (C) 2013 Mathias Grimmberger <mgri@zaphod.sax.de>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include <fcntl.h>
23#include <unistd.h>
24#include <stdlib.h>
25#include <string.h>
26#include <math.h>
27#include <glib.h>
28#include "libsigrok.h"
29#include "libsigrok-internal.h"
30#include "protocol.h"
31
32static const uint32_t scanopts[] = {
33 SR_CONF_CONN,
34 SR_CONF_SERIALCOMM
35};
36
37static const uint32_t devopts[] = {
38 SR_CONF_OSCILLOSCOPE,
39 SR_CONF_LIMIT_FRAMES | SR_CONF_SET,
40 SR_CONF_TIMEBASE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
41 SR_CONF_TRIGGER_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
42 SR_CONF_TRIGGER_SLOPE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
43 SR_CONF_HORIZ_TRIGGERPOS | SR_CONF_SET,
44 SR_CONF_NUM_HDIV | SR_CONF_GET,
45 SR_CONF_SAMPLERATE | SR_CONF_GET,
46 SR_CONF_DATA_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
47};
48
49static const uint32_t analog_devopts[] = {
50 SR_CONF_NUM_VDIV | SR_CONF_GET,
51 SR_CONF_VDIV | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
52 SR_CONF_COUPLING | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
53};
54
55static const uint64_t timebases[][2] = {
56 /* nanoseconds */
57 { 1, 1000000000 },
58 { 2, 1000000000 },
59 { 5, 1000000000 },
60 { 10, 1000000000 },
61 { 20, 1000000000 },
62 { 50, 1000000000 },
63 { 100, 1000000000 },
64 { 500, 1000000000 },
65 /* microseconds */
66 { 1, 1000000 },
67 { 2, 1000000 },
68 { 5, 1000000 },
69 { 10, 1000000 },
70 { 20, 1000000 },
71 { 50, 1000000 },
72 { 100, 1000000 },
73 { 200, 1000000 },
74 { 500, 1000000 },
75 /* milliseconds */
76 { 1, 1000 },
77 { 2, 1000 },
78 { 5, 1000 },
79 { 10, 1000 },
80 { 20, 1000 },
81 { 50, 1000 },
82 { 100, 1000 },
83 { 200, 1000 },
84 { 500, 1000 },
85 /* seconds */
86 { 1, 1 },
87 { 2, 1 },
88 { 5, 1 },
89 { 10, 1 },
90 { 20, 1 },
91 { 50, 1 },
92 { 100, 1 },
93 { 200, 1 },
94 { 500, 1 },
95 { 1000, 1 },
96};
97
98static const uint64_t vdivs[][2] = {
99 /* microvolts */
100 { 500, 1000000 },
101 /* millivolts */
102 { 1, 1000 },
103 { 2, 1000 },
104 { 5, 1000 },
105 { 10, 1000 },
106 { 20, 1000 },
107 { 50, 1000 },
108 { 100, 1000 },
109 { 200, 1000 },
110 { 500, 1000 },
111 /* volts */
112 { 1, 1 },
113 { 2, 1 },
114 { 5, 1 },
115 { 10, 1 },
116 { 20, 1 },
117 { 50, 1 },
118 { 100, 1 },
119};
120
121#define NUM_TIMEBASE ARRAY_SIZE(timebases)
122#define NUM_VDIV ARRAY_SIZE(vdivs)
123
124static const char *trigger_sources[] = {
125 "CH1",
126 "CH2",
127 "CH3",
128 "CH4",
129 "EXT",
130 "AC Line",
131 "D0",
132 "D1",
133 "D2",
134 "D3",
135 "D4",
136 "D5",
137 "D6",
138 "D7",
139 "D8",
140 "D9",
141 "D10",
142 "D11",
143 "D12",
144 "D13",
145 "D14",
146 "D15",
147};
148
149static const char *trigger_slopes[] = {
150 "r",
151 "f",
152};
153
154static const char *coupling[] = {
155 "AC",
156 "DC",
157 "GND",
158};
159
160/* Do not change the order of entries */
161static const char *data_sources[] = {
162 "Live",
163 "Memory",
164 "Segmented",
165};
166
167enum vendor {
168 RIGOL,
169 AGILENT,
170};
171
172enum series {
173 VS5000,
174 DS1000,
175 DS2000,
176 DS2000A,
177 DSO1000,
178 DS1000Z,
179};
180
181/* short name, full name */
182static const struct rigol_ds_vendor supported_vendors[] = {
183 [RIGOL] = {"Rigol", "Rigol Technologies"},
184 [AGILENT] = {"Agilent", "Agilent Technologies"},
185};
186
187#define VENDOR(x) &supported_vendors[x]
188/* vendor, series, protocol, max timebase, min vdiv, number of horizontal divs,
189 * live waveform samples, memory buffer samples */
190static const struct rigol_ds_series supported_series[] = {
191 [VS5000] = {VENDOR(RIGOL), "VS5000", PROTOCOL_V1, FORMAT_RAW,
192 {50, 1}, {2, 1000}, 14, 2048, 0},
193 [DS1000] = {VENDOR(RIGOL), "DS1000", PROTOCOL_V2, FORMAT_IEEE488_2,
194 {50, 1}, {2, 1000}, 12, 600, 1048576},
195 [DS2000] = {VENDOR(RIGOL), "DS2000", PROTOCOL_V3, FORMAT_IEEE488_2,
196 {500, 1}, {500, 1000000}, 14, 1400, 14000},
197 [DS2000A] = {VENDOR(RIGOL), "DS2000A", PROTOCOL_V3, FORMAT_IEEE488_2,
198 {1000, 1}, {500, 1000000}, 14, 1400, 14000},
199 [DSO1000] = {VENDOR(AGILENT), "DSO1000", PROTOCOL_V3, FORMAT_IEEE488_2,
200 {50, 1}, {2, 1000}, 12, 600, 20480},
201 [DS1000Z] = {VENDOR(RIGOL), "DS1000Z", PROTOCOL_V4, FORMAT_IEEE488_2,
202 {50, 1}, {1, 1000}, 12, 1200, 12000000},
203};
204
205#define SERIES(x) &supported_series[x]
206/* series, model, min timebase, analog channels, digital */
207static const struct rigol_ds_model supported_models[] = {
208 {SERIES(VS5000), "VS5022", {20, 1000000000}, 2, false},
209 {SERIES(VS5000), "VS5042", {10, 1000000000}, 2, false},
210 {SERIES(VS5000), "VS5062", {5, 1000000000}, 2, false},
211 {SERIES(VS5000), "VS5102", {2, 1000000000}, 2, false},
212 {SERIES(VS5000), "VS5202", {2, 1000000000}, 2, false},
213 {SERIES(VS5000), "VS5022D", {20, 1000000000}, 2, true},
214 {SERIES(VS5000), "VS5042D", {10, 1000000000}, 2, true},
215 {SERIES(VS5000), "VS5062D", {5, 1000000000}, 2, true},
216 {SERIES(VS5000), "VS5102D", {2, 1000000000}, 2, true},
217 {SERIES(VS5000), "VS5202D", {2, 1000000000}, 2, true},
218 {SERIES(DS1000), "DS1052E", {5, 1000000000}, 2, false},
219 {SERIES(DS1000), "DS1102E", {2, 1000000000}, 2, false},
220 {SERIES(DS1000), "DS1152E", {2, 1000000000}, 2, false},
221 {SERIES(DS1000), "DS1052D", {5, 1000000000}, 2, true},
222 {SERIES(DS1000), "DS1102D", {2, 1000000000}, 2, true},
223 {SERIES(DS1000), "DS1152D", {2, 1000000000}, 2, true},
224 {SERIES(DS2000), "DS2072", {5, 1000000000}, 2, false},
225 {SERIES(DS2000), "DS2102", {5, 1000000000}, 2, false},
226 {SERIES(DS2000), "DS2202", {2, 1000000000}, 2, false},
227 {SERIES(DS2000), "DS2302", {1, 1000000000}, 2, false},
228 {SERIES(DS2000A), "DS2072A", {5, 1000000000}, 2, false},
229 {SERIES(DS2000A), "DS2102A", {5, 1000000000}, 2, false},
230 {SERIES(DS2000A), "DS2202A", {2, 1000000000}, 2, false},
231 {SERIES(DS2000A), "DS2302A", {1, 1000000000}, 2, false},
232 {SERIES(DSO1000), "DSO1002A", {5, 1000000000}, 2, false},
233 {SERIES(DSO1000), "DSO1004A", {5, 1000000000}, 4, false},
234 {SERIES(DSO1000), "DSO1012A", {2, 1000000000}, 2, false},
235 {SERIES(DSO1000), "DSO1014A", {2, 1000000000}, 4, false},
236 {SERIES(DSO1000), "DSO1022A", {2, 1000000000}, 2, false},
237 {SERIES(DSO1000), "DSO1024A", {2, 1000000000}, 4, false},
238 {SERIES(DS1000Z), "DS1054Z", {5, 1000000000}, 4, false},
239 {SERIES(DS1000Z), "DS1074Z", {5, 1000000000}, 4, false},
240 {SERIES(DS1000Z), "DS1104Z", {5, 1000000000}, 4, false},
241 {SERIES(DS1000Z), "DS1074Z-S", {5, 1000000000}, 4, false},
242 {SERIES(DS1000Z), "DS1104Z-S", {5, 1000000000}, 4, false},
243 {SERIES(DS1000Z), "MSO1074Z", {5, 1000000000}, 4, true},
244 {SERIES(DS1000Z), "MSO1104Z", {5, 1000000000}, 4, true},
245 {SERIES(DS1000Z), "MSO1074Z-S", {5, 1000000000}, 4, true},
246 {SERIES(DS1000Z), "MSO1104Z-S", {5, 1000000000}, 4, true},
247};
248
249SR_PRIV struct sr_dev_driver rigol_ds_driver_info;
250
251static void clear_helper(void *priv)
252{
253 struct dev_context *devc;
254 unsigned int i;
255
256 devc = priv;
257 g_free(devc->data);
258 g_free(devc->buffer);
259 for (i = 0; i < ARRAY_SIZE(devc->coupling); i++)
260 g_free(devc->coupling[i]);
261 g_free(devc->trigger_source);
262 g_free(devc->trigger_slope);
263 g_free(devc->analog_groups);
264 g_free(devc);
265}
266
267static int dev_clear(const struct sr_dev_driver *di)
268{
269 return std_dev_clear(di, clear_helper);
270}
271
272static int init(struct sr_dev_driver *di, struct sr_context *sr_ctx)
273{
274 return std_init(sr_ctx, di, LOG_PREFIX);
275}
276
277static struct sr_dev_inst *probe_device(struct sr_scpi_dev_inst *scpi)
278{
279 struct dev_context *devc;
280 struct sr_dev_inst *sdi;
281 struct sr_scpi_hw_info *hw_info;
282 struct sr_channel *ch;
283 long n[3];
284 unsigned int i;
285 const struct rigol_ds_model *model = NULL;
286 gchar *channel_name, **version;
287
288 if (sr_scpi_get_hw_id(scpi, &hw_info) != SR_OK) {
289 sr_info("Couldn't get IDN response, retrying.");
290 sr_scpi_close(scpi);
291 sr_scpi_open(scpi);
292 if (sr_scpi_get_hw_id(scpi, &hw_info) != SR_OK) {
293 sr_info("Couldn't get IDN response.");
294 return NULL;
295 }
296 }
297
298 for (i = 0; i < ARRAY_SIZE(supported_models); i++) {
299 if (!strcasecmp(hw_info->manufacturer,
300 supported_models[i].series->vendor->full_name) &&
301 !strcmp(hw_info->model, supported_models[i].name)) {
302 model = &supported_models[i];
303 break;
304 }
305 }
306
307 if (!model) {
308 sr_scpi_hw_info_free(hw_info);
309 return NULL;
310 }
311
312 sdi = g_malloc0(sizeof(struct sr_dev_inst));
313 sdi->status = SR_ST_ACTIVE;
314 sdi->vendor = g_strdup(model->series->vendor->name);
315 sdi->model = g_strdup(model->name);
316 sdi->version = g_strdup(hw_info->firmware_version);
317 sdi->conn = scpi;
318 sdi->driver = &rigol_ds_driver_info;
319 sdi->inst_type = SR_INST_SCPI;
320 sdi->serial_num = g_strdup(hw_info->serial_number);
321 devc = g_malloc0(sizeof(struct dev_context));
322 devc->limit_frames = 0;
323 devc->model = model;
324 devc->format = model->series->format;
325
326 /* DS1000 models with firmware before 0.2.4 used the old data format. */
327 if (model->series == SERIES(DS1000)) {
328 version = g_strsplit(hw_info->firmware_version, ".", 0);
329 do {
330 if (!version[0] || !version[1] || !version[2])
331 break;
332 if (version[0][0] == 0 || version[1][0] == 0 || version[2][0] == 0)
333 break;
334 for (i = 0; i < 3; i++) {
335 if (sr_atol(version[i], &n[i]) != SR_OK)
336 break;
337 }
338 if (i != 3)
339 break;
340 if (n[0] != 0 || n[1] > 2)
341 break;
342 if (n[1] == 2 && n[2] > 3)
343 break;
344 sr_dbg("Found DS1000 firmware < 0.2.4, using raw data format.");
345 devc->format = FORMAT_RAW;
346 } while (0);
347 g_strfreev(version);
348 }
349
350 sr_scpi_hw_info_free(hw_info);
351
352 devc->analog_groups = g_malloc0(sizeof(struct sr_channel_group*) *
353 model->analog_channels);
354
355 for (i = 0; i < model->analog_channels; i++) {
356 channel_name = g_strdup_printf("CH%d", i + 1);
357 ch = sr_channel_new(sdi, i, SR_CHANNEL_ANALOG, TRUE, channel_name);
358
359 devc->analog_groups[i] = g_malloc0(sizeof(struct sr_channel_group));
360
361 devc->analog_groups[i]->name = channel_name;
362 devc->analog_groups[i]->channels = g_slist_append(NULL, ch);
363 sdi->channel_groups = g_slist_append(sdi->channel_groups,
364 devc->analog_groups[i]);
365 }
366
367 if (devc->model->has_digital) {
368 devc->digital_group = g_malloc0(sizeof(struct sr_channel_group));
369
370 for (i = 0; i < ARRAY_SIZE(devc->digital_channels); i++) {
371 channel_name = g_strdup_printf("D%d", i);
372 ch = sr_channel_new(sdi, i, SR_CHANNEL_LOGIC, TRUE, channel_name);
373 g_free(channel_name);
374 devc->digital_group->channels = g_slist_append(
375 devc->digital_group->channels, ch);
376 }
377 devc->digital_group->name = g_strdup("LA");
378 sdi->channel_groups = g_slist_append(sdi->channel_groups,
379 devc->digital_group);
380 }
381
382 for (i = 0; i < NUM_TIMEBASE; i++) {
383 if (!memcmp(&devc->model->min_timebase, &timebases[i], sizeof(uint64_t[2])))
384 devc->timebases = &timebases[i];
385 if (!memcmp(&devc->model->series->max_timebase, &timebases[i], sizeof(uint64_t[2])))
386 devc->num_timebases = &timebases[i] - devc->timebases + 1;
387 }
388
389 for (i = 0; i < NUM_VDIV; i++) {
390 if (!memcmp(&devc->model->series->min_vdiv,
391 &vdivs[i], sizeof(uint64_t[2]))) {
392 devc->vdivs = &vdivs[i];
393 devc->num_vdivs = NUM_VDIV - i;
394 }
395 }
396
397 devc->buffer = g_malloc(ACQ_BUFFER_SIZE);
398 devc->data = g_malloc(ACQ_BUFFER_SIZE * sizeof(float));
399
400 devc->data_source = DATA_SOURCE_LIVE;
401
402 sdi->priv = devc;
403
404 return sdi;
405}
406
407static GSList *scan(struct sr_dev_driver *di, GSList *options)
408{
409 return sr_scpi_scan(di->priv, options, probe_device);
410}
411
412static GSList *dev_list(const struct sr_dev_driver *di)
413{
414 return ((struct drv_context *)(di->priv))->instances;
415}
416
417static int dev_open(struct sr_dev_inst *sdi)
418{
419 int ret;
420 struct sr_scpi_dev_inst *scpi = sdi->conn;
421
422 if ((ret = sr_scpi_open(scpi)) < 0) {
423 sr_err("Failed to open SCPI device: %s.", sr_strerror(ret));
424 return SR_ERR;
425 }
426
427 if ((ret = rigol_ds_get_dev_cfg(sdi)) < 0) {
428 sr_err("Failed to get device config: %s.", sr_strerror(ret));
429 return SR_ERR;
430 }
431
432 sdi->status = SR_ST_ACTIVE;
433
434 return SR_OK;
435}
436
437static int dev_close(struct sr_dev_inst *sdi)
438{
439 struct sr_scpi_dev_inst *scpi;
440 struct dev_context *devc;
441
442 if (sdi->status != SR_ST_ACTIVE)
443 return SR_ERR_DEV_CLOSED;
444
445 scpi = sdi->conn;
446 devc = sdi->priv;
447
448 if (devc->model->series->protocol == PROTOCOL_V2)
449 rigol_ds_config_set(sdi, ":KEY:LOCK DISABLE");
450
451 if (scpi) {
452 if (sr_scpi_close(scpi) < 0)
453 return SR_ERR;
454 sdi->status = SR_ST_INACTIVE;
455 }
456
457 return SR_OK;
458}
459
460static int cleanup(const struct sr_dev_driver *di)
461{
462 return dev_clear(di);
463}
464
465static int analog_frame_size(const struct sr_dev_inst *sdi)
466{
467 struct dev_context *devc = sdi->priv;
468 struct sr_channel *ch;
469 int analog_channels = 0;
470 GSList *l;
471
472 for (l = sdi->channels; l; l = l->next) {
473 ch = l->data;
474 if (ch->type == SR_CHANNEL_ANALOG && ch->enabled)
475 analog_channels++;
476 }
477
478 if (analog_channels == 0)
479 return 0;
480
481 switch (devc->data_source) {
482 case DATA_SOURCE_LIVE:
483 return devc->model->series->live_samples;
484 case DATA_SOURCE_MEMORY:
485 return devc->model->series->buffer_samples / analog_channels;
486 default:
487 return 0;
488 }
489}
490
491static int digital_frame_size(const struct sr_dev_inst *sdi)
492{
493 struct dev_context *devc = sdi->priv;
494
495 switch (devc->data_source) {
496 case DATA_SOURCE_LIVE:
497 return devc->model->series->live_samples * 2;
498 case DATA_SOURCE_MEMORY:
499 return devc->model->series->buffer_samples * 2;
500 default:
501 return 0;
502 }
503}
504
505static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
506 const struct sr_channel_group *cg)
507{
508 struct dev_context *devc;
509 struct sr_channel *ch;
510 const char *tmp_str;
511 uint64_t samplerate;
512 int analog_channel = -1;
513 float smallest_diff = INFINITY;
514 int idx = -1;
515 unsigned i;
516
517 if (!sdi || !(devc = sdi->priv))
518 return SR_ERR_ARG;
519
520 /* If a channel group is specified, it must be a valid one. */
521 if (cg && !g_slist_find(sdi->channel_groups, cg)) {
522 sr_err("Invalid channel group specified.");
523 return SR_ERR;
524 }
525
526 if (cg) {
527 ch = g_slist_nth_data(cg->channels, 0);
528 if (!ch)
529 return SR_ERR;
530 if (ch->type == SR_CHANNEL_ANALOG) {
531 if (ch->name[2] < '1' || ch->name[2] > '4')
532 return SR_ERR;
533 analog_channel = ch->name[2] - '1';
534 }
535 }
536
537 switch (key) {
538 case SR_CONF_NUM_HDIV:
539 *data = g_variant_new_int32(devc->model->series->num_horizontal_divs);
540 break;
541 case SR_CONF_NUM_VDIV:
542 *data = g_variant_new_int32(devc->num_vdivs);
543 break;
544 case SR_CONF_DATA_SOURCE:
545 if (devc->data_source == DATA_SOURCE_LIVE)
546 *data = g_variant_new_string("Live");
547 else if (devc->data_source == DATA_SOURCE_MEMORY)
548 *data = g_variant_new_string("Memory");
549 else
550 *data = g_variant_new_string("Segmented");
551 break;
552 case SR_CONF_SAMPLERATE:
553 if (devc->data_source == DATA_SOURCE_LIVE) {
554 samplerate = analog_frame_size(sdi) /
555 (devc->timebase * devc->model->series->num_horizontal_divs);
556 *data = g_variant_new_uint64(samplerate);
557 } else {
558 sr_dbg("Unknown data source: %d.", devc->data_source);
559 return SR_ERR_NA;
560 }
561 break;
562 case SR_CONF_TRIGGER_SOURCE:
563 if (!strcmp(devc->trigger_source, "ACL"))
564 tmp_str = "AC Line";
565 else if (!strcmp(devc->trigger_source, "CHAN1"))
566 tmp_str = "CH1";
567 else if (!strcmp(devc->trigger_source, "CHAN2"))
568 tmp_str = "CH2";
569 else if (!strcmp(devc->trigger_source, "CHAN3"))
570 tmp_str = "CH3";
571 else if (!strcmp(devc->trigger_source, "CHAN4"))
572 tmp_str = "CH4";
573 else
574 tmp_str = devc->trigger_source;
575 *data = g_variant_new_string(tmp_str);
576 break;
577 case SR_CONF_TRIGGER_SLOPE:
578 if (!strncmp(devc->trigger_slope, "POS", 3)) {
579 tmp_str = "r";
580 } else if (!strncmp(devc->trigger_slope, "NEG", 3)) {
581 tmp_str = "f";
582 } else {
583 sr_dbg("Unknown trigger slope: '%s'.", devc->trigger_slope);
584 return SR_ERR_NA;
585 }
586 *data = g_variant_new_string(tmp_str);
587 break;
588 case SR_CONF_TIMEBASE:
589 for (i = 0; i < devc->num_timebases; i++) {
590 float tb = (float)devc->timebases[i][0] / devc->timebases[i][1];
591 float diff = fabs(devc->timebase - tb);
592 if (diff < smallest_diff) {
593 smallest_diff = diff;
594 idx = i;
595 }
596 }
597 if (idx < 0) {
598 sr_dbg("Negative timebase index: %d.", idx);
599 return SR_ERR_NA;
600 }
601 *data = g_variant_new("(tt)", devc->timebases[idx][0],
602 devc->timebases[idx][1]);
603 break;
604 case SR_CONF_VDIV:
605 if (analog_channel < 0) {
606 sr_dbg("Negative analog channel: %d.", analog_channel);
607 return SR_ERR_NA;
608 }
609 for (i = 0; i < ARRAY_SIZE(vdivs); i++) {
610 float vdiv = (float)vdivs[i][0] / vdivs[i][1];
611 float diff = fabs(devc->vdiv[analog_channel] - vdiv);
612 if (diff < smallest_diff) {
613 smallest_diff = diff;
614 idx = i;
615 }
616 }
617 if (idx < 0) {
618 sr_dbg("Negative vdiv index: %d.", idx);
619 return SR_ERR_NA;
620 }
621 *data = g_variant_new("(tt)", vdivs[idx][0], vdivs[idx][1]);
622 break;
623 case SR_CONF_COUPLING:
624 if (analog_channel < 0) {
625 sr_dbg("Negative analog channel: %d.", analog_channel);
626 return SR_ERR_NA;
627 }
628 *data = g_variant_new_string(devc->coupling[analog_channel]);
629 break;
630 default:
631 return SR_ERR_NA;
632 }
633
634 return SR_OK;
635}
636
637static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi,
638 const struct sr_channel_group *cg)
639{
640 struct dev_context *devc;
641 uint64_t p, q;
642 double t_dbl;
643 unsigned int i, j;
644 int ret;
645 const char *tmp_str;
646 char buffer[16];
647
648 if (!(devc = sdi->priv))
649 return SR_ERR_ARG;
650
651 if (sdi->status != SR_ST_ACTIVE)
652 return SR_ERR_DEV_CLOSED;
653
654 /* If a channel group is specified, it must be a valid one. */
655 if (cg && !g_slist_find(sdi->channel_groups, cg)) {
656 sr_err("Invalid channel group specified.");
657 return SR_ERR;
658 }
659
660 ret = SR_OK;
661 switch (key) {
662 case SR_CONF_LIMIT_FRAMES:
663 devc->limit_frames = g_variant_get_uint64(data);
664 break;
665 case SR_CONF_TRIGGER_SLOPE:
666 tmp_str = g_variant_get_string(data, NULL);
667
668 if (!tmp_str || !(tmp_str[0] == 'f' || tmp_str[0] == 'r')) {
669 sr_err("Unknown trigger slope: '%s'.",
670 (tmp_str) ? tmp_str : "NULL");
671 return SR_ERR_ARG;
672 }
673
674 g_free(devc->trigger_slope);
675 devc->trigger_slope = g_strdup((tmp_str[0] == 'r') ? "POS" : "NEG");
676 ret = rigol_ds_config_set(sdi, ":TRIG:EDGE:SLOP %s", devc->trigger_slope);
677 break;
678 case SR_CONF_HORIZ_TRIGGERPOS:
679 t_dbl = g_variant_get_double(data);
680 if (t_dbl < 0.0 || t_dbl > 1.0) {
681 sr_err("Invalid horiz. trigger position: %g.", t_dbl);
682 return SR_ERR;
683 }
684 devc->horiz_triggerpos = t_dbl;
685 /* We have the trigger offset as a percentage of the frame, but
686 * need to express this in seconds. */
687 t_dbl = -(devc->horiz_triggerpos - 0.5) * devc->timebase * devc->num_timebases;
688 g_ascii_formatd(buffer, sizeof(buffer), "%.6f", t_dbl);
689 ret = rigol_ds_config_set(sdi, ":TIM:OFFS %s", buffer);
690 break;
691 case SR_CONF_TIMEBASE:
692 g_variant_get(data, "(tt)", &p, &q);
693 for (i = 0; i < devc->num_timebases; i++) {
694 if (devc->timebases[i][0] == p && devc->timebases[i][1] == q) {
695 devc->timebase = (float)p / q;
696 g_ascii_formatd(buffer, sizeof(buffer), "%.9f",
697 devc->timebase);
698 ret = rigol_ds_config_set(sdi, ":TIM:SCAL %s", buffer);
699 break;
700 }
701 }
702 if (i == devc->num_timebases) {
703 sr_err("Invalid timebase index: %d.", i);
704 ret = SR_ERR_ARG;
705 }
706 break;
707 case SR_CONF_TRIGGER_SOURCE:
708 tmp_str = g_variant_get_string(data, NULL);
709 for (i = 0; i < ARRAY_SIZE(trigger_sources); i++) {
710 if (!strcmp(trigger_sources[i], tmp_str)) {
711 g_free(devc->trigger_source);
712 devc->trigger_source = g_strdup(trigger_sources[i]);
713 if (!strcmp(devc->trigger_source, "AC Line"))
714 tmp_str = "ACL";
715 else if (!strcmp(devc->trigger_source, "CH1"))
716 tmp_str = "CHAN1";
717 else if (!strcmp(devc->trigger_source, "CH2"))
718 tmp_str = "CHAN2";
719 else if (!strcmp(devc->trigger_source, "CH3"))
720 tmp_str = "CHAN3";
721 else if (!strcmp(devc->trigger_source, "CH4"))
722 tmp_str = "CHAN4";
723 else
724 tmp_str = (char *)devc->trigger_source;
725 ret = rigol_ds_config_set(sdi, ":TRIG:EDGE:SOUR %s", tmp_str);
726 break;
727 }
728 }
729 if (i == ARRAY_SIZE(trigger_sources)) {
730 sr_err("Invalid trigger source index: %d.", i);
731 ret = SR_ERR_ARG;
732 }
733 break;
734 case SR_CONF_VDIV:
735 if (!cg) {
736 sr_err("No channel group specified.");
737 return SR_ERR_CHANNEL_GROUP;
738 }
739 g_variant_get(data, "(tt)", &p, &q);
740 for (i = 0; i < devc->model->analog_channels; i++) {
741 if (cg == devc->analog_groups[i]) {
742 for (j = 0; j < ARRAY_SIZE(vdivs); j++) {
743 if (vdivs[j][0] != p || vdivs[j][1] != q)
744 continue;
745 devc->vdiv[i] = (float)p / q;
746 g_ascii_formatd(buffer, sizeof(buffer), "%.3f",
747 devc->vdiv[i]);
748 return rigol_ds_config_set(sdi, ":CHAN%d:SCAL %s", i + 1,
749 buffer);
750 }
751 sr_err("Invalid vdiv index: %d.", j);
752 return SR_ERR_ARG;
753 }
754 }
755 sr_dbg("Didn't set vdiv, unknown channel(group).");
756 return SR_ERR_NA;
757 case SR_CONF_COUPLING:
758 if (!cg) {
759 sr_err("No channel group specified.");
760 return SR_ERR_CHANNEL_GROUP;
761 }
762 tmp_str = g_variant_get_string(data, NULL);
763 for (i = 0; i < devc->model->analog_channels; i++) {
764 if (cg == devc->analog_groups[i]) {
765 for (j = 0; j < ARRAY_SIZE(coupling); j++) {
766 if (!strcmp(tmp_str, coupling[j])) {
767 g_free(devc->coupling[i]);
768 devc->coupling[i] = g_strdup(coupling[j]);
769 return rigol_ds_config_set(sdi, ":CHAN%d:COUP %s", i + 1,
770 devc->coupling[i]);
771 }
772 }
773 sr_err("Invalid coupling index: %d.", j);
774 return SR_ERR_ARG;
775 }
776 }
777 sr_dbg("Didn't set coupling, unknown channel(group).");
778 return SR_ERR_NA;
779 case SR_CONF_DATA_SOURCE:
780 tmp_str = g_variant_get_string(data, NULL);
781 if (!strcmp(tmp_str, "Live"))
782 devc->data_source = DATA_SOURCE_LIVE;
783 else if (devc->model->series->protocol >= PROTOCOL_V2
784 && !strcmp(tmp_str, "Memory"))
785 devc->data_source = DATA_SOURCE_MEMORY;
786 else if (devc->model->series->protocol >= PROTOCOL_V3
787 && !strcmp(tmp_str, "Segmented"))
788 devc->data_source = DATA_SOURCE_SEGMENTED;
789 else {
790 sr_err("Unknown data source: '%s'.", tmp_str);
791 return SR_ERR;
792 }
793 break;
794 default:
795 return SR_ERR_NA;
796 }
797
798 return ret;
799}
800
801static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
802 const struct sr_channel_group *cg)
803{
804 GVariant *tuple, *rational[2];
805 GVariantBuilder gvb;
806 unsigned int i;
807 struct dev_context *devc = NULL;
808
809 if (sdi)
810 devc = sdi->priv;
811
812 if (key == SR_CONF_SCAN_OPTIONS) {
813 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
814 scanopts, ARRAY_SIZE(scanopts), sizeof(uint32_t));
815 return SR_OK;
816 } else if (key == SR_CONF_DEVICE_OPTIONS && !cg) {
817 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
818 devopts, ARRAY_SIZE(devopts), sizeof(uint32_t));
819 return SR_OK;
820 }
821
822 /* Every other option requires a valid device instance. */
823 if (!sdi || !(devc = sdi->priv))
824 return SR_ERR_ARG;
825
826 /* If a channel group is specified, it must be a valid one. */
827 if (cg && !g_slist_find(sdi->channel_groups, cg)) {
828 sr_err("Invalid channel group specified.");
829 return SR_ERR;
830 }
831
832 switch (key) {
833 case SR_CONF_DEVICE_OPTIONS:
834 if (!cg) {
835 sr_err("No channel group specified.");
836 return SR_ERR_CHANNEL_GROUP;
837 }
838 if (cg == devc->digital_group) {
839 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
840 NULL, 0, sizeof(uint32_t));
841 return SR_OK;
842 } else {
843 for (i = 0; i < devc->model->analog_channels; i++) {
844 if (cg == devc->analog_groups[i]) {
845 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
846 analog_devopts, ARRAY_SIZE(analog_devopts), sizeof(uint32_t));
847 return SR_OK;
848 }
849 }
850 return SR_ERR_NA;
851 }
852 break;
853 case SR_CONF_COUPLING:
854 if (!cg) {
855 sr_err("No channel group specified.");
856 return SR_ERR_CHANNEL_GROUP;
857 }
858 *data = g_variant_new_strv(coupling, ARRAY_SIZE(coupling));
859 break;
860 case SR_CONF_VDIV:
861 if (!devc)
862 /* Can't know this until we have the exact model. */
863 return SR_ERR_ARG;
864 if (!cg) {
865 sr_err("No channel group specified.");
866 return SR_ERR_CHANNEL_GROUP;
867 }
868 g_variant_builder_init(&gvb, G_VARIANT_TYPE_ARRAY);
869 for (i = 0; i < devc->num_vdivs; i++) {
870 rational[0] = g_variant_new_uint64(devc->vdivs[i][0]);
871 rational[1] = g_variant_new_uint64(devc->vdivs[i][1]);
872 tuple = g_variant_new_tuple(rational, 2);
873 g_variant_builder_add_value(&gvb, tuple);
874 }
875 *data = g_variant_builder_end(&gvb);
876 break;
877 case SR_CONF_TIMEBASE:
878 if (!devc)
879 /* Can't know this until we have the exact model. */
880 return SR_ERR_ARG;
881 if (devc->num_timebases <= 0)
882 return SR_ERR_NA;
883 g_variant_builder_init(&gvb, G_VARIANT_TYPE_ARRAY);
884 for (i = 0; i < devc->num_timebases; i++) {
885 rational[0] = g_variant_new_uint64(devc->timebases[i][0]);
886 rational[1] = g_variant_new_uint64(devc->timebases[i][1]);
887 tuple = g_variant_new_tuple(rational, 2);
888 g_variant_builder_add_value(&gvb, tuple);
889 }
890 *data = g_variant_builder_end(&gvb);
891 break;
892 case SR_CONF_TRIGGER_SOURCE:
893 if (!devc)
894 /* Can't know this until we have the exact model. */
895 return SR_ERR_ARG;
896 *data = g_variant_new_strv(trigger_sources,
897 devc->model->has_digital ? ARRAY_SIZE(trigger_sources) : 4);
898 break;
899 case SR_CONF_TRIGGER_SLOPE:
900 *data = g_variant_new_strv(trigger_slopes, ARRAY_SIZE(trigger_slopes));
901 break;
902 case SR_CONF_DATA_SOURCE:
903 if (!devc)
904 /* Can't know this until we have the exact model. */
905 return SR_ERR_ARG;
906 switch (devc->model->series->protocol) {
907 case PROTOCOL_V1:
908 *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources) - 2);
909 break;
910 case PROTOCOL_V2:
911 *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources) - 1);
912 break;
913 default:
914 *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources));
915 break;
916 }
917 break;
918 default:
919 return SR_ERR_NA;
920 }
921
922 return SR_OK;
923}
924
925static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
926{
927 struct sr_scpi_dev_inst *scpi;
928 struct dev_context *devc;
929 struct sr_channel *ch;
930 struct sr_datafeed_packet packet;
931 gboolean some_digital;
932 GSList *l;
933
934 if (sdi->status != SR_ST_ACTIVE)
935 return SR_ERR_DEV_CLOSED;
936
937 scpi = sdi->conn;
938 devc = sdi->priv;
939
940 devc->num_frames = 0;
941
942 some_digital = FALSE;
943 for (l = sdi->channels; l; l = l->next) {
944 ch = l->data;
945 sr_dbg("handling channel %s", ch->name);
946 if (ch->type == SR_CHANNEL_ANALOG) {
947 if (ch->enabled)
948 devc->enabled_channels = g_slist_append(
949 devc->enabled_channels, ch);
950 if (ch->enabled != devc->analog_channels[ch->index]) {
951 /* Enabled channel is currently disabled, or vice versa. */
952 if (rigol_ds_config_set(sdi, ":CHAN%d:DISP %s", ch->index + 1,
953 ch->enabled ? "ON" : "OFF") != SR_OK)
954 return SR_ERR;
955 devc->analog_channels[ch->index] = ch->enabled;
956 }
957 } else if (ch->type == SR_CHANNEL_LOGIC) {
958 /* Only one list entry for DS1000D series. All channels are retrieved
959 * together when this entry is processed. */
960 if (ch->enabled && (
961 devc->model->series->protocol > PROTOCOL_V2 ||
962 !some_digital))
963 devc->enabled_channels = g_slist_append(
964 devc->enabled_channels, ch);
965 if (ch->enabled) {
966 some_digital = TRUE;
967 /* Turn on LA module if currently off. */
968 if (!devc->la_enabled) {
969 if (rigol_ds_config_set(sdi,
970 devc->model->series->protocol >= PROTOCOL_V4 ?
971 ":LA:STAT ON" : ":LA:DISP ON") != SR_OK)
972 return SR_ERR;
973 devc->la_enabled = TRUE;
974 }
975 }
976 if (ch->enabled != devc->digital_channels[ch->index]) {
977 /* Enabled channel is currently disabled, or vice versa. */
978 if (rigol_ds_config_set(sdi,
979 devc->model->series->protocol >= PROTOCOL_V4 ?
980 ":LA:DIG%d:DISP %s" : ":DIG%d:TURN %s", ch->index,
981 ch->enabled ? "ON" : "OFF") != SR_OK)
982 return SR_ERR;
983 devc->digital_channels[ch->index] = ch->enabled;
984 }
985 }
986 }
987
988 if (!devc->enabled_channels)
989 return SR_ERR;
990
991 /* Turn off LA module if on and no digital channels selected. */
992 if (devc->la_enabled && !some_digital)
993 if (rigol_ds_config_set(sdi,
994 devc->model->series->protocol >= PROTOCOL_V4 ?
995 ":LA:STAT OFF" : ":LA:DISP OFF") != SR_OK)
996 return SR_ERR;
997
998 /* Set memory mode. */
999 if (devc->data_source == DATA_SOURCE_SEGMENTED) {
1000 sr_err("Data source 'Segmented' not yet supported");
1001 return SR_ERR;
1002 }
1003
1004 devc->analog_frame_size = analog_frame_size(sdi);
1005 devc->digital_frame_size = digital_frame_size(sdi);
1006
1007 switch (devc->model->series->protocol) {
1008 case PROTOCOL_V2:
1009 if (rigol_ds_config_set(sdi, ":ACQ:MEMD LONG") != SR_OK)
1010 return SR_ERR;
1011 break;
1012 case PROTOCOL_V3:
1013 /* Apparently for the DS2000 the memory
1014 * depth can only be set in Running state -
1015 * this matches the behaviour of the UI. */
1016 if (rigol_ds_config_set(sdi, ":RUN") != SR_OK)
1017 return SR_ERR;
1018 if (rigol_ds_config_set(sdi, ":ACQ:MDEP %d",
1019 devc->analog_frame_size) != SR_OK)
1020 return SR_ERR;
1021 if (rigol_ds_config_set(sdi, ":STOP") != SR_OK)
1022 return SR_ERR;
1023 break;
1024 default:
1025 break;
1026 }
1027
1028 if (devc->data_source == DATA_SOURCE_LIVE)
1029 if (rigol_ds_config_set(sdi, ":RUN") != SR_OK)
1030 return SR_ERR;
1031
1032 sr_scpi_source_add(sdi->session, scpi, G_IO_IN, 50,
1033 rigol_ds_receive, (void *)sdi);
1034
1035 /* Send header packet to the session bus. */
1036 std_session_send_df_header(cb_data, LOG_PREFIX);
1037
1038 devc->channel_entry = devc->enabled_channels;
1039
1040 if (rigol_ds_capture_start(sdi) != SR_OK)
1041 return SR_ERR;
1042
1043 /* Start of first frame. */
1044 packet.type = SR_DF_FRAME_BEGIN;
1045 sr_session_send(cb_data, &packet);
1046
1047 return SR_OK;
1048}
1049
1050static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1051{
1052 struct dev_context *devc;
1053 struct sr_scpi_dev_inst *scpi;
1054 struct sr_datafeed_packet packet;
1055
1056 (void)cb_data;
1057
1058 devc = sdi->priv;
1059
1060 if (sdi->status != SR_ST_ACTIVE) {
1061 sr_err("Device inactive, can't stop acquisition.");
1062 return SR_ERR;
1063 }
1064
1065 /* End of last frame. */
1066 packet.type = SR_DF_END;
1067 sr_session_send(sdi, &packet);
1068
1069 g_slist_free(devc->enabled_channels);
1070 devc->enabled_channels = NULL;
1071 scpi = sdi->conn;
1072 sr_scpi_source_remove(sdi->session, scpi);
1073
1074 return SR_OK;
1075}
1076
1077SR_PRIV struct sr_dev_driver rigol_ds_driver_info = {
1078 .name = "rigol-ds",
1079 .longname = "Rigol DS",
1080 .api_version = 1,
1081 .init = init,
1082 .cleanup = cleanup,
1083 .scan = scan,
1084 .dev_list = dev_list,
1085 .dev_clear = dev_clear,
1086 .config_get = config_get,
1087 .config_set = config_set,
1088 .config_list = config_list,
1089 .dev_open = dev_open,
1090 .dev_close = dev_close,
1091 .dev_acquisition_start = dev_acquisition_start,
1092 .dev_acquisition_stop = dev_acquisition_stop,
1093 .priv = NULL,
1094};
Hardware access and backend lib