]>
Commit | Line | Data |
---|---|---|
1 | /* | |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, | |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
7 | * | |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | /* | |
23 | * ASIX SIGMA/SIGMA2 logic analyzer driver | |
24 | */ | |
25 | ||
26 | #include <config.h> | |
27 | #include "protocol.h" | |
28 | ||
29 | #define USB_VENDOR 0xa600 | |
30 | #define USB_PRODUCT 0xa000 | |
31 | #define USB_DESCRIPTION "ASIX SIGMA" | |
32 | #define USB_VENDOR_NAME "ASIX" | |
33 | #define USB_MODEL_NAME "SIGMA" | |
34 | ||
35 | /* | |
36 | * The ASIX Sigma supports arbitrary integer frequency divider in | |
37 | * the 50MHz mode. The divider is in range 1...256 , allowing for | |
38 | * very precise sampling rate selection. This driver supports only | |
39 | * a subset of the sampling rates. | |
40 | */ | |
41 | SR_PRIV const uint64_t samplerates[] = { | |
42 | SR_KHZ(200), /* div=250 */ | |
43 | SR_KHZ(250), /* div=200 */ | |
44 | SR_KHZ(500), /* div=100 */ | |
45 | SR_MHZ(1), /* div=50 */ | |
46 | SR_MHZ(5), /* div=10 */ | |
47 | SR_MHZ(10), /* div=5 */ | |
48 | SR_MHZ(25), /* div=2 */ | |
49 | SR_MHZ(50), /* div=1 */ | |
50 | SR_MHZ(100), /* Special FW needed */ | |
51 | SR_MHZ(200), /* Special FW needed */ | |
52 | }; | |
53 | ||
54 | SR_PRIV const size_t samplerates_count = ARRAY_SIZE(samplerates); | |
55 | ||
56 | static const char sigma_firmware_files[][24] = { | |
57 | /* 50 MHz, supports 8 bit fractions */ | |
58 | "asix-sigma-50.fw", | |
59 | /* 100 MHz */ | |
60 | "asix-sigma-100.fw", | |
61 | /* 200 MHz */ | |
62 | "asix-sigma-200.fw", | |
63 | /* Synchronous clock from pin */ | |
64 | "asix-sigma-50sync.fw", | |
65 | /* Frequency counter */ | |
66 | "asix-sigma-phasor.fw", | |
67 | }; | |
68 | ||
69 | static int sigma_read(void *buf, size_t size, struct dev_context *devc) | |
70 | { | |
71 | int ret; | |
72 | ||
73 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); | |
74 | if (ret < 0) { | |
75 | sr_err("ftdi_read_data failed: %s", | |
76 | ftdi_get_error_string(&devc->ftdic)); | |
77 | } | |
78 | ||
79 | return ret; | |
80 | } | |
81 | ||
82 | static int sigma_write(void *buf, size_t size, struct dev_context *devc) | |
83 | { | |
84 | int ret; | |
85 | ||
86 | ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); | |
87 | if (ret < 0) { | |
88 | sr_err("ftdi_write_data failed: %s", | |
89 | ftdi_get_error_string(&devc->ftdic)); | |
90 | } else if ((size_t) ret != size) { | |
91 | sr_err("ftdi_write_data did not complete write."); | |
92 | } | |
93 | ||
94 | return ret; | |
95 | } | |
96 | ||
97 | /* | |
98 | * NOTE: We chose the buffer size to be large enough to hold any write to the | |
99 | * device. We still print a message just in case. | |
100 | */ | |
101 | SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, | |
102 | struct dev_context *devc) | |
103 | { | |
104 | size_t i; | |
105 | uint8_t buf[80]; | |
106 | int idx = 0; | |
107 | ||
108 | if ((2 * len + 2) > sizeof(buf)) { | |
109 | sr_err("Attempted to write %zu bytes, but buffer is too small.", | |
110 | len); | |
111 | return SR_ERR_BUG; | |
112 | } | |
113 | ||
114 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
115 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
116 | ||
117 | for (i = 0; i < len; i++) { | |
118 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); | |
119 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
120 | } | |
121 | ||
122 | return sigma_write(buf, idx, devc); | |
123 | } | |
124 | ||
125 | SR_PRIV int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc) | |
126 | { | |
127 | return sigma_write_register(reg, &value, 1, devc); | |
128 | } | |
129 | ||
130 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, | |
131 | struct dev_context *devc) | |
132 | { | |
133 | uint8_t buf[3]; | |
134 | ||
135 | buf[0] = REG_ADDR_LOW | (reg & 0xf); | |
136 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
137 | buf[2] = REG_READ_ADDR; | |
138 | ||
139 | sigma_write(buf, sizeof(buf), devc); | |
140 | ||
141 | return sigma_read(data, len, devc); | |
142 | } | |
143 | ||
144 | static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc) | |
145 | { | |
146 | uint8_t value; | |
147 | ||
148 | if (1 != sigma_read_register(reg, &value, 1, devc)) { | |
149 | sr_err("sigma_get_register: 1 byte expected"); | |
150 | return 0; | |
151 | } | |
152 | ||
153 | return value; | |
154 | } | |
155 | ||
156 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, | |
157 | struct dev_context *devc) | |
158 | { | |
159 | uint8_t buf[] = { | |
160 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
161 | ||
162 | REG_READ_ADDR | NEXT_REG, | |
163 | REG_READ_ADDR | NEXT_REG, | |
164 | REG_READ_ADDR | NEXT_REG, | |
165 | REG_READ_ADDR | NEXT_REG, | |
166 | REG_READ_ADDR | NEXT_REG, | |
167 | REG_READ_ADDR | NEXT_REG, | |
168 | }; | |
169 | uint8_t result[6]; | |
170 | ||
171 | sigma_write(buf, sizeof(buf), devc); | |
172 | ||
173 | sigma_read(result, sizeof(result), devc); | |
174 | ||
175 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
176 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
177 | ||
178 | /* Not really sure why this must be done, but according to spec. */ | |
179 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
180 | *stoppos -= 64; | |
181 | ||
182 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
183 | *triggerpos -= 64; | |
184 | ||
185 | return 1; | |
186 | } | |
187 | ||
188 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, | |
189 | uint8_t *data, struct dev_context *devc) | |
190 | { | |
191 | size_t i; | |
192 | uint8_t buf[4096]; | |
193 | int idx = 0; | |
194 | ||
195 | /* Send the startchunk. Index start with 1. */ | |
196 | buf[0] = startchunk >> 8; | |
197 | buf[1] = startchunk & 0xff; | |
198 | sigma_write_register(WRITE_MEMROW, buf, 2, devc); | |
199 | ||
200 | /* Read the DRAM. */ | |
201 | buf[idx++] = REG_DRAM_BLOCK; | |
202 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
203 | ||
204 | for (i = 0; i < numchunks; i++) { | |
205 | /* Alternate bit to copy from DRAM to cache. */ | |
206 | if (i != (numchunks - 1)) | |
207 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
208 | ||
209 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
210 | ||
211 | if (i != (numchunks - 1)) | |
212 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
213 | } | |
214 | ||
215 | sigma_write(buf, idx, devc); | |
216 | ||
217 | return sigma_read(data, numchunks * CHUNK_SIZE, devc); | |
218 | } | |
219 | ||
220 | /* Upload trigger look-up tables to Sigma. */ | |
221 | SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc) | |
222 | { | |
223 | int i; | |
224 | uint8_t tmp[2]; | |
225 | uint16_t bit; | |
226 | ||
227 | /* Transpose the table and send to Sigma. */ | |
228 | for (i = 0; i < 16; i++) { | |
229 | bit = 1 << i; | |
230 | ||
231 | tmp[0] = tmp[1] = 0; | |
232 | ||
233 | if (lut->m2d[0] & bit) | |
234 | tmp[0] |= 0x01; | |
235 | if (lut->m2d[1] & bit) | |
236 | tmp[0] |= 0x02; | |
237 | if (lut->m2d[2] & bit) | |
238 | tmp[0] |= 0x04; | |
239 | if (lut->m2d[3] & bit) | |
240 | tmp[0] |= 0x08; | |
241 | ||
242 | if (lut->m3 & bit) | |
243 | tmp[0] |= 0x10; | |
244 | if (lut->m3s & bit) | |
245 | tmp[0] |= 0x20; | |
246 | if (lut->m4 & bit) | |
247 | tmp[0] |= 0x40; | |
248 | ||
249 | if (lut->m0d[0] & bit) | |
250 | tmp[1] |= 0x01; | |
251 | if (lut->m0d[1] & bit) | |
252 | tmp[1] |= 0x02; | |
253 | if (lut->m0d[2] & bit) | |
254 | tmp[1] |= 0x04; | |
255 | if (lut->m0d[3] & bit) | |
256 | tmp[1] |= 0x08; | |
257 | ||
258 | if (lut->m1d[0] & bit) | |
259 | tmp[1] |= 0x10; | |
260 | if (lut->m1d[1] & bit) | |
261 | tmp[1] |= 0x20; | |
262 | if (lut->m1d[2] & bit) | |
263 | tmp[1] |= 0x40; | |
264 | if (lut->m1d[3] & bit) | |
265 | tmp[1] |= 0x80; | |
266 | ||
267 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), | |
268 | devc); | |
269 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); | |
270 | } | |
271 | ||
272 | /* Send the parameters */ | |
273 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
274 | sizeof(lut->params), devc); | |
275 | ||
276 | return SR_OK; | |
277 | } | |
278 | ||
279 | SR_PRIV void sigma_clear_helper(void *priv) | |
280 | { | |
281 | struct dev_context *devc; | |
282 | ||
283 | devc = priv; | |
284 | ||
285 | ftdi_deinit(&devc->ftdic); | |
286 | } | |
287 | ||
288 | /* | |
289 | * Configure the FPGA for bitbang mode. | |
290 | * This sequence is documented in section 2. of the ASIX Sigma programming | |
291 | * manual. This sequence is necessary to configure the FPGA in the Sigma | |
292 | * into Bitbang mode, in which it can be programmed with the firmware. | |
293 | */ | |
294 | static int sigma_fpga_init_bitbang(struct dev_context *devc) | |
295 | { | |
296 | uint8_t suicide[] = { | |
297 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
298 | }; | |
299 | uint8_t init_array[] = { | |
300 | 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, | |
301 | 0x01, 0x01, | |
302 | }; | |
303 | int i, ret, timeout = (10 * 1000); | |
304 | uint8_t data; | |
305 | ||
306 | /* Section 2. part 1), do the FPGA suicide. */ | |
307 | sigma_write(suicide, sizeof(suicide), devc); | |
308 | sigma_write(suicide, sizeof(suicide), devc); | |
309 | sigma_write(suicide, sizeof(suicide), devc); | |
310 | sigma_write(suicide, sizeof(suicide), devc); | |
311 | ||
312 | /* Section 2. part 2), do pulse on D1. */ | |
313 | sigma_write(init_array, sizeof(init_array), devc); | |
314 | ftdi_usb_purge_buffers(&devc->ftdic); | |
315 | ||
316 | /* Wait until the FPGA asserts D6/INIT_B. */ | |
317 | for (i = 0; i < timeout; i++) { | |
318 | ret = sigma_read(&data, 1, devc); | |
319 | if (ret < 0) | |
320 | return ret; | |
321 | /* Test if pin D6 got asserted. */ | |
322 | if (data & (1 << 5)) | |
323 | return 0; | |
324 | /* The D6 was not asserted yet, wait a bit. */ | |
325 | g_usleep(10 * 1000); | |
326 | } | |
327 | ||
328 | return SR_ERR_TIMEOUT; | |
329 | } | |
330 | ||
331 | /* | |
332 | * Configure the FPGA for logic-analyzer mode. | |
333 | */ | |
334 | static int sigma_fpga_init_la(struct dev_context *devc) | |
335 | { | |
336 | /* Initialize the logic analyzer mode. */ | |
337 | uint8_t logic_mode_start[] = { | |
338 | REG_ADDR_LOW | (READ_ID & 0xf), | |
339 | REG_ADDR_HIGH | (READ_ID >> 8), | |
340 | REG_READ_ADDR, /* Read ID register. */ | |
341 | ||
342 | REG_ADDR_LOW | (WRITE_TEST & 0xf), | |
343 | REG_DATA_LOW | 0x5, | |
344 | REG_DATA_HIGH_WRITE | 0x5, | |
345 | REG_READ_ADDR, /* Read scratch register. */ | |
346 | ||
347 | REG_DATA_LOW | 0xa, | |
348 | REG_DATA_HIGH_WRITE | 0xa, | |
349 | REG_READ_ADDR, /* Read scratch register. */ | |
350 | ||
351 | REG_ADDR_LOW | (WRITE_MODE & 0xf), | |
352 | REG_DATA_LOW | 0x0, | |
353 | REG_DATA_HIGH_WRITE | 0x8, | |
354 | }; | |
355 | ||
356 | uint8_t result[3]; | |
357 | int ret; | |
358 | ||
359 | /* Initialize the logic analyzer mode. */ | |
360 | sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); | |
361 | ||
362 | /* Expect a 3 byte reply since we issued three READ requests. */ | |
363 | ret = sigma_read(result, 3, devc); | |
364 | if (ret != 3) | |
365 | goto err; | |
366 | ||
367 | if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) | |
368 | goto err; | |
369 | ||
370 | return SR_OK; | |
371 | err: | |
372 | sr_err("Configuration failed. Invalid reply received."); | |
373 | return SR_ERR; | |
374 | } | |
375 | ||
376 | /* | |
377 | * Read the firmware from a file and transform it into a series of bitbang | |
378 | * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d | |
379 | * by the caller of this function. | |
380 | */ | |
381 | static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name, | |
382 | uint8_t **bb_cmd, gsize *bb_cmd_size) | |
383 | { | |
384 | size_t i, file_size, bb_size; | |
385 | char *firmware; | |
386 | uint8_t *bb_stream, *bbs; | |
387 | uint32_t imm; | |
388 | int bit, v; | |
389 | int ret = SR_OK; | |
390 | ||
391 | /* Retrieve the on-disk firmware file content. */ | |
392 | firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE, | |
393 | name, &file_size, 256 * 1024); | |
394 | if (!firmware) | |
395 | return SR_ERR; | |
396 | ||
397 | /* Unscramble the file content (XOR with "random" sequence). */ | |
398 | imm = 0x3f6df2ab; | |
399 | for (i = 0; i < file_size; i++) { | |
400 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
401 | firmware[i] ^= imm & 0xff; | |
402 | } | |
403 | ||
404 | /* | |
405 | * Generate a sequence of bitbang samples. With two samples per | |
406 | * FPGA configuration bit, providing the level for the DIN signal | |
407 | * as well as two edges for CCLK. See Xilinx UG332 for details | |
408 | * ("slave serial" mode). | |
409 | * | |
410 | * Note that CCLK is inverted in hardware. That's why the | |
411 | * respective bit is first set and then cleared in the bitbang | |
412 | * sample sets. So that the DIN level will be stable when the | |
413 | * data gets sampled at the rising CCLK edge, and the signals' | |
414 | * setup time constraint will be met. | |
415 | * | |
416 | * The caller will put the FPGA into download mode, will send | |
417 | * the bitbang samples, and release the allocated memory. | |
418 | */ | |
419 | bb_size = file_size * 8 * 2; | |
420 | bb_stream = (uint8_t *)g_try_malloc(bb_size); | |
421 | if (!bb_stream) { | |
422 | sr_err("%s: Failed to allocate bitbang stream", __func__); | |
423 | ret = SR_ERR_MALLOC; | |
424 | goto exit; | |
425 | } | |
426 | bbs = bb_stream; | |
427 | for (i = 0; i < file_size; i++) { | |
428 | for (bit = 7; bit >= 0; bit--) { | |
429 | v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00; | |
430 | *bbs++ = v | 0x01; | |
431 | *bbs++ = v; | |
432 | } | |
433 | } | |
434 | ||
435 | /* The transformation completed successfully, return the result. */ | |
436 | *bb_cmd = bb_stream; | |
437 | *bb_cmd_size = bb_size; | |
438 | ||
439 | exit: | |
440 | g_free(firmware); | |
441 | return ret; | |
442 | } | |
443 | ||
444 | static int upload_firmware(struct sr_context *ctx, | |
445 | int firmware_idx, struct dev_context *devc) | |
446 | { | |
447 | int ret; | |
448 | unsigned char *buf; | |
449 | unsigned char pins; | |
450 | size_t buf_size; | |
451 | const char *firmware = sigma_firmware_files[firmware_idx]; | |
452 | struct ftdi_context *ftdic = &devc->ftdic; | |
453 | ||
454 | /* Make sure it's an ASIX SIGMA. */ | |
455 | ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT, | |
456 | USB_DESCRIPTION, NULL); | |
457 | if (ret < 0) { | |
458 | sr_err("ftdi_usb_open failed: %s", | |
459 | ftdi_get_error_string(ftdic)); | |
460 | return 0; | |
461 | } | |
462 | ||
463 | ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG); | |
464 | if (ret < 0) { | |
465 | sr_err("ftdi_set_bitmode failed: %s", | |
466 | ftdi_get_error_string(ftdic)); | |
467 | return 0; | |
468 | } | |
469 | ||
470 | /* Four times the speed of sigmalogan - Works well. */ | |
471 | ret = ftdi_set_baudrate(ftdic, 750 * 1000); | |
472 | if (ret < 0) { | |
473 | sr_err("ftdi_set_baudrate failed: %s", | |
474 | ftdi_get_error_string(ftdic)); | |
475 | return 0; | |
476 | } | |
477 | ||
478 | /* Initialize the FPGA for firmware upload. */ | |
479 | ret = sigma_fpga_init_bitbang(devc); | |
480 | if (ret) | |
481 | return ret; | |
482 | ||
483 | /* Prepare firmware. */ | |
484 | ret = sigma_fw_2_bitbang(ctx, firmware, &buf, &buf_size); | |
485 | if (ret != SR_OK) { | |
486 | sr_err("An error occurred while reading the firmware: %s", | |
487 | firmware); | |
488 | return ret; | |
489 | } | |
490 | ||
491 | /* Upload firmware. */ | |
492 | sr_info("Uploading firmware file '%s'.", firmware); | |
493 | sigma_write(buf, buf_size, devc); | |
494 | ||
495 | g_free(buf); | |
496 | ||
497 | ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET); | |
498 | if (ret < 0) { | |
499 | sr_err("ftdi_set_bitmode failed: %s", | |
500 | ftdi_get_error_string(ftdic)); | |
501 | return SR_ERR; | |
502 | } | |
503 | ||
504 | ftdi_usb_purge_buffers(ftdic); | |
505 | ||
506 | /* Discard garbage. */ | |
507 | while (sigma_read(&pins, 1, devc) == 1) | |
508 | ; | |
509 | ||
510 | /* Initialize the FPGA for logic-analyzer mode. */ | |
511 | ret = sigma_fpga_init_la(devc); | |
512 | if (ret != SR_OK) | |
513 | return ret; | |
514 | ||
515 | devc->cur_firmware = firmware_idx; | |
516 | ||
517 | sr_info("Firmware uploaded."); | |
518 | ||
519 | return SR_OK; | |
520 | } | |
521 | ||
522 | /* | |
523 | * Sigma doesn't support limiting the number of samples, so we have to | |
524 | * translate the number and the samplerate to an elapsed time. | |
525 | * | |
526 | * In addition we need to ensure that the last data cluster has passed | |
527 | * the hardware pipeline, and became available to the PC side. With RLE | |
528 | * compression up to 327ms could pass before another cluster accumulates | |
529 | * at 200kHz samplerate when input pins don't change. | |
530 | */ | |
531 | SR_PRIV uint64_t sigma_limit_samples_to_msec(const struct dev_context *devc, | |
532 | uint64_t limit_samples) | |
533 | { | |
534 | uint64_t limit_msec; | |
535 | uint64_t worst_cluster_time_ms; | |
536 | ||
537 | limit_msec = limit_samples * 1000 / devc->cur_samplerate; | |
538 | worst_cluster_time_ms = 65536 * 1000 / devc->cur_samplerate; | |
539 | /* | |
540 | * One cluster time is not enough to flush pipeline when sampling | |
541 | * grounded pins with 1 sample limit at 200kHz. Hence the 2* fix. | |
542 | */ | |
543 | return limit_msec + 2 * worst_cluster_time_ms; | |
544 | } | |
545 | ||
546 | SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) | |
547 | { | |
548 | struct dev_context *devc; | |
549 | struct drv_context *drvc; | |
550 | size_t i; | |
551 | int ret; | |
552 | ||
553 | devc = sdi->priv; | |
554 | drvc = sdi->driver->context; | |
555 | ret = SR_OK; | |
556 | ||
557 | /* Reject rates that are not in the list of supported rates. */ | |
558 | for (i = 0; i < samplerates_count; i++) { | |
559 | if (samplerates[i] == samplerate) | |
560 | break; | |
561 | } | |
562 | if (i >= samplerates_count || samplerates[i] == 0) | |
563 | return SR_ERR_SAMPLERATE; | |
564 | ||
565 | /* | |
566 | * Depending on the samplerates of 200/100/50- MHz, specific | |
567 | * firmware is required and higher rates might limit the set | |
568 | * of available channels. | |
569 | */ | |
570 | if (samplerate <= SR_MHZ(50)) { | |
571 | ret = upload_firmware(drvc->sr_ctx, 0, devc); | |
572 | devc->num_channels = 16; | |
573 | } else if (samplerate == SR_MHZ(100)) { | |
574 | ret = upload_firmware(drvc->sr_ctx, 1, devc); | |
575 | devc->num_channels = 8; | |
576 | } else if (samplerate == SR_MHZ(200)) { | |
577 | ret = upload_firmware(drvc->sr_ctx, 2, devc); | |
578 | devc->num_channels = 4; | |
579 | } | |
580 | ||
581 | /* | |
582 | * Derive the sample period from the sample rate as well as the | |
583 | * number of samples that the device will communicate within | |
584 | * an "event" (memory organization internal to the device). | |
585 | */ | |
586 | if (ret == SR_OK) { | |
587 | devc->cur_samplerate = samplerate; | |
588 | devc->period_ps = 1000000000000ULL / samplerate; | |
589 | devc->samples_per_event = 16 / devc->num_channels; | |
590 | devc->state.state = SIGMA_IDLE; | |
591 | } | |
592 | ||
593 | /* | |
594 | * Support for "limit_samples" is implemented by stopping | |
595 | * acquisition after a corresponding period of time. | |
596 | * Re-calculate that period of time, in case the limit is | |
597 | * set first and the samplerate gets (re-)configured later. | |
598 | */ | |
599 | if (ret == SR_OK && devc->limit_samples) { | |
600 | uint64_t msecs; | |
601 | msecs = sigma_limit_samples_to_msec(devc, devc->limit_samples); | |
602 | devc->limit_msec = msecs; | |
603 | } | |
604 | ||
605 | return ret; | |
606 | } | |
607 | ||
608 | /* | |
609 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
610 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
611 | * in addition to value/mask trigger for any number of channels. | |
612 | * | |
613 | * The Sigma supports complex triggers using boolean expressions, but this | |
614 | * has not been implemented yet. | |
615 | */ | |
616 | SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi) | |
617 | { | |
618 | struct dev_context *devc; | |
619 | struct sr_trigger *trigger; | |
620 | struct sr_trigger_stage *stage; | |
621 | struct sr_trigger_match *match; | |
622 | const GSList *l, *m; | |
623 | int channelbit, trigger_set; | |
624 | ||
625 | devc = sdi->priv; | |
626 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); | |
627 | if (!(trigger = sr_session_trigger_get(sdi->session))) | |
628 | return SR_OK; | |
629 | ||
630 | trigger_set = 0; | |
631 | for (l = trigger->stages; l; l = l->next) { | |
632 | stage = l->data; | |
633 | for (m = stage->matches; m; m = m->next) { | |
634 | match = m->data; | |
635 | if (!match->channel->enabled) | |
636 | /* Ignore disabled channels with a trigger. */ | |
637 | continue; | |
638 | channelbit = 1 << (match->channel->index); | |
639 | if (devc->cur_samplerate >= SR_MHZ(100)) { | |
640 | /* Fast trigger support. */ | |
641 | if (trigger_set) { | |
642 | sr_err("Only a single pin trigger is " | |
643 | "supported in 100 and 200MHz mode."); | |
644 | return SR_ERR; | |
645 | } | |
646 | if (match->match == SR_TRIGGER_FALLING) | |
647 | devc->trigger.fallingmask |= channelbit; | |
648 | else if (match->match == SR_TRIGGER_RISING) | |
649 | devc->trigger.risingmask |= channelbit; | |
650 | else { | |
651 | sr_err("Only rising/falling trigger is " | |
652 | "supported in 100 and 200MHz mode."); | |
653 | return SR_ERR; | |
654 | } | |
655 | ||
656 | trigger_set++; | |
657 | } else { | |
658 | /* Simple trigger support (event). */ | |
659 | if (match->match == SR_TRIGGER_ONE) { | |
660 | devc->trigger.simplevalue |= channelbit; | |
661 | devc->trigger.simplemask |= channelbit; | |
662 | } | |
663 | else if (match->match == SR_TRIGGER_ZERO) { | |
664 | devc->trigger.simplevalue &= ~channelbit; | |
665 | devc->trigger.simplemask |= channelbit; | |
666 | } | |
667 | else if (match->match == SR_TRIGGER_FALLING) { | |
668 | devc->trigger.fallingmask |= channelbit; | |
669 | trigger_set++; | |
670 | } | |
671 | else if (match->match == SR_TRIGGER_RISING) { | |
672 | devc->trigger.risingmask |= channelbit; | |
673 | trigger_set++; | |
674 | } | |
675 | ||
676 | /* | |
677 | * Actually, Sigma supports 2 rising/falling triggers, | |
678 | * but they are ORed and the current trigger syntax | |
679 | * does not permit ORed triggers. | |
680 | */ | |
681 | if (trigger_set > 1) { | |
682 | sr_err("Only 1 rising/falling trigger " | |
683 | "is supported."); | |
684 | return SR_ERR; | |
685 | } | |
686 | } | |
687 | } | |
688 | } | |
689 | ||
690 | return SR_OK; | |
691 | } | |
692 | ||
693 | ||
694 | /* Software trigger to determine exact trigger position. */ | |
695 | static int get_trigger_offset(uint8_t *samples, uint16_t last_sample, | |
696 | struct sigma_trigger *t) | |
697 | { | |
698 | int i; | |
699 | uint16_t sample = 0; | |
700 | ||
701 | for (i = 0; i < 8; i++) { | |
702 | if (i > 0) | |
703 | last_sample = sample; | |
704 | sample = samples[2 * i] | (samples[2 * i + 1] << 8); | |
705 | ||
706 | /* Simple triggers. */ | |
707 | if ((sample & t->simplemask) != t->simplevalue) | |
708 | continue; | |
709 | ||
710 | /* Rising edge. */ | |
711 | if (((last_sample & t->risingmask) != 0) || | |
712 | ((sample & t->risingmask) != t->risingmask)) | |
713 | continue; | |
714 | ||
715 | /* Falling edge. */ | |
716 | if ((last_sample & t->fallingmask) != t->fallingmask || | |
717 | (sample & t->fallingmask) != 0) | |
718 | continue; | |
719 | ||
720 | break; | |
721 | } | |
722 | ||
723 | /* If we did not match, return original trigger pos. */ | |
724 | return i & 0x7; | |
725 | } | |
726 | ||
727 | /* | |
728 | * Return the timestamp of "DRAM cluster". | |
729 | */ | |
730 | static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster) | |
731 | { | |
732 | return (cluster->timestamp_hi << 8) | cluster->timestamp_lo; | |
733 | } | |
734 | ||
735 | static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster, | |
736 | unsigned int events_in_cluster, | |
737 | unsigned int triggered, | |
738 | struct sr_dev_inst *sdi) | |
739 | { | |
740 | struct dev_context *devc = sdi->priv; | |
741 | struct sigma_state *ss = &devc->state; | |
742 | struct sr_datafeed_packet packet; | |
743 | struct sr_datafeed_logic logic; | |
744 | uint16_t tsdiff, ts; | |
745 | uint8_t samples[2048]; | |
746 | unsigned int i; | |
747 | ||
748 | ts = sigma_dram_cluster_ts(dram_cluster); | |
749 | tsdiff = ts - ss->lastts; | |
750 | ss->lastts = ts + EVENTS_PER_CLUSTER; | |
751 | ||
752 | packet.type = SR_DF_LOGIC; | |
753 | packet.payload = &logic; | |
754 | logic.unitsize = 2; | |
755 | logic.data = samples; | |
756 | ||
757 | /* | |
758 | * First of all, send Sigrok a copy of the last sample from | |
759 | * previous cluster as many times as needed to make up for | |
760 | * the differential characteristics of data we get from the | |
761 | * Sigma. Sigrok needs one sample of data per period. | |
762 | * | |
763 | * One DRAM cluster contains a timestamp and seven samples, | |
764 | * the units of timestamp are "devc->period_ps" , the first | |
765 | * sample in the cluster happens at the time of the timestamp | |
766 | * and the remaining samples happen at timestamp +1...+6 . | |
767 | */ | |
768 | for (ts = 0; ts < tsdiff; ts++) { | |
769 | i = ts % 1024; | |
770 | samples[2 * i + 0] = ss->lastsample & 0xff; | |
771 | samples[2 * i + 1] = ss->lastsample >> 8; | |
772 | ||
773 | /* | |
774 | * If we have 1024 samples ready or we're at the | |
775 | * end of submitting the padding samples, submit | |
776 | * the packet to Sigrok. | |
777 | */ | |
778 | if ((i == 1023) || (ts == tsdiff - 1)) { | |
779 | logic.length = (i + 1) * logic.unitsize; | |
780 | sr_session_send(sdi, &packet); | |
781 | } | |
782 | } | |
783 | ||
784 | /* | |
785 | * Parse the samples in current cluster and prepare them | |
786 | * to be submitted to Sigrok. | |
787 | */ | |
788 | for (i = 0; i < events_in_cluster; i++) { | |
789 | samples[2 * i + 1] = dram_cluster->samples[i].sample_lo; | |
790 | samples[2 * i + 0] = dram_cluster->samples[i].sample_hi; | |
791 | } | |
792 | ||
793 | /* Send data up to trigger point (if triggered). */ | |
794 | int trigger_offset = 0; | |
795 | if (triggered) { | |
796 | /* | |
797 | * Trigger is not always accurate to sample because of | |
798 | * pipeline delay. However, it always triggers before | |
799 | * the actual event. We therefore look at the next | |
800 | * samples to pinpoint the exact position of the trigger. | |
801 | */ | |
802 | trigger_offset = get_trigger_offset(samples, | |
803 | ss->lastsample, &devc->trigger); | |
804 | ||
805 | if (trigger_offset > 0) { | |
806 | packet.type = SR_DF_LOGIC; | |
807 | logic.length = trigger_offset * logic.unitsize; | |
808 | sr_session_send(sdi, &packet); | |
809 | events_in_cluster -= trigger_offset; | |
810 | } | |
811 | ||
812 | /* Only send trigger if explicitly enabled. */ | |
813 | if (devc->use_triggers) { | |
814 | packet.type = SR_DF_TRIGGER; | |
815 | sr_session_send(sdi, &packet); | |
816 | } | |
817 | } | |
818 | ||
819 | if (events_in_cluster > 0) { | |
820 | packet.type = SR_DF_LOGIC; | |
821 | logic.length = events_in_cluster * logic.unitsize; | |
822 | logic.data = samples + (trigger_offset * logic.unitsize); | |
823 | sr_session_send(sdi, &packet); | |
824 | } | |
825 | ||
826 | ss->lastsample = | |
827 | samples[2 * (events_in_cluster - 1) + 0] | | |
828 | (samples[2 * (events_in_cluster - 1) + 1] << 8); | |
829 | ||
830 | } | |
831 | ||
832 | /* | |
833 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. | |
834 | * Each event is 20ns apart, and can contain multiple samples. | |
835 | * | |
836 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
837 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
838 | * For 50 MHz and below, events contain one sample for each channel, | |
839 | * spread 20 ns apart. | |
840 | */ | |
841 | static int decode_chunk_ts(struct sigma_dram_line *dram_line, | |
842 | uint16_t events_in_line, | |
843 | uint32_t trigger_event, | |
844 | struct sr_dev_inst *sdi) | |
845 | { | |
846 | struct sigma_dram_cluster *dram_cluster; | |
847 | struct dev_context *devc = sdi->priv; | |
848 | unsigned int clusters_in_line = | |
849 | (events_in_line + (EVENTS_PER_CLUSTER - 1)) / EVENTS_PER_CLUSTER; | |
850 | unsigned int events_in_cluster; | |
851 | unsigned int i; | |
852 | uint32_t trigger_cluster = ~0, triggered = 0; | |
853 | ||
854 | /* Check if trigger is in this chunk. */ | |
855 | if (trigger_event < (64 * 7)) { | |
856 | if (devc->cur_samplerate <= SR_MHZ(50)) { | |
857 | trigger_event -= MIN(EVENTS_PER_CLUSTER - 1, | |
858 | trigger_event); | |
859 | } | |
860 | ||
861 | /* Find in which cluster the trigger occurred. */ | |
862 | trigger_cluster = trigger_event / EVENTS_PER_CLUSTER; | |
863 | } | |
864 | ||
865 | /* For each full DRAM cluster. */ | |
866 | for (i = 0; i < clusters_in_line; i++) { | |
867 | dram_cluster = &dram_line->cluster[i]; | |
868 | ||
869 | /* The last cluster might not be full. */ | |
870 | if ((i == clusters_in_line - 1) && | |
871 | (events_in_line % EVENTS_PER_CLUSTER)) { | |
872 | events_in_cluster = events_in_line % EVENTS_PER_CLUSTER; | |
873 | } else { | |
874 | events_in_cluster = EVENTS_PER_CLUSTER; | |
875 | } | |
876 | ||
877 | triggered = (i == trigger_cluster); | |
878 | sigma_decode_dram_cluster(dram_cluster, events_in_cluster, | |
879 | triggered, sdi); | |
880 | } | |
881 | ||
882 | return SR_OK; | |
883 | } | |
884 | ||
885 | static int download_capture(struct sr_dev_inst *sdi) | |
886 | { | |
887 | struct dev_context *devc = sdi->priv; | |
888 | const uint32_t chunks_per_read = 32; | |
889 | struct sigma_dram_line *dram_line; | |
890 | int bufsz; | |
891 | uint32_t stoppos, triggerpos; | |
892 | uint8_t modestatus; | |
893 | ||
894 | uint32_t i; | |
895 | uint32_t dl_lines_total, dl_lines_curr, dl_lines_done; | |
896 | uint32_t dl_events_in_line = 64 * 7; | |
897 | uint32_t trg_line = ~0, trg_event = ~0; | |
898 | ||
899 | dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line)); | |
900 | if (!dram_line) | |
901 | return FALSE; | |
902 | ||
903 | sr_info("Downloading sample data."); | |
904 | ||
905 | /* Stop acquisition. */ | |
906 | sigma_set_register(WRITE_MODE, 0x11, devc); | |
907 | ||
908 | /* Set SDRAM Read Enable. */ | |
909 | sigma_set_register(WRITE_MODE, 0x02, devc); | |
910 | ||
911 | /* Get the current position. */ | |
912 | sigma_read_pos(&stoppos, &triggerpos, devc); | |
913 | ||
914 | /* Check if trigger has fired. */ | |
915 | modestatus = sigma_get_register(READ_MODE, devc); | |
916 | if (modestatus & 0x20) { | |
917 | trg_line = triggerpos >> 9; | |
918 | trg_event = triggerpos & 0x1ff; | |
919 | } | |
920 | ||
921 | /* | |
922 | * Determine how many 1024b "DRAM lines" do we need to read from the | |
923 | * Sigma so we have a complete set of samples. Note that the last | |
924 | * line can be only partial, containing less than 64 clusters. | |
925 | */ | |
926 | dl_lines_total = (stoppos >> 9) + 1; | |
927 | ||
928 | dl_lines_done = 0; | |
929 | ||
930 | while (dl_lines_total > dl_lines_done) { | |
931 | /* We can download only up-to 32 DRAM lines in one go! */ | |
932 | dl_lines_curr = MIN(chunks_per_read, dl_lines_total); | |
933 | ||
934 | bufsz = sigma_read_dram(dl_lines_done, dl_lines_curr, | |
935 | (uint8_t *)dram_line, devc); | |
936 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ | |
937 | (void)bufsz; | |
938 | ||
939 | /* This is the first DRAM line, so find the initial timestamp. */ | |
940 | if (dl_lines_done == 0) { | |
941 | devc->state.lastts = | |
942 | sigma_dram_cluster_ts(&dram_line[0].cluster[0]); | |
943 | devc->state.lastsample = 0; | |
944 | } | |
945 | ||
946 | for (i = 0; i < dl_lines_curr; i++) { | |
947 | uint32_t trigger_event = ~0; | |
948 | /* The last "DRAM line" can be only partially full. */ | |
949 | if (dl_lines_done + i == dl_lines_total - 1) | |
950 | dl_events_in_line = stoppos & 0x1ff; | |
951 | ||
952 | /* Test if the trigger happened on this line. */ | |
953 | if (dl_lines_done + i == trg_line) | |
954 | trigger_event = trg_event; | |
955 | ||
956 | decode_chunk_ts(dram_line + i, dl_events_in_line, | |
957 | trigger_event, sdi); | |
958 | } | |
959 | ||
960 | dl_lines_done += dl_lines_curr; | |
961 | } | |
962 | ||
963 | std_session_send_df_end(sdi); | |
964 | ||
965 | sdi->driver->dev_acquisition_stop(sdi); | |
966 | ||
967 | g_free(dram_line); | |
968 | ||
969 | return TRUE; | |
970 | } | |
971 | ||
972 | /* | |
973 | * Handle the Sigma when in CAPTURE mode. This function checks: | |
974 | * - Sampling time ended | |
975 | * - DRAM capacity overflow | |
976 | * This function triggers download of the samples from Sigma | |
977 | * in case either of the above conditions is true. | |
978 | */ | |
979 | static int sigma_capture_mode(struct sr_dev_inst *sdi) | |
980 | { | |
981 | struct dev_context *devc = sdi->priv; | |
982 | ||
983 | uint64_t running_msec; | |
984 | struct timeval tv; | |
985 | ||
986 | uint32_t stoppos, triggerpos; | |
987 | ||
988 | /* Check if the selected sampling duration passed. */ | |
989 | gettimeofday(&tv, 0); | |
990 | running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 + | |
991 | (tv.tv_usec - devc->start_tv.tv_usec) / 1000; | |
992 | if (running_msec >= devc->limit_msec) | |
993 | return download_capture(sdi); | |
994 | ||
995 | /* Get the position in DRAM to which the FPGA is writing now. */ | |
996 | sigma_read_pos(&stoppos, &triggerpos, devc); | |
997 | /* Test if DRAM is full and if so, download the data. */ | |
998 | if ((stoppos >> 9) == 32767) | |
999 | return download_capture(sdi); | |
1000 | ||
1001 | return TRUE; | |
1002 | } | |
1003 | ||
1004 | SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data) | |
1005 | { | |
1006 | struct sr_dev_inst *sdi; | |
1007 | struct dev_context *devc; | |
1008 | ||
1009 | (void)fd; | |
1010 | (void)revents; | |
1011 | ||
1012 | sdi = cb_data; | |
1013 | devc = sdi->priv; | |
1014 | ||
1015 | if (devc->state.state == SIGMA_IDLE) | |
1016 | return TRUE; | |
1017 | ||
1018 | if (devc->state.state == SIGMA_CAPTURE) | |
1019 | return sigma_capture_mode(sdi); | |
1020 | ||
1021 | return TRUE; | |
1022 | } | |
1023 | ||
1024 | /* Build a LUT entry used by the trigger functions. */ | |
1025 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
1026 | { | |
1027 | int i, j, k, bit; | |
1028 | ||
1029 | /* For each quad channel. */ | |
1030 | for (i = 0; i < 4; i++) { | |
1031 | entry[i] = 0xffff; | |
1032 | ||
1033 | /* For each bit in LUT. */ | |
1034 | for (j = 0; j < 16; j++) | |
1035 | ||
1036 | /* For each channel in quad. */ | |
1037 | for (k = 0; k < 4; k++) { | |
1038 | bit = 1 << (i * 4 + k); | |
1039 | ||
1040 | /* Set bit in entry */ | |
1041 | if ((mask & bit) && ((!(value & bit)) != | |
1042 | (!(j & (1 << k))))) | |
1043 | entry[i] &= ~(1 << j); | |
1044 | } | |
1045 | } | |
1046 | } | |
1047 | ||
1048 | /* Add a logical function to LUT mask. */ | |
1049 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1050 | int index, int neg, uint16_t *mask) | |
1051 | { | |
1052 | int i, j; | |
1053 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1054 | ||
1055 | memset(x, 0, 4 * sizeof(int)); | |
1056 | ||
1057 | /* Trigger detect condition. */ | |
1058 | switch (oper) { | |
1059 | case OP_LEVEL: | |
1060 | x[0][1] = 1; | |
1061 | x[1][1] = 1; | |
1062 | break; | |
1063 | case OP_NOT: | |
1064 | x[0][0] = 1; | |
1065 | x[1][0] = 1; | |
1066 | break; | |
1067 | case OP_RISE: | |
1068 | x[0][1] = 1; | |
1069 | break; | |
1070 | case OP_FALL: | |
1071 | x[1][0] = 1; | |
1072 | break; | |
1073 | case OP_RISEFALL: | |
1074 | x[0][1] = 1; | |
1075 | x[1][0] = 1; | |
1076 | break; | |
1077 | case OP_NOTRISE: | |
1078 | x[1][1] = 1; | |
1079 | x[0][0] = 1; | |
1080 | x[1][0] = 1; | |
1081 | break; | |
1082 | case OP_NOTFALL: | |
1083 | x[1][1] = 1; | |
1084 | x[0][0] = 1; | |
1085 | x[0][1] = 1; | |
1086 | break; | |
1087 | case OP_NOTRISEFALL: | |
1088 | x[1][1] = 1; | |
1089 | x[0][0] = 1; | |
1090 | break; | |
1091 | } | |
1092 | ||
1093 | /* Transpose if neg is set. */ | |
1094 | if (neg) { | |
1095 | for (i = 0; i < 2; i++) { | |
1096 | for (j = 0; j < 2; j++) { | |
1097 | tmp = x[i][j]; | |
1098 | x[i][j] = x[1 - i][1 - j]; | |
1099 | x[1 - i][1 - j] = tmp; | |
1100 | } | |
1101 | } | |
1102 | } | |
1103 | ||
1104 | /* Update mask with function. */ | |
1105 | for (i = 0; i < 16; i++) { | |
1106 | a = (i >> (2 * index + 0)) & 1; | |
1107 | b = (i >> (2 * index + 1)) & 1; | |
1108 | ||
1109 | aset = (*mask >> i) & 1; | |
1110 | bset = x[b][a]; | |
1111 | ||
1112 | rset = 0; | |
1113 | if (func == FUNC_AND || func == FUNC_NAND) | |
1114 | rset = aset & bset; | |
1115 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1116 | rset = aset | bset; | |
1117 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1118 | rset = aset ^ bset; | |
1119 | ||
1120 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1121 | rset = !rset; | |
1122 | ||
1123 | *mask &= ~(1 << i); | |
1124 | ||
1125 | if (rset) | |
1126 | *mask |= 1 << i; | |
1127 | } | |
1128 | } | |
1129 | ||
1130 | /* | |
1131 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1132 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1133 | * set at any time, but a full mask and value can be set (0/1). | |
1134 | */ | |
1135 | SR_PRIV int sigma_build_basic_trigger(struct triggerlut *lut, struct dev_context *devc) | |
1136 | { | |
1137 | int i,j; | |
1138 | uint16_t masks[2] = { 0, 0 }; | |
1139 | ||
1140 | memset(lut, 0, sizeof(struct triggerlut)); | |
1141 | ||
1142 | /* Constant for simple triggers. */ | |
1143 | lut->m4 = 0xa000; | |
1144 | ||
1145 | /* Value/mask trigger support. */ | |
1146 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, | |
1147 | lut->m2d); | |
1148 | ||
1149 | /* Rise/fall trigger support. */ | |
1150 | for (i = 0, j = 0; i < 16; i++) { | |
1151 | if (devc->trigger.risingmask & (1 << i) || | |
1152 | devc->trigger.fallingmask & (1 << i)) | |
1153 | masks[j++] = 1 << i; | |
1154 | } | |
1155 | ||
1156 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1157 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1158 | ||
1159 | /* Add glue logic */ | |
1160 | if (masks[0] || masks[1]) { | |
1161 | /* Transition trigger. */ | |
1162 | if (masks[0] & devc->trigger.risingmask) | |
1163 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); | |
1164 | if (masks[0] & devc->trigger.fallingmask) | |
1165 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); | |
1166 | if (masks[1] & devc->trigger.risingmask) | |
1167 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); | |
1168 | if (masks[1] & devc->trigger.fallingmask) | |
1169 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); | |
1170 | } else { | |
1171 | /* Only value/mask trigger. */ | |
1172 | lut->m3 = 0xffff; | |
1173 | } | |
1174 | ||
1175 | /* Triggertype: event. */ | |
1176 | lut->params.selres = 3; | |
1177 | ||
1178 | return SR_OK; | |
1179 | } |