]> sigrok.org Git - libsigrok.git/blame_incremental - src/hardware/asix-sigma/asix-sigma.c
projects / libsigrok.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
Add udev rule for Rigol 1000Z series
[libsigrok.git] / src / hardware / asix-sigma / asix-sigma.c
... / ...
CommitLineData
1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22/*
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
24 */
25
26#include <glib.h>
27#include <glib/gstdio.h>
28#include <ftdi.h>
29#include <string.h>
30#include <unistd.h>
31#include "libsigrok.h"
32#include "libsigrok-internal.h"
33#include "asix-sigma.h"
34
35#define USB_VENDOR 0xa600
36#define USB_PRODUCT 0xa000
37#define USB_DESCRIPTION "ASIX SIGMA"
38#define USB_VENDOR_NAME "ASIX"
39#define USB_MODEL_NAME "SIGMA"
40
41SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
42static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
43
44/*
45 * The ASIX Sigma supports arbitrary integer frequency divider in
46 * the 50MHz mode. The divider is in range 1...256 , allowing for
47 * very precise sampling rate selection. This driver supports only
48 * a subset of the sampling rates.
49 */
50static const uint64_t samplerates[] = {
51 SR_KHZ(200), /* div=250 */
52 SR_KHZ(250), /* div=200 */
53 SR_KHZ(500), /* div=100 */
54 SR_MHZ(1), /* div=50 */
55 SR_MHZ(5), /* div=10 */
56 SR_MHZ(10), /* div=5 */
57 SR_MHZ(25), /* div=2 */
58 SR_MHZ(50), /* div=1 */
59 SR_MHZ(100), /* Special FW needed */
60 SR_MHZ(200), /* Special FW needed */
61};
62
63/*
64 * Channel numbers seem to go from 1-16, according to this image:
65 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
66 * (the cable has two additional GND pins, and a TI and TO pin)
67 */
68static const char *channel_names[] = {
69 "1", "2", "3", "4", "5", "6", "7", "8",
70 "9", "10", "11", "12", "13", "14", "15", "16",
71};
72
73static const uint32_t drvopts[] = {
74 SR_CONF_LOGIC_ANALYZER,
75};
76
77static const uint32_t devopts[] = {
78 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
79 SR_CONF_LIMIT_SAMPLES | SR_CONF_SET,
80 SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
81 SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
82 SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET,
83};
84
85static const int32_t trigger_matches[] = {
86 SR_TRIGGER_ZERO,
87 SR_TRIGGER_ONE,
88 SR_TRIGGER_RISING,
89 SR_TRIGGER_FALLING,
90};
91
92static const char *sigma_firmware_files[] = {
93 /* 50 MHz, supports 8 bit fractions */
94 FIRMWARE_DIR "/asix-sigma-50.fw",
95 /* 100 MHz */
96 FIRMWARE_DIR "/asix-sigma-100.fw",
97 /* 200 MHz */
98 FIRMWARE_DIR "/asix-sigma-200.fw",
99 /* Synchronous clock from pin */
100 FIRMWARE_DIR "/asix-sigma-50sync.fw",
101 /* Frequency counter */
102 FIRMWARE_DIR "/asix-sigma-phasor.fw",
103};
104
105static int sigma_read(void *buf, size_t size, struct dev_context *devc)
106{
107 int ret;
108
109 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
110 if (ret < 0) {
111 sr_err("ftdi_read_data failed: %s",
112 ftdi_get_error_string(&devc->ftdic));
113 }
114
115 return ret;
116}
117
118static int sigma_write(void *buf, size_t size, struct dev_context *devc)
119{
120 int ret;
121
122 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
123 if (ret < 0) {
124 sr_err("ftdi_write_data failed: %s",
125 ftdi_get_error_string(&devc->ftdic));
126 } else if ((size_t) ret != size) {
127 sr_err("ftdi_write_data did not complete write.");
128 }
129
130 return ret;
131}
132
133static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
134 struct dev_context *devc)
135{
136 size_t i;
137 uint8_t buf[len + 2];
138 int idx = 0;
139
140 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
141 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
142
143 for (i = 0; i < len; ++i) {
144 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
145 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
146 }
147
148 return sigma_write(buf, idx, devc);
149}
150
151static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
152{
153 return sigma_write_register(reg, &value, 1, devc);
154}
155
156static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
157 struct dev_context *devc)
158{
159 uint8_t buf[3];
160
161 buf[0] = REG_ADDR_LOW | (reg & 0xf);
162 buf[1] = REG_ADDR_HIGH | (reg >> 4);
163 buf[2] = REG_READ_ADDR;
164
165 sigma_write(buf, sizeof(buf), devc);
166
167 return sigma_read(data, len, devc);
168}
169
170static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
171{
172 uint8_t value;
173
174 if (1 != sigma_read_register(reg, &value, 1, devc)) {
175 sr_err("sigma_get_register: 1 byte expected");
176 return 0;
177 }
178
179 return value;
180}
181
182static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
183 struct dev_context *devc)
184{
185 uint8_t buf[] = {
186 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
187
188 REG_READ_ADDR | NEXT_REG,
189 REG_READ_ADDR | NEXT_REG,
190 REG_READ_ADDR | NEXT_REG,
191 REG_READ_ADDR | NEXT_REG,
192 REG_READ_ADDR | NEXT_REG,
193 REG_READ_ADDR | NEXT_REG,
194 };
195 uint8_t result[6];
196
197 sigma_write(buf, sizeof(buf), devc);
198
199 sigma_read(result, sizeof(result), devc);
200
201 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
202 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
203
204 /* Not really sure why this must be done, but according to spec. */
205 if ((--*stoppos & 0x1ff) == 0x1ff)
206 *stoppos -= 64;
207
208 if ((*--triggerpos & 0x1ff) == 0x1ff)
209 *triggerpos -= 64;
210
211 return 1;
212}
213
214static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
215 uint8_t *data, struct dev_context *devc)
216{
217 size_t i;
218 uint8_t buf[4096];
219 int idx = 0;
220
221 /* Send the startchunk. Index start with 1. */
222 buf[0] = startchunk >> 8;
223 buf[1] = startchunk & 0xff;
224 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
225
226 /* Read the DRAM. */
227 buf[idx++] = REG_DRAM_BLOCK;
228 buf[idx++] = REG_DRAM_WAIT_ACK;
229
230 for (i = 0; i < numchunks; ++i) {
231 /* Alternate bit to copy from DRAM to cache. */
232 if (i != (numchunks - 1))
233 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
234
235 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
236
237 if (i != (numchunks - 1))
238 buf[idx++] = REG_DRAM_WAIT_ACK;
239 }
240
241 sigma_write(buf, idx, devc);
242
243 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
244}
245
246/* Upload trigger look-up tables to Sigma. */
247static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
248{
249 int i;
250 uint8_t tmp[2];
251 uint16_t bit;
252
253 /* Transpose the table and send to Sigma. */
254 for (i = 0; i < 16; ++i) {
255 bit = 1 << i;
256
257 tmp[0] = tmp[1] = 0;
258
259 if (lut->m2d[0] & bit)
260 tmp[0] |= 0x01;
261 if (lut->m2d[1] & bit)
262 tmp[0] |= 0x02;
263 if (lut->m2d[2] & bit)
264 tmp[0] |= 0x04;
265 if (lut->m2d[3] & bit)
266 tmp[0] |= 0x08;
267
268 if (lut->m3 & bit)
269 tmp[0] |= 0x10;
270 if (lut->m3s & bit)
271 tmp[0] |= 0x20;
272 if (lut->m4 & bit)
273 tmp[0] |= 0x40;
274
275 if (lut->m0d[0] & bit)
276 tmp[1] |= 0x01;
277 if (lut->m0d[1] & bit)
278 tmp[1] |= 0x02;
279 if (lut->m0d[2] & bit)
280 tmp[1] |= 0x04;
281 if (lut->m0d[3] & bit)
282 tmp[1] |= 0x08;
283
284 if (lut->m1d[0] & bit)
285 tmp[1] |= 0x10;
286 if (lut->m1d[1] & bit)
287 tmp[1] |= 0x20;
288 if (lut->m1d[2] & bit)
289 tmp[1] |= 0x40;
290 if (lut->m1d[3] & bit)
291 tmp[1] |= 0x80;
292
293 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
294 devc);
295 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
296 }
297
298 /* Send the parameters */
299 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
300 sizeof(lut->params), devc);
301
302 return SR_OK;
303}
304
305static void clear_helper(void *priv)
306{
307 struct dev_context *devc;
308
309 devc = priv;
310
311 ftdi_deinit(&devc->ftdic);
312}
313
314static int dev_clear(const struct sr_dev_driver *di)
315{
316 return std_dev_clear(di, clear_helper);
317}
318
319static int init(struct sr_dev_driver *di, struct sr_context *sr_ctx)
320{
321 return std_init(sr_ctx, di, LOG_PREFIX);
322}
323
324static GSList *scan(struct sr_dev_driver *di, GSList *options)
325{
326 struct sr_dev_inst *sdi;
327 struct drv_context *drvc;
328 struct dev_context *devc;
329 GSList *devices;
330 struct ftdi_device_list *devlist;
331 char serial_txt[10];
332 uint32_t serial;
333 int ret;
334 unsigned int i;
335
336 (void)options;
337
338 drvc = di->priv;
339
340 devices = NULL;
341
342 devc = g_malloc0(sizeof(struct dev_context));
343
344 ftdi_init(&devc->ftdic);
345
346 /* Look for SIGMAs. */
347
348 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
349 USB_VENDOR, USB_PRODUCT)) <= 0) {
350 if (ret < 0)
351 sr_err("ftdi_usb_find_all(): %d", ret);
352 goto free;
353 }
354
355 /* Make sure it's a version 1 or 2 SIGMA. */
356 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
357 serial_txt, sizeof(serial_txt));
358 sscanf(serial_txt, "%x", &serial);
359
360 if (serial < 0xa6010000 || serial > 0xa602ffff) {
361 sr_err("Only SIGMA and SIGMA2 are supported "
362 "in this version of libsigrok.");
363 goto free;
364 }
365
366 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
367
368 devc->cur_samplerate = samplerates[0];
369 devc->period_ps = 0;
370 devc->limit_msec = 0;
371 devc->cur_firmware = -1;
372 devc->num_channels = 0;
373 devc->samples_per_event = 0;
374 devc->capture_ratio = 50;
375 devc->use_triggers = 0;
376
377 /* Register SIGMA device. */
378 sdi = g_malloc0(sizeof(struct sr_dev_inst));
379 sdi->status = SR_ST_INITIALIZING;
380 sdi->vendor = g_strdup(USB_VENDOR_NAME);
381 sdi->model = g_strdup(USB_MODEL_NAME);
382 sdi->driver = di;
383
384 for (i = 0; i < ARRAY_SIZE(channel_names); i++)
385 sr_channel_new(sdi, i, SR_CHANNEL_LOGIC, TRUE, channel_names[i]);
386
387 devices = g_slist_append(devices, sdi);
388 drvc->instances = g_slist_append(drvc->instances, sdi);
389 sdi->priv = devc;
390
391 /* We will open the device again when we need it. */
392 ftdi_list_free(&devlist);
393
394 return devices;
395
396free:
397 ftdi_deinit(&devc->ftdic);
398 g_free(devc);
399 return NULL;
400}
401
402static GSList *dev_list(const struct sr_dev_driver *di)
403{
404 return ((struct drv_context *)(di->priv))->instances;
405}
406
407/*
408 * Configure the FPGA for bitbang mode.
409 * This sequence is documented in section 2. of the ASIX Sigma programming
410 * manual. This sequence is necessary to configure the FPGA in the Sigma
411 * into Bitbang mode, in which it can be programmed with the firmware.
412 */
413static int sigma_fpga_init_bitbang(struct dev_context *devc)
414{
415 uint8_t suicide[] = {
416 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
417 };
418 uint8_t init_array[] = {
419 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
420 0x01, 0x01,
421 };
422 int i, ret, timeout = 10000;
423 uint8_t data;
424
425 /* Section 2. part 1), do the FPGA suicide. */
426 sigma_write(suicide, sizeof(suicide), devc);
427 sigma_write(suicide, sizeof(suicide), devc);
428 sigma_write(suicide, sizeof(suicide), devc);
429 sigma_write(suicide, sizeof(suicide), devc);
430
431 /* Section 2. part 2), do pulse on D1. */
432 sigma_write(init_array, sizeof(init_array), devc);
433 ftdi_usb_purge_buffers(&devc->ftdic);
434
435 /* Wait until the FPGA asserts D6/INIT_B. */
436 for (i = 0; i < timeout; i++) {
437 ret = sigma_read(&data, 1, devc);
438 if (ret < 0)
439 return ret;
440 /* Test if pin D6 got asserted. */
441 if (data & (1 << 5))
442 return 0;
443 /* The D6 was not asserted yet, wait a bit. */
444 g_usleep(10000);
445 }
446
447 return SR_ERR_TIMEOUT;
448}
449
450/*
451 * Configure the FPGA for logic-analyzer mode.
452 */
453static int sigma_fpga_init_la(struct dev_context *devc)
454{
455 /* Initialize the logic analyzer mode. */
456 uint8_t logic_mode_start[] = {
457 REG_ADDR_LOW | (READ_ID & 0xf),
458 REG_ADDR_HIGH | (READ_ID >> 8),
459 REG_READ_ADDR, /* Read ID register. */
460
461 REG_ADDR_LOW | (WRITE_TEST & 0xf),
462 REG_DATA_LOW | 0x5,
463 REG_DATA_HIGH_WRITE | 0x5,
464 REG_READ_ADDR, /* Read scratch register. */
465
466 REG_DATA_LOW | 0xa,
467 REG_DATA_HIGH_WRITE | 0xa,
468 REG_READ_ADDR, /* Read scratch register. */
469
470 REG_ADDR_LOW | (WRITE_MODE & 0xf),
471 REG_DATA_LOW | 0x0,
472 REG_DATA_HIGH_WRITE | 0x8,
473 };
474
475 uint8_t result[3];
476 int ret;
477
478 /* Initialize the logic analyzer mode. */
479 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
480
481 /* Expect a 3 byte reply since we issued three READ requests. */
482 ret = sigma_read(result, 3, devc);
483 if (ret != 3)
484 goto err;
485
486 if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa)
487 goto err;
488
489 return SR_OK;
490err:
491 sr_err("Configuration failed. Invalid reply received.");
492 return SR_ERR;
493}
494
495/*
496 * Read the firmware from a file and transform it into a series of bitbang
497 * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d
498 * by the caller of this function.
499 */
500static int sigma_fw_2_bitbang(const char *filename,
501 uint8_t **bb_cmd, gsize *bb_cmd_size)
502{
503 GMappedFile *file;
504 GError *error;
505 gsize i, file_size, bb_size;
506 gchar *firmware;
507 uint8_t *bb_stream, *bbs;
508 uint32_t imm;
509 int bit, v;
510 int ret = SR_OK;
511
512 /*
513 * Map the file and make the mapped buffer writable.
514 * NOTE: Using writable=TRUE does _NOT_ mean that file that is mapped
515 * will be modified. It will not be modified until someone uses
516 * g_file_set_contents() on it.
517 */
518 error = NULL;
519 file = g_mapped_file_new(filename, TRUE, &error);
520 g_assert_no_error(error);
521
522 file_size = g_mapped_file_get_length(file);
523 firmware = g_mapped_file_get_contents(file);
524 g_assert(firmware);
525
526 /* Weird magic transformation below, I have no idea what it does. */
527 imm = 0x3f6df2ab;
528 for (i = 0; i < file_size; i++) {
529 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
530 firmware[i] ^= imm & 0xff;
531 }
532
533 /*
534 * Now that the firmware is "transformed", we will transcribe the
535 * firmware blob into a sequence of toggles of the Dx wires. This
536 * sequence will be fed directly into the Sigma, which must be in
537 * the FPGA bitbang programming mode.
538 */
539
540 /* Each bit of firmware is transcribed as two toggles of Dx wires. */
541 bb_size = file_size * 8 * 2;
542 bb_stream = (uint8_t *)g_try_malloc(bb_size);
543 if (!bb_stream) {
544 sr_err("%s: Failed to allocate bitbang stream", __func__);
545 ret = SR_ERR_MALLOC;
546 goto exit;
547 }
548
549 bbs = bb_stream;
550 for (i = 0; i < file_size; i++) {
551 for (bit = 7; bit >= 0; bit--) {
552 v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00;
553 *bbs++ = v | 0x01;
554 *bbs++ = v;
555 }
556 }
557
558 /* The transformation completed successfully, return the result. */
559 *bb_cmd = bb_stream;
560 *bb_cmd_size = bb_size;
561
562exit:
563 g_mapped_file_unref(file);
564 return ret;
565}
566
567static int upload_firmware(int firmware_idx, struct dev_context *devc)
568{
569 int ret;
570 unsigned char *buf;
571 unsigned char pins;
572 size_t buf_size;
573 const char *firmware = sigma_firmware_files[firmware_idx];
574 struct ftdi_context *ftdic = &devc->ftdic;
575
576 /* Make sure it's an ASIX SIGMA. */
577 ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT,
578 USB_DESCRIPTION, NULL);
579 if (ret < 0) {
580 sr_err("ftdi_usb_open failed: %s",
581 ftdi_get_error_string(ftdic));
582 return 0;
583 }
584
585 ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG);
586 if (ret < 0) {
587 sr_err("ftdi_set_bitmode failed: %s",
588 ftdi_get_error_string(ftdic));
589 return 0;
590 }
591
592 /* Four times the speed of sigmalogan - Works well. */
593 ret = ftdi_set_baudrate(ftdic, 750000);
594 if (ret < 0) {
595 sr_err("ftdi_set_baudrate failed: %s",
596 ftdi_get_error_string(ftdic));
597 return 0;
598 }
599
600 /* Initialize the FPGA for firmware upload. */
601 ret = sigma_fpga_init_bitbang(devc);
602 if (ret)
603 return ret;
604
605 /* Prepare firmware. */
606 ret = sigma_fw_2_bitbang(firmware, &buf, &buf_size);
607 if (ret != SR_OK) {
608 sr_err("An error occured while reading the firmware: %s",
609 firmware);
610 return ret;
611 }
612
613 /* Upload firmare. */
614 sr_info("Uploading firmware file '%s'.", firmware);
615 sigma_write(buf, buf_size, devc);
616
617 g_free(buf);
618
619 ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET);
620 if (ret < 0) {
621 sr_err("ftdi_set_bitmode failed: %s",
622 ftdi_get_error_string(ftdic));
623 return SR_ERR;
624 }
625
626 ftdi_usb_purge_buffers(ftdic);
627
628 /* Discard garbage. */
629 while (sigma_read(&pins, 1, devc) == 1)
630 ;
631
632 /* Initialize the FPGA for logic-analyzer mode. */
633 ret = sigma_fpga_init_la(devc);
634 if (ret != SR_OK)
635 return ret;
636
637 devc->cur_firmware = firmware_idx;
638
639 sr_info("Firmware uploaded.");
640
641 return SR_OK;
642}
643
644static int dev_open(struct sr_dev_inst *sdi)
645{
646 struct dev_context *devc;
647 int ret;
648
649 devc = sdi->priv;
650
651 /* Make sure it's an ASIX SIGMA. */
652 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
653 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
654
655 sr_err("ftdi_usb_open failed: %s",
656 ftdi_get_error_string(&devc->ftdic));
657
658 return 0;
659 }
660
661 sdi->status = SR_ST_ACTIVE;
662
663 return SR_OK;
664}
665
666static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
667{
668 struct dev_context *devc;
669 unsigned int i;
670 int ret;
671
672 devc = sdi->priv;
673 ret = SR_OK;
674
675 for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
676 if (samplerates[i] == samplerate)
677 break;
678 }
679 if (samplerates[i] == 0)
680 return SR_ERR_SAMPLERATE;
681
682 if (samplerate <= SR_MHZ(50)) {
683 ret = upload_firmware(0, devc);
684 devc->num_channels = 16;
685 } else if (samplerate == SR_MHZ(100)) {
686 ret = upload_firmware(1, devc);
687 devc->num_channels = 8;
688 } else if (samplerate == SR_MHZ(200)) {
689 ret = upload_firmware(2, devc);
690 devc->num_channels = 4;
691 }
692
693 if (ret == SR_OK) {
694 devc->cur_samplerate = samplerate;
695 devc->period_ps = 1000000000000ULL / samplerate;
696 devc->samples_per_event = 16 / devc->num_channels;
697 devc->state.state = SIGMA_IDLE;
698 }
699
700 return ret;
701}
702
703/*
704 * In 100 and 200 MHz mode, only a single pin rising/falling can be
705 * set as trigger. In other modes, two rising/falling triggers can be set,
706 * in addition to value/mask trigger for any number of channels.
707 *
708 * The Sigma supports complex triggers using boolean expressions, but this
709 * has not been implemented yet.
710 */
711static int convert_trigger(const struct sr_dev_inst *sdi)
712{
713 struct dev_context *devc;
714 struct sr_trigger *trigger;
715 struct sr_trigger_stage *stage;
716 struct sr_trigger_match *match;
717 const GSList *l, *m;
718 int channelbit, trigger_set;
719
720 devc = sdi->priv;
721 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
722 if (!(trigger = sr_session_trigger_get(sdi->session)))
723 return SR_OK;
724
725 trigger_set = 0;
726 for (l = trigger->stages; l; l = l->next) {
727 stage = l->data;
728 for (m = stage->matches; m; m = m->next) {
729 match = m->data;
730 if (!match->channel->enabled)
731 /* Ignore disabled channels with a trigger. */
732 continue;
733 channelbit = 1 << (match->channel->index);
734 if (devc->cur_samplerate >= SR_MHZ(100)) {
735 /* Fast trigger support. */
736 if (trigger_set) {
737 sr_err("Only a single pin trigger is "
738 "supported in 100 and 200MHz mode.");
739 return SR_ERR;
740 }
741 if (match->match == SR_TRIGGER_FALLING)
742 devc->trigger.fallingmask |= channelbit;
743 else if (match->match == SR_TRIGGER_RISING)
744 devc->trigger.risingmask |= channelbit;
745 else {
746 sr_err("Only rising/falling trigger is "
747 "supported in 100 and 200MHz mode.");
748 return SR_ERR;
749 }
750
751 ++trigger_set;
752 } else {
753 /* Simple trigger support (event). */
754 if (match->match == SR_TRIGGER_ONE) {
755 devc->trigger.simplevalue |= channelbit;
756 devc->trigger.simplemask |= channelbit;
757 }
758 else if (match->match == SR_TRIGGER_ZERO) {
759 devc->trigger.simplevalue &= ~channelbit;
760 devc->trigger.simplemask |= channelbit;
761 }
762 else if (match->match == SR_TRIGGER_FALLING) {
763 devc->trigger.fallingmask |= channelbit;
764 ++trigger_set;
765 }
766 else if (match->match == SR_TRIGGER_RISING) {
767 devc->trigger.risingmask |= channelbit;
768 ++trigger_set;
769 }
770
771 /*
772 * Actually, Sigma supports 2 rising/falling triggers,
773 * but they are ORed and the current trigger syntax
774 * does not permit ORed triggers.
775 */
776 if (trigger_set > 1) {
777 sr_err("Only 1 rising/falling trigger "
778 "is supported.");
779 return SR_ERR;
780 }
781 }
782 }
783 }
784
785 return SR_OK;
786}
787
788static int dev_close(struct sr_dev_inst *sdi)
789{
790 struct dev_context *devc;
791
792 devc = sdi->priv;
793
794 /* TODO */
795 if (sdi->status == SR_ST_ACTIVE)
796 ftdi_usb_close(&devc->ftdic);
797
798 sdi->status = SR_ST_INACTIVE;
799
800 return SR_OK;
801}
802
803static int cleanup(const struct sr_dev_driver *di)
804{
805 return dev_clear(di);
806}
807
808static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
809 const struct sr_channel_group *cg)
810{
811 struct dev_context *devc;
812
813 (void)cg;
814
815 if (!sdi)
816 return SR_ERR;
817 devc = sdi->priv;
818
819 switch (key) {
820 case SR_CONF_SAMPLERATE:
821 *data = g_variant_new_uint64(devc->cur_samplerate);
822 break;
823 case SR_CONF_LIMIT_MSEC:
824 *data = g_variant_new_uint64(devc->limit_msec);
825 break;
826 case SR_CONF_CAPTURE_RATIO:
827 *data = g_variant_new_uint64(devc->capture_ratio);
828 break;
829 default:
830 return SR_ERR_NA;
831 }
832
833 return SR_OK;
834}
835
836static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi,
837 const struct sr_channel_group *cg)
838{
839 struct dev_context *devc;
840 uint64_t tmp;
841 int ret;
842
843 (void)cg;
844
845 if (sdi->status != SR_ST_ACTIVE)
846 return SR_ERR_DEV_CLOSED;
847
848 devc = sdi->priv;
849
850 ret = SR_OK;
851 switch (key) {
852 case SR_CONF_SAMPLERATE:
853 ret = set_samplerate(sdi, g_variant_get_uint64(data));
854 break;
855 case SR_CONF_LIMIT_MSEC:
856 tmp = g_variant_get_uint64(data);
857 if (tmp > 0)
858 devc->limit_msec = g_variant_get_uint64(data);
859 else
860 ret = SR_ERR;
861 break;
862 case SR_CONF_LIMIT_SAMPLES:
863 tmp = g_variant_get_uint64(data);
864 devc->limit_msec = tmp * 1000 / devc->cur_samplerate;
865 break;
866 case SR_CONF_CAPTURE_RATIO:
867 tmp = g_variant_get_uint64(data);
868 if (tmp <= 100)
869 devc->capture_ratio = tmp;
870 else
871 ret = SR_ERR;
872 break;
873 default:
874 ret = SR_ERR_NA;
875 }
876
877 return ret;
878}
879
880static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
881 const struct sr_channel_group *cg)
882{
883 GVariant *gvar;
884 GVariantBuilder gvb;
885
886 (void)cg;
887
888 switch (key) {
889 case SR_CONF_DEVICE_OPTIONS:
890 if (!sdi)
891 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
892 drvopts, ARRAY_SIZE(drvopts), sizeof(uint32_t));
893 else
894 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
895 devopts, ARRAY_SIZE(devopts), sizeof(uint32_t));
896 break;
897 case SR_CONF_SAMPLERATE:
898 g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
899 gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
900 ARRAY_SIZE(samplerates), sizeof(uint64_t));
901 g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
902 *data = g_variant_builder_end(&gvb);
903 break;
904 case SR_CONF_TRIGGER_MATCH:
905 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
906 trigger_matches, ARRAY_SIZE(trigger_matches),
907 sizeof(int32_t));
908 break;
909 default:
910 return SR_ERR_NA;
911 }
912
913 return SR_OK;
914}
915
916/* Software trigger to determine exact trigger position. */
917static int get_trigger_offset(uint8_t *samples, uint16_t last_sample,
918 struct sigma_trigger *t)
919{
920 int i;
921 uint16_t sample = 0;
922
923 for (i = 0; i < 8; ++i) {
924 if (i > 0)
925 last_sample = sample;
926 sample = samples[2 * i] | (samples[2 * i + 1] << 8);
927
928 /* Simple triggers. */
929 if ((sample & t->simplemask) != t->simplevalue)
930 continue;
931
932 /* Rising edge. */
933 if (((last_sample & t->risingmask) != 0) ||
934 ((sample & t->risingmask) != t->risingmask))
935 continue;
936
937 /* Falling edge. */
938 if ((last_sample & t->fallingmask) != t->fallingmask ||
939 (sample & t->fallingmask) != 0)
940 continue;
941
942 break;
943 }
944
945 /* If we did not match, return original trigger pos. */
946 return i & 0x7;
947}
948
949/*
950 * Return the timestamp of "DRAM cluster".
951 */
952static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster)
953{
954 return (cluster->timestamp_hi << 8) | cluster->timestamp_lo;
955}
956
957static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster,
958 unsigned int events_in_cluster,
959 unsigned int triggered,
960 struct sr_dev_inst *sdi)
961{
962 struct dev_context *devc = sdi->priv;
963 struct sigma_state *ss = &devc->state;
964 struct sr_datafeed_packet packet;
965 struct sr_datafeed_logic logic;
966 uint16_t tsdiff, ts;
967 uint8_t samples[2048];
968 unsigned int i;
969
970 ts = sigma_dram_cluster_ts(dram_cluster);
971 tsdiff = ts - ss->lastts;
972 ss->lastts = ts;
973
974 packet.type = SR_DF_LOGIC;
975 packet.payload = &logic;
976 logic.unitsize = 2;
977 logic.data = samples;
978
979 /*
980 * First of all, send Sigrok a copy of the last sample from
981 * previous cluster as many times as needed to make up for
982 * the differential characteristics of data we get from the
983 * Sigma. Sigrok needs one sample of data per period.
984 *
985 * One DRAM cluster contains a timestamp and seven samples,
986 * the units of timestamp are "devc->period_ps" , the first
987 * sample in the cluster happens at the time of the timestamp
988 * and the remaining samples happen at timestamp +1...+6 .
989 */
990 for (ts = 0; ts < tsdiff - (EVENTS_PER_CLUSTER - 1); ts++) {
991 i = ts % 1024;
992 samples[2 * i + 0] = ss->lastsample & 0xff;
993 samples[2 * i + 1] = ss->lastsample >> 8;
994
995 /*
996 * If we have 1024 samples ready or we're at the
997 * end of submitting the padding samples, submit
998 * the packet to Sigrok.
999 */
1000 if ((i == 1023) || (ts == (tsdiff - EVENTS_PER_CLUSTER))) {
1001 logic.length = (i + 1) * logic.unitsize;
1002 sr_session_send(sdi, &packet);
1003 }
1004 }
1005
1006 /*
1007 * Parse the samples in current cluster and prepare them
1008 * to be submitted to Sigrok.
1009 */
1010 for (i = 0; i < events_in_cluster; i++) {
1011 samples[2 * i + 1] = dram_cluster->samples[i].sample_lo;
1012 samples[2 * i + 0] = dram_cluster->samples[i].sample_hi;
1013 }
1014
1015 /* Send data up to trigger point (if triggered). */
1016 int trigger_offset = 0;
1017 if (triggered) {
1018 /*
1019 * Trigger is not always accurate to sample because of
1020 * pipeline delay. However, it always triggers before
1021 * the actual event. We therefore look at the next
1022 * samples to pinpoint the exact position of the trigger.
1023 */
1024 trigger_offset = get_trigger_offset(samples,
1025 ss->lastsample, &devc->trigger);
1026
1027 if (trigger_offset > 0) {
1028 packet.type = SR_DF_LOGIC;
1029 logic.length = trigger_offset * logic.unitsize;
1030 sr_session_send(sdi, &packet);
1031 events_in_cluster -= trigger_offset;
1032 }
1033
1034 /* Only send trigger if explicitly enabled. */
1035 if (devc->use_triggers) {
1036 packet.type = SR_DF_TRIGGER;
1037 sr_session_send(sdi, &packet);
1038 }
1039 }
1040
1041 if (events_in_cluster > 0) {
1042 packet.type = SR_DF_LOGIC;
1043 logic.length = events_in_cluster * logic.unitsize;
1044 logic.data = samples + (trigger_offset * logic.unitsize);
1045 sr_session_send(sdi, &packet);
1046 }
1047
1048 ss->lastsample =
1049 samples[2 * (events_in_cluster - 1) + 0] |
1050 (samples[2 * (events_in_cluster - 1) + 1] << 8);
1051
1052}
1053
1054/*
1055 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
1056 * Each event is 20ns apart, and can contain multiple samples.
1057 *
1058 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
1059 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
1060 * For 50 MHz and below, events contain one sample for each channel,
1061 * spread 20 ns apart.
1062 */
1063static int decode_chunk_ts(struct sigma_dram_line *dram_line,
1064 uint16_t events_in_line,
1065 uint32_t trigger_event,
1066 struct sr_dev_inst *sdi)
1067{
1068 struct sigma_dram_cluster *dram_cluster;
1069 struct dev_context *devc = sdi->priv;
1070 unsigned int clusters_in_line =
1071 (events_in_line + (EVENTS_PER_CLUSTER - 1)) / EVENTS_PER_CLUSTER;
1072 unsigned int events_in_cluster;
1073 unsigned int i;
1074 uint32_t trigger_cluster = ~0, triggered = 0;
1075
1076 /* Check if trigger is in this chunk. */
1077 if (trigger_event < (64 * 7)) {
1078 if (devc->cur_samplerate <= SR_MHZ(50)) {
1079 trigger_event -= MIN(EVENTS_PER_CLUSTER - 1,
1080 trigger_event);
1081 }
1082
1083 /* Find in which cluster the trigger occured. */
1084 trigger_cluster = trigger_event / EVENTS_PER_CLUSTER;
1085 }
1086
1087 /* For each full DRAM cluster. */
1088 for (i = 0; i < clusters_in_line; i++) {
1089 dram_cluster = &dram_line->cluster[i];
1090
1091 /* The last cluster might not be full. */
1092 if ((i == clusters_in_line - 1) &&
1093 (events_in_line % EVENTS_PER_CLUSTER)) {
1094 events_in_cluster = events_in_line % EVENTS_PER_CLUSTER;
1095 } else {
1096 events_in_cluster = EVENTS_PER_CLUSTER;
1097 }
1098
1099 triggered = (i == trigger_cluster);
1100 sigma_decode_dram_cluster(dram_cluster, events_in_cluster,
1101 triggered, sdi);
1102 }
1103
1104 return SR_OK;
1105}
1106
1107static int download_capture(struct sr_dev_inst *sdi)
1108{
1109 struct dev_context *devc = sdi->priv;
1110 const uint32_t chunks_per_read = 32;
1111 struct sigma_dram_line *dram_line;
1112 int bufsz;
1113 uint32_t stoppos, triggerpos;
1114 struct sr_datafeed_packet packet;
1115 uint8_t modestatus;
1116
1117 uint32_t i;
1118 uint32_t dl_lines_total, dl_lines_curr, dl_lines_done;
1119 uint32_t dl_events_in_line = 64 * 7;
1120 uint32_t trg_line = ~0, trg_event = ~0;
1121
1122 dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line));
1123 if (!dram_line)
1124 return FALSE;
1125
1126 sr_info("Downloading sample data.");
1127
1128 /* Stop acquisition. */
1129 sigma_set_register(WRITE_MODE, 0x11, devc);
1130
1131 /* Set SDRAM Read Enable. */
1132 sigma_set_register(WRITE_MODE, 0x02, devc);
1133
1134 /* Get the current position. */
1135 sigma_read_pos(&stoppos, &triggerpos, devc);
1136
1137 /* Check if trigger has fired. */
1138 modestatus = sigma_get_register(READ_MODE, devc);
1139 if (modestatus & 0x20) {
1140 trg_line = triggerpos >> 9;
1141 trg_event = triggerpos & 0x1ff;
1142 }
1143
1144 /*
1145 * Determine how many 1024b "DRAM lines" do we need to read from the
1146 * Sigma so we have a complete set of samples. Note that the last
1147 * line can be only partial, containing less than 64 clusters.
1148 */
1149 dl_lines_total = (stoppos >> 9) + 1;
1150
1151 dl_lines_done = 0;
1152
1153 while (dl_lines_total > dl_lines_done) {
1154 /* We can download only up-to 32 DRAM lines in one go! */
1155 dl_lines_curr = MIN(chunks_per_read, dl_lines_total);
1156
1157 bufsz = sigma_read_dram(dl_lines_done, dl_lines_curr,
1158 (uint8_t *)dram_line, devc);
1159 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1160 (void)bufsz;
1161
1162 /* This is the first DRAM line, so find the initial timestamp. */
1163 if (dl_lines_done == 0) {
1164 devc->state.lastts =
1165 sigma_dram_cluster_ts(&dram_line[0].cluster[0]);
1166 devc->state.lastsample = 0;
1167 }
1168
1169 for (i = 0; i < dl_lines_curr; i++) {
1170 uint32_t trigger_event = ~0;
1171 /* The last "DRAM line" can be only partially full. */
1172 if (dl_lines_done + i == dl_lines_total - 1)
1173 dl_events_in_line = stoppos & 0x1ff;
1174
1175 /* Test if the trigger happened on this line. */
1176 if (dl_lines_done + i == trg_line)
1177 trigger_event = trg_event;
1178
1179 decode_chunk_ts(dram_line + i, dl_events_in_line,
1180 trigger_event, sdi);
1181 }
1182
1183 dl_lines_done += dl_lines_curr;
1184 }
1185
1186 /* All done. */
1187 packet.type = SR_DF_END;
1188 sr_session_send(sdi, &packet);
1189
1190 dev_acquisition_stop(sdi, sdi);
1191
1192 g_free(dram_line);
1193
1194 return TRUE;
1195}
1196
1197/*
1198 * Handle the Sigma when in CAPTURE mode. This function checks:
1199 * - Sampling time ended
1200 * - DRAM capacity overflow
1201 * This function triggers download of the samples from Sigma
1202 * in case either of the above conditions is true.
1203 */
1204static int sigma_capture_mode(struct sr_dev_inst *sdi)
1205{
1206 struct dev_context *devc = sdi->priv;
1207
1208 uint64_t running_msec;
1209 struct timeval tv;
1210
1211 uint32_t stoppos, triggerpos;
1212
1213 /* Check if the selected sampling duration passed. */
1214 gettimeofday(&tv, 0);
1215 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1216 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1217 if (running_msec >= devc->limit_msec)
1218 return download_capture(sdi);
1219
1220 /* Get the position in DRAM to which the FPGA is writing now. */
1221 sigma_read_pos(&stoppos, &triggerpos, devc);
1222 /* Test if DRAM is full and if so, download the data. */
1223 if ((stoppos >> 9) == 32767)
1224 return download_capture(sdi);
1225
1226 return TRUE;
1227}
1228
1229static int receive_data(int fd, int revents, void *cb_data)
1230{
1231 struct sr_dev_inst *sdi;
1232 struct dev_context *devc;
1233
1234 (void)fd;
1235 (void)revents;
1236
1237 sdi = cb_data;
1238 devc = sdi->priv;
1239
1240 if (devc->state.state == SIGMA_IDLE)
1241 return TRUE;
1242
1243 if (devc->state.state == SIGMA_CAPTURE)
1244 return sigma_capture_mode(sdi);
1245
1246 return TRUE;
1247}
1248
1249/* Build a LUT entry used by the trigger functions. */
1250static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1251{
1252 int i, j, k, bit;
1253
1254 /* For each quad channel. */
1255 for (i = 0; i < 4; ++i) {
1256 entry[i] = 0xffff;
1257
1258 /* For each bit in LUT. */
1259 for (j = 0; j < 16; ++j)
1260
1261 /* For each channel in quad. */
1262 for (k = 0; k < 4; ++k) {
1263 bit = 1 << (i * 4 + k);
1264
1265 /* Set bit in entry */
1266 if ((mask & bit) &&
1267 ((!(value & bit)) !=
1268 (!(j & (1 << k)))))
1269 entry[i] &= ~(1 << j);
1270 }
1271 }
1272}
1273
1274/* Add a logical function to LUT mask. */
1275static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1276 int index, int neg, uint16_t *mask)
1277{
1278 int i, j;
1279 int x[2][2], tmp, a, b, aset, bset, rset;
1280
1281 memset(x, 0, 4 * sizeof(int));
1282
1283 /* Trigger detect condition. */
1284 switch (oper) {
1285 case OP_LEVEL:
1286 x[0][1] = 1;
1287 x[1][1] = 1;
1288 break;
1289 case OP_NOT:
1290 x[0][0] = 1;
1291 x[1][0] = 1;
1292 break;
1293 case OP_RISE:
1294 x[0][1] = 1;
1295 break;
1296 case OP_FALL:
1297 x[1][0] = 1;
1298 break;
1299 case OP_RISEFALL:
1300 x[0][1] = 1;
1301 x[1][0] = 1;
1302 break;
1303 case OP_NOTRISE:
1304 x[1][1] = 1;
1305 x[0][0] = 1;
1306 x[1][0] = 1;
1307 break;
1308 case OP_NOTFALL:
1309 x[1][1] = 1;
1310 x[0][0] = 1;
1311 x[0][1] = 1;
1312 break;
1313 case OP_NOTRISEFALL:
1314 x[1][1] = 1;
1315 x[0][0] = 1;
1316 break;
1317 }
1318
1319 /* Transpose if neg is set. */
1320 if (neg) {
1321 for (i = 0; i < 2; ++i) {
1322 for (j = 0; j < 2; ++j) {
1323 tmp = x[i][j];
1324 x[i][j] = x[1-i][1-j];
1325 x[1-i][1-j] = tmp;
1326 }
1327 }
1328 }
1329
1330 /* Update mask with function. */
1331 for (i = 0; i < 16; ++i) {
1332 a = (i >> (2 * index + 0)) & 1;
1333 b = (i >> (2 * index + 1)) & 1;
1334
1335 aset = (*mask >> i) & 1;
1336 bset = x[b][a];
1337
1338 rset = 0;
1339 if (func == FUNC_AND || func == FUNC_NAND)
1340 rset = aset & bset;
1341 else if (func == FUNC_OR || func == FUNC_NOR)
1342 rset = aset | bset;
1343 else if (func == FUNC_XOR || func == FUNC_NXOR)
1344 rset = aset ^ bset;
1345
1346 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1347 rset = !rset;
1348
1349 *mask &= ~(1 << i);
1350
1351 if (rset)
1352 *mask |= 1 << i;
1353 }
1354}
1355
1356/*
1357 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1358 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1359 * set at any time, but a full mask and value can be set (0/1).
1360 */
1361static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1362{
1363 int i,j;
1364 uint16_t masks[2] = { 0, 0 };
1365
1366 memset(lut, 0, sizeof(struct triggerlut));
1367
1368 /* Contant for simple triggers. */
1369 lut->m4 = 0xa000;
1370
1371 /* Value/mask trigger support. */
1372 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1373 lut->m2d);
1374
1375 /* Rise/fall trigger support. */
1376 for (i = 0, j = 0; i < 16; ++i) {
1377 if (devc->trigger.risingmask & (1 << i) ||
1378 devc->trigger.fallingmask & (1 << i))
1379 masks[j++] = 1 << i;
1380 }
1381
1382 build_lut_entry(masks[0], masks[0], lut->m0d);
1383 build_lut_entry(masks[1], masks[1], lut->m1d);
1384
1385 /* Add glue logic */
1386 if (masks[0] || masks[1]) {
1387 /* Transition trigger. */
1388 if (masks[0] & devc->trigger.risingmask)
1389 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1390 if (masks[0] & devc->trigger.fallingmask)
1391 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1392 if (masks[1] & devc->trigger.risingmask)
1393 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1394 if (masks[1] & devc->trigger.fallingmask)
1395 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1396 } else {
1397 /* Only value/mask trigger. */
1398 lut->m3 = 0xffff;
1399 }
1400
1401 /* Triggertype: event. */
1402 lut->params.selres = 3;
1403
1404 return SR_OK;
1405}
1406
1407static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
1408{
1409 struct dev_context *devc;
1410 struct clockselect_50 clockselect;
1411 int frac, triggerpin, ret;
1412 uint8_t triggerselect = 0;
1413 struct triggerinout triggerinout_conf;
1414 struct triggerlut lut;
1415
1416 if (sdi->status != SR_ST_ACTIVE)
1417 return SR_ERR_DEV_CLOSED;
1418
1419 devc = sdi->priv;
1420
1421 if (convert_trigger(sdi) != SR_OK) {
1422 sr_err("Failed to configure triggers.");
1423 return SR_ERR;
1424 }
1425
1426 /* If the samplerate has not been set, default to 200 kHz. */
1427 if (devc->cur_firmware == -1) {
1428 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1429 return ret;
1430 }
1431
1432 /* Enter trigger programming mode. */
1433 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1434
1435 /* 100 and 200 MHz mode. */
1436 if (devc->cur_samplerate >= SR_MHZ(100)) {
1437 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1438
1439 /* Find which pin to trigger on from mask. */
1440 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1441 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1442 (1 << triggerpin))
1443 break;
1444
1445 /* Set trigger pin and light LED on trigger. */
1446 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1447
1448 /* Default rising edge. */
1449 if (devc->trigger.fallingmask)
1450 triggerselect |= 1 << 3;
1451
1452 /* All other modes. */
1453 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1454 build_basic_trigger(&lut, devc);
1455
1456 sigma_write_trigger_lut(&lut, devc);
1457
1458 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1459 }
1460
1461 /* Setup trigger in and out pins to default values. */
1462 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1463 triggerinout_conf.trgout_bytrigger = 1;
1464 triggerinout_conf.trgout_enable = 1;
1465
1466 sigma_write_register(WRITE_TRIGGER_OPTION,
1467 (uint8_t *) &triggerinout_conf,
1468 sizeof(struct triggerinout), devc);
1469
1470 /* Go back to normal mode. */
1471 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1472
1473 /* Set clock select register. */
1474 if (devc->cur_samplerate == SR_MHZ(200))
1475 /* Enable 4 channels. */
1476 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1477 else if (devc->cur_samplerate == SR_MHZ(100))
1478 /* Enable 8 channels. */
1479 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1480 else {
1481 /*
1482 * 50 MHz mode (or fraction thereof). Any fraction down to
1483 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1484 */
1485 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1486
1487 clockselect.async = 0;
1488 clockselect.fraction = frac;
1489 clockselect.disabled_channels = 0;
1490
1491 sigma_write_register(WRITE_CLOCK_SELECT,
1492 (uint8_t *) &clockselect,
1493 sizeof(clockselect), devc);
1494 }
1495
1496 /* Setup maximum post trigger time. */
1497 sigma_set_register(WRITE_POST_TRIGGER,
1498 (devc->capture_ratio * 255) / 100, devc);
1499
1500 /* Start acqusition. */
1501 gettimeofday(&devc->start_tv, 0);
1502 sigma_set_register(WRITE_MODE, 0x0d, devc);
1503
1504 devc->cb_data = cb_data;
1505
1506 /* Send header packet to the session bus. */
1507 std_session_send_df_header(sdi, LOG_PREFIX);
1508
1509 /* Add capture source. */
1510 sr_session_source_add(sdi->session, 0, G_IO_IN, 10, receive_data, (void *)sdi);
1511
1512 devc->state.state = SIGMA_CAPTURE;
1513
1514 return SR_OK;
1515}
1516
1517static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1518{
1519 struct dev_context *devc;
1520
1521 (void)cb_data;
1522
1523 devc = sdi->priv;
1524 devc->state.state = SIGMA_IDLE;
1525
1526 sr_session_source_remove(sdi->session, 0);
1527
1528 return SR_OK;
1529}
1530
1531SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1532 .name = "asix-sigma",
1533 .longname = "ASIX SIGMA/SIGMA2",
1534 .api_version = 1,
1535 .init = init,
1536 .cleanup = cleanup,
1537 .scan = scan,
1538 .dev_list = dev_list,
1539 .dev_clear = dev_clear,
1540 .config_get = config_get,
1541 .config_set = config_set,
1542 .config_list = config_list,
1543 .dev_open = dev_open,
1544 .dev_close = dev_close,
1545 .dev_acquisition_start = dev_acquisition_start,
1546 .dev_acquisition_stop = dev_acquisition_stop,
1547 .priv = NULL,
1548};
Hardware access and backend lib