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Commit | Line | Data |
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1 | ------------------------------------------------------------------------------- | |
2 | PS/2 keyboard | |
3 | ------------------------------------------------------------------------------- | |
4 | ||
5 | This is a collection of PS/2 keyboard communication examples. | |
6 | ||
7 | A random PS/2 keyboard and a random PC mainboard were used as data source. | |
8 | ||
9 | For details see: | |
10 | https://web.archive.org/web/20161231114842/http://www.computer-engineering.org/ps2protocol/ | |
11 | https://www.avrfreaks.net/sites/default/files/PS2%20Keyboard.pdf | |
12 | ||
13 | ||
14 | Logic analyzer setup | |
15 | -------------------- | |
16 | ||
17 | The logic analyzer used was a Saleae Logic (at 24 MHz): | |
18 | ||
19 | Probe PS/2 | |
20 | ---------------- | |
21 | 2 Data | |
22 | 3 Clock | |
23 | ||
24 | ||
25 | ps2_keyboard_asdfgh.sr | |
26 | ---------------------- | |
27 | ||
28 | This file contains a sequence of keypresses on a standard PS/2 keyboard: | |
29 | a, s, d, f, g. The dump contains the "make code" and "break code" of each key. | |
30 | ||
31 | After each transmission, the receiving controller appears to pull the clock | |
32 | line low for more than 100 microseconds. This inhibits transmission until the | |
33 | clock line is released, presumably because the receiving controller needs time | |
34 | to process data. Due to this, additional very short clock pulses can be | |
35 | observed, as the controller starts inhibiting communication only shortly after | |
36 | packets are received. | |
37 | ||
38 | ||
39 | ps2_keyboard_asdfgh_no_inhibit.sr | |
40 | --------------------------------- | |
41 | ||
42 | The keys a, s, d, f and g pressed on a random PS/2 keyboard. | |
43 | ||
44 | In this dump, the receiving end was passive, without inhibiting communication. | |
45 | Thus only clock pulses produced by the keyboard can be observed. |