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1 | /* | |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se> | |
5 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
6 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
7 | * | |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #include "protocol.h" | |
23 | ||
24 | #include <stdint.h> | |
25 | #include <string.h> | |
26 | #include <glib.h> | |
27 | #include <glib/gstdio.h> | |
28 | #include <stdio.h> | |
29 | #include <errno.h> | |
30 | #include <math.h> | |
31 | #include "libsigrok.h" | |
32 | #include "libsigrok-internal.h" | |
33 | ||
34 | #define FPGA_FIRMWARE_18 FIRMWARE_DIR"/saleae-logic16-fpga-18.bitstream" | |
35 | #define FPGA_FIRMWARE_33 FIRMWARE_DIR"/saleae-logic16-fpga-33.bitstream" | |
36 | ||
37 | #define MAX_SAMPLE_RATE SR_MHZ(100) | |
38 | #define MAX_4CH_SAMPLE_RATE SR_MHZ(50) | |
39 | #define MAX_7CH_SAMPLE_RATE SR_MHZ(40) | |
40 | #define MAX_8CH_SAMPLE_RATE SR_MHZ(32) | |
41 | #define MAX_10CH_SAMPLE_RATE SR_MHZ(25) | |
42 | #define MAX_13CH_SAMPLE_RATE SR_MHZ(16) | |
43 | ||
44 | #define BASE_CLOCK_0_FREQ SR_MHZ(100) | |
45 | #define BASE_CLOCK_1_FREQ SR_MHZ(160) | |
46 | ||
47 | #define COMMAND_START_ACQUISITION 1 | |
48 | #define COMMAND_ABORT_ACQUISITION_ASYNC 2 | |
49 | #define COMMAND_WRITE_EEPROM 6 | |
50 | #define COMMAND_READ_EEPROM 7 | |
51 | #define COMMAND_WRITE_LED_TABLE 0x7a | |
52 | #define COMMAND_SET_LED_MODE 0x7b | |
53 | #define COMMAND_RETURN_TO_BOOTLOADER 0x7c | |
54 | #define COMMAND_ABORT_ACQUISITION_SYNC 0x7d | |
55 | #define COMMAND_FPGA_UPLOAD_INIT 0x7e | |
56 | #define COMMAND_FPGA_UPLOAD_SEND_DATA 0x7f | |
57 | #define COMMAND_FPGA_WRITE_REGISTER 0x80 | |
58 | #define COMMAND_FPGA_READ_REGISTER 0x81 | |
59 | #define COMMAND_GET_REVID 0x82 | |
60 | ||
61 | #define WRITE_EEPROM_COOKIE1 0x42 | |
62 | #define WRITE_EEPROM_COOKIE2 0x55 | |
63 | #define READ_EEPROM_COOKIE1 0x33 | |
64 | #define READ_EEPROM_COOKIE2 0x81 | |
65 | #define ABORT_ACQUISITION_SYNC_PATTERN 0x55 | |
66 | ||
67 | #define MAX_EMPTY_TRANSFERS 64 | |
68 | ||
69 | static void encrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt) | |
70 | { | |
71 | uint8_t state1 = 0x9b, state2 = 0x54; | |
72 | uint8_t t, v; | |
73 | int i; | |
74 | ||
75 | for (i = 0; i < cnt; i++) { | |
76 | v = src[i]; | |
77 | t = (((v ^ state2 ^ 0x2b) - 0x05) ^ 0x35) - 0x39; | |
78 | t = (((t ^ state1 ^ 0x5a) - 0xb0) ^ 0x38) - 0x45; | |
79 | dest[i] = state2 = t; | |
80 | state1 = v; | |
81 | } | |
82 | } | |
83 | ||
84 | static void decrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt) | |
85 | { | |
86 | uint8_t state1 = 0x9b, state2 = 0x54; | |
87 | uint8_t t, v; | |
88 | int i; | |
89 | ||
90 | for (i = 0; i < cnt; i++) { | |
91 | v = src[i]; | |
92 | t = (((v + 0x45) ^ 0x38) + 0xb0) ^ 0x5a ^ state1; | |
93 | t = (((t + 0x39) ^ 0x35) + 0x05) ^ 0x2b ^ state2; | |
94 | dest[i] = state1 = t; | |
95 | state2 = v; | |
96 | } | |
97 | } | |
98 | ||
99 | static int do_ep1_command(const struct sr_dev_inst *sdi, | |
100 | const uint8_t *command, uint8_t cmd_len, | |
101 | uint8_t *reply, uint8_t reply_len) | |
102 | { | |
103 | uint8_t buf[64]; | |
104 | struct sr_usb_dev_inst *usb; | |
105 | int ret, xfer; | |
106 | ||
107 | usb = sdi->conn; | |
108 | ||
109 | if (cmd_len < 1 || cmd_len > 64 || reply_len > 64 || | |
110 | command == NULL || (reply_len > 0 && reply == NULL)) | |
111 | return SR_ERR_ARG; | |
112 | ||
113 | encrypt(buf, command, cmd_len); | |
114 | ||
115 | ret = libusb_bulk_transfer(usb->devhdl, 1, buf, cmd_len, &xfer, 1000); | |
116 | if (ret != 0) { | |
117 | sr_dbg("Failed to send EP1 command 0x%02x: %s.", | |
118 | command[0], libusb_error_name(ret)); | |
119 | return SR_ERR; | |
120 | } | |
121 | if (xfer != cmd_len) { | |
122 | sr_dbg("Failed to send EP1 command 0x%02x: incorrect length " | |
123 | "%d != %d.", xfer, cmd_len); | |
124 | return SR_ERR; | |
125 | } | |
126 | ||
127 | if (reply_len == 0) | |
128 | return SR_OK; | |
129 | ||
130 | ret = libusb_bulk_transfer(usb->devhdl, 0x80 | 1, buf, reply_len, | |
131 | &xfer, 1000); | |
132 | if (ret != 0) { | |
133 | sr_dbg("Failed to receive reply to EP1 command 0x%02x: %s.", | |
134 | command[0], libusb_error_name(ret)); | |
135 | return SR_ERR; | |
136 | } | |
137 | if (xfer != reply_len) { | |
138 | sr_dbg("Failed to receive reply to EP1 command 0x%02x: " | |
139 | "incorrect length %d != %d.", xfer, reply_len); | |
140 | return SR_ERR; | |
141 | } | |
142 | ||
143 | decrypt(reply, buf, reply_len); | |
144 | ||
145 | return SR_OK; | |
146 | } | |
147 | ||
148 | static int read_eeprom(const struct sr_dev_inst *sdi, | |
149 | uint8_t address, uint8_t length, uint8_t *buf) | |
150 | { | |
151 | uint8_t command[5] = { | |
152 | COMMAND_READ_EEPROM, | |
153 | READ_EEPROM_COOKIE1, | |
154 | READ_EEPROM_COOKIE2, | |
155 | address, | |
156 | length, | |
157 | }; | |
158 | ||
159 | return do_ep1_command(sdi, command, 5, buf, length); | |
160 | } | |
161 | ||
162 | static int upload_led_table(const struct sr_dev_inst *sdi, | |
163 | const uint8_t *table, uint8_t offset, uint8_t cnt) | |
164 | { | |
165 | uint8_t chunk, command[64]; | |
166 | int ret; | |
167 | ||
168 | if (cnt < 1 || cnt + offset > 64 || table == NULL) | |
169 | return SR_ERR_ARG; | |
170 | ||
171 | while (cnt > 0) { | |
172 | chunk = (cnt > 32 ? 32 : cnt); | |
173 | ||
174 | command[0] = COMMAND_WRITE_LED_TABLE; | |
175 | command[1] = offset; | |
176 | command[2] = chunk; | |
177 | memcpy(command + 3, table, chunk); | |
178 | ||
179 | ret = do_ep1_command(sdi, command, 3 + chunk, NULL, 0); | |
180 | if (ret != SR_OK) | |
181 | return ret; | |
182 | ||
183 | table += chunk; | |
184 | offset += chunk; | |
185 | cnt -= chunk; | |
186 | } | |
187 | ||
188 | return SR_OK; | |
189 | } | |
190 | ||
191 | static int set_led_mode(const struct sr_dev_inst *sdi, | |
192 | uint8_t animate, uint16_t t2reload, uint8_t div, | |
193 | uint8_t repeat) | |
194 | { | |
195 | uint8_t command[6] = { | |
196 | COMMAND_SET_LED_MODE, | |
197 | animate, | |
198 | t2reload & 0xff, | |
199 | t2reload >> 8, | |
200 | div, | |
201 | repeat, | |
202 | }; | |
203 | ||
204 | return do_ep1_command(sdi, command, 6, NULL, 0); | |
205 | } | |
206 | ||
207 | static int read_fpga_register(const struct sr_dev_inst *sdi, | |
208 | uint8_t address, uint8_t *value) | |
209 | { | |
210 | uint8_t command[3] = { | |
211 | COMMAND_FPGA_READ_REGISTER, | |
212 | 1, | |
213 | address, | |
214 | }; | |
215 | ||
216 | return do_ep1_command(sdi, command, 3, value, 1); | |
217 | } | |
218 | ||
219 | static int write_fpga_registers(const struct sr_dev_inst *sdi, | |
220 | uint8_t (*regs)[2], uint8_t cnt) | |
221 | { | |
222 | uint8_t command[64]; | |
223 | int i; | |
224 | ||
225 | if (cnt < 1 || cnt > 31) | |
226 | return SR_ERR_ARG; | |
227 | ||
228 | command[0] = COMMAND_FPGA_WRITE_REGISTER; | |
229 | command[1] = cnt; | |
230 | for (i = 0; i < cnt; i++) { | |
231 | command[2 + 2 * i] = regs[i][0]; | |
232 | command[3 + 2 * i] = regs[i][1]; | |
233 | } | |
234 | ||
235 | return do_ep1_command(sdi, command, 2 * (cnt + 1), NULL, 0); | |
236 | } | |
237 | ||
238 | static int write_fpga_register(const struct sr_dev_inst *sdi, | |
239 | uint8_t address, uint8_t value) | |
240 | { | |
241 | uint8_t regs[2] = { address, value }; | |
242 | ||
243 | return write_fpga_registers(sdi, ®s, 1); | |
244 | } | |
245 | ||
246 | static uint8_t map_eeprom_data(uint8_t v) | |
247 | { | |
248 | return (((v ^ 0x80) + 0x44) ^ 0xd5) + 0x69; | |
249 | } | |
250 | ||
251 | static int prime_fpga(const struct sr_dev_inst *sdi) | |
252 | { | |
253 | uint8_t eeprom_data[16]; | |
254 | uint8_t old_reg_10, version; | |
255 | uint8_t regs[8][2] = { | |
256 | {10, 0x00}, | |
257 | {10, 0x40}, | |
258 | {12, 0}, | |
259 | {10, 0xc0}, | |
260 | {10, 0x40}, | |
261 | {6, 0}, | |
262 | {7, 1}, | |
263 | {7, 0} | |
264 | }; | |
265 | int i, ret; | |
266 | ||
267 | if ((ret = read_eeprom(sdi, 16, 16, eeprom_data)) != SR_OK) | |
268 | return ret; | |
269 | ||
270 | if ((ret = read_fpga_register(sdi, 10, &old_reg_10)) != SR_OK) | |
271 | return ret; | |
272 | ||
273 | regs[0][1] = (old_reg_10 &= 0x7f); | |
274 | regs[1][1] |= old_reg_10; | |
275 | regs[3][1] |= old_reg_10; | |
276 | regs[4][1] |= old_reg_10; | |
277 | ||
278 | for (i = 0; i < 16; i++) { | |
279 | regs[2][1] = eeprom_data[i]; | |
280 | regs[5][1] = map_eeprom_data(eeprom_data[i]); | |
281 | if (i) | |
282 | ret = write_fpga_registers(sdi, ®s[2], 6); | |
283 | else | |
284 | ret = write_fpga_registers(sdi, ®s[0], 8); | |
285 | if (ret != SR_OK) | |
286 | return ret; | |
287 | } | |
288 | ||
289 | if ((ret = write_fpga_register(sdi, 10, old_reg_10)) != SR_OK) | |
290 | return ret; | |
291 | ||
292 | if ((ret = read_fpga_register(sdi, 0, &version)) != SR_OK) | |
293 | return ret; | |
294 | ||
295 | if (version != 0x10) { | |
296 | sr_err("Invalid FPGA bitstream version: 0x%02x != 0x10.", version); | |
297 | return SR_ERR; | |
298 | } | |
299 | ||
300 | return SR_OK; | |
301 | } | |
302 | ||
303 | static void make_heartbeat(uint8_t *table, int len) | |
304 | { | |
305 | int i, j; | |
306 | ||
307 | memset(table, 0, len); | |
308 | len >>= 3; | |
309 | for (i = 0; i < 2; i++) | |
310 | for (j = 0; j < len; j++) | |
311 | *table++ = sin(j * M_PI / len) * 255; | |
312 | } | |
313 | ||
314 | static int configure_led(const struct sr_dev_inst *sdi) | |
315 | { | |
316 | uint8_t table[64]; | |
317 | int ret; | |
318 | ||
319 | make_heartbeat(table, 64); | |
320 | if ((ret = upload_led_table(sdi, table, 0, 64)) != SR_OK) | |
321 | return ret; | |
322 | ||
323 | return set_led_mode(sdi, 1, 6250, 0, 1); | |
324 | } | |
325 | ||
326 | static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, | |
327 | enum voltage_range vrange) | |
328 | { | |
329 | struct dev_context *devc; | |
330 | int offset, chunksize, ret; | |
331 | const char *filename; | |
332 | uint8_t len, buf[256 * 62], command[64]; | |
333 | FILE *fw; | |
334 | ||
335 | devc = sdi->priv; | |
336 | ||
337 | if (devc->cur_voltage_range == vrange) | |
338 | return SR_OK; | |
339 | ||
340 | switch (vrange) { | |
341 | case VOLTAGE_RANGE_18_33_V: | |
342 | filename = FPGA_FIRMWARE_18; | |
343 | break; | |
344 | case VOLTAGE_RANGE_5_V: | |
345 | filename = FPGA_FIRMWARE_33; | |
346 | break; | |
347 | default: | |
348 | sr_err("Unsupported voltage range."); | |
349 | return SR_ERR; | |
350 | } | |
351 | ||
352 | sr_info("Uploading FPGA bitstream at %s.", filename); | |
353 | if ((fw = g_fopen(filename, "rb")) == NULL) { | |
354 | sr_err("Unable to open bitstream file %s for reading: %s.", | |
355 | filename, strerror(errno)); | |
356 | return SR_ERR; | |
357 | } | |
358 | ||
359 | buf[0] = COMMAND_FPGA_UPLOAD_INIT; | |
360 | if ((ret = do_ep1_command(sdi, buf, 1, NULL, 0)) != SR_OK) { | |
361 | fclose(fw); | |
362 | return ret; | |
363 | } | |
364 | ||
365 | while (1) { | |
366 | chunksize = fread(buf, 1, sizeof(buf), fw); | |
367 | if (chunksize == 0) | |
368 | break; | |
369 | ||
370 | for (offset = 0; offset < chunksize; offset += 62) { | |
371 | len = (offset + 62 > chunksize ? | |
372 | chunksize - offset : 62); | |
373 | command[0] = COMMAND_FPGA_UPLOAD_SEND_DATA; | |
374 | command[1] = len; | |
375 | memcpy(command + 2, buf + offset, len); | |
376 | ret = do_ep1_command(sdi, command, len + 2, NULL, 0); | |
377 | if (ret != SR_OK) { | |
378 | fclose(fw); | |
379 | return ret; | |
380 | } | |
381 | } | |
382 | ||
383 | sr_info("Uploaded %d bytes.", chunksize); | |
384 | } | |
385 | fclose(fw); | |
386 | sr_info("FPGA bitstream upload done."); | |
387 | ||
388 | if ((ret = prime_fpga(sdi)) != SR_OK) | |
389 | return ret; | |
390 | ||
391 | if ((ret = configure_led(sdi)) != SR_OK) | |
392 | return ret; | |
393 | ||
394 | devc->cur_voltage_range = vrange; | |
395 | return SR_OK; | |
396 | } | |
397 | ||
398 | static int abort_acquisition_sync(const struct sr_dev_inst *sdi) | |
399 | { | |
400 | static const uint8_t command[2] = { | |
401 | COMMAND_ABORT_ACQUISITION_SYNC, | |
402 | ABORT_ACQUISITION_SYNC_PATTERN, | |
403 | }; | |
404 | uint8_t reply, expected_reply; | |
405 | int ret; | |
406 | ||
407 | if ((ret = do_ep1_command(sdi, command, 2, &reply, 1)) != SR_OK) | |
408 | return ret; | |
409 | ||
410 | expected_reply = ~command[1]; | |
411 | if (reply != expected_reply) { | |
412 | sr_err("Invalid response for abort acquisition command: " | |
413 | "0x%02x != 0x%02x.", reply, expected_reply); | |
414 | return SR_ERR; | |
415 | } | |
416 | ||
417 | return SR_OK; | |
418 | } | |
419 | ||
420 | SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi, | |
421 | uint64_t samplerate, uint16_t channels) | |
422 | { | |
423 | uint8_t clock_select, reg1, reg10; | |
424 | uint64_t div; | |
425 | int i, ret, nchan = 0; | |
426 | struct dev_context *devc; | |
427 | ||
428 | devc = sdi->priv; | |
429 | ||
430 | if (samplerate == 0 || samplerate > MAX_SAMPLE_RATE) { | |
431 | sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate); | |
432 | return SR_ERR; | |
433 | } | |
434 | ||
435 | if (BASE_CLOCK_0_FREQ % samplerate == 0 && | |
436 | (div = BASE_CLOCK_0_FREQ / samplerate) <= 256) { | |
437 | clock_select = 0; | |
438 | } else if (BASE_CLOCK_1_FREQ % samplerate == 0 && | |
439 | (div = BASE_CLOCK_1_FREQ / samplerate) <= 256) { | |
440 | clock_select = 1; | |
441 | } else { | |
442 | sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate); | |
443 | return SR_ERR; | |
444 | } | |
445 | ||
446 | for (i = 0; i < 16; i++) | |
447 | if (channels & (1U << i)) | |
448 | nchan++; | |
449 | ||
450 | if ((nchan >= 13 && samplerate > MAX_13CH_SAMPLE_RATE) || | |
451 | (nchan >= 10 && samplerate > MAX_10CH_SAMPLE_RATE) || | |
452 | (nchan >= 8 && samplerate > MAX_8CH_SAMPLE_RATE) || | |
453 | (nchan >= 7 && samplerate > MAX_7CH_SAMPLE_RATE) || | |
454 | (nchan >= 4 && samplerate > MAX_4CH_SAMPLE_RATE)) { | |
455 | sr_err("Unable to sample at %" PRIu64 "Hz " | |
456 | "with this many channels.", samplerate); | |
457 | return SR_ERR; | |
458 | } | |
459 | ||
460 | ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range); | |
461 | if (ret != SR_OK) | |
462 | return ret; | |
463 | ||
464 | if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK) | |
465 | return ret; | |
466 | ||
467 | if (reg1 != 0x08) { | |
468 | sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x08.", reg1); | |
469 | return SR_ERR; | |
470 | } | |
471 | ||
472 | if ((ret = write_fpga_register(sdi, 1, 0x40)) != SR_OK) | |
473 | return ret; | |
474 | ||
475 | if ((ret = write_fpga_register(sdi, 10, clock_select)) != SR_OK) | |
476 | return ret; | |
477 | ||
478 | if ((ret = write_fpga_register(sdi, 4, (uint8_t)(div - 1))) != SR_OK) | |
479 | return ret; | |
480 | ||
481 | if ((ret = write_fpga_register(sdi, 2, (uint8_t)(channels & 0xff))) != SR_OK) | |
482 | return ret; | |
483 | ||
484 | if ((ret = write_fpga_register(sdi, 3, (uint8_t)(channels >> 8))) != SR_OK) | |
485 | return ret; | |
486 | ||
487 | if ((ret = write_fpga_register(sdi, 1, 0x42)) != SR_OK) | |
488 | return ret; | |
489 | ||
490 | if ((ret = write_fpga_register(sdi, 1, 0x40)) != SR_OK) | |
491 | return ret; | |
492 | ||
493 | if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK) | |
494 | return ret; | |
495 | ||
496 | if (reg1 != 0x48) { | |
497 | sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x48.", reg1); | |
498 | return SR_ERR; | |
499 | } | |
500 | ||
501 | if ((ret = read_fpga_register(sdi, 10, ®10)) != SR_OK) | |
502 | return ret; | |
503 | ||
504 | if (reg10 != clock_select) { | |
505 | sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x%02x.", | |
506 | reg10, clock_select); | |
507 | return SR_ERR; | |
508 | } | |
509 | ||
510 | return SR_OK; | |
511 | } | |
512 | ||
513 | SR_PRIV int logic16_start_acquisition(const struct sr_dev_inst *sdi) | |
514 | { | |
515 | static const uint8_t command[1] = { | |
516 | COMMAND_START_ACQUISITION, | |
517 | }; | |
518 | int ret; | |
519 | ||
520 | if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK) | |
521 | return ret; | |
522 | ||
523 | return write_fpga_register(sdi, 1, 0x41); | |
524 | } | |
525 | ||
526 | SR_PRIV int logic16_abort_acquisition(const struct sr_dev_inst *sdi) | |
527 | { | |
528 | static const uint8_t command[1] = { | |
529 | COMMAND_ABORT_ACQUISITION_ASYNC, | |
530 | }; | |
531 | int ret; | |
532 | uint8_t reg1, reg8, reg9; | |
533 | ||
534 | if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK) | |
535 | return ret; | |
536 | ||
537 | if ((ret = write_fpga_register(sdi, 1, 0x00)) != SR_OK) | |
538 | return ret; | |
539 | ||
540 | if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK) | |
541 | return ret; | |
542 | ||
543 | if (reg1 != 0x08) { | |
544 | sr_dbg("Invalid state at acquisition stop: 0x%02x != 0x08.", reg1); | |
545 | return SR_ERR; | |
546 | } | |
547 | ||
548 | if ((ret = read_fpga_register(sdi, 8, ®8)) != SR_OK) | |
549 | return ret; | |
550 | ||
551 | if ((ret = read_fpga_register(sdi, 9, ®9)) != SR_OK) | |
552 | return ret; | |
553 | ||
554 | return SR_OK; | |
555 | } | |
556 | ||
557 | SR_PRIV int logic16_init_device(const struct sr_dev_inst *sdi) | |
558 | { | |
559 | struct dev_context *devc; | |
560 | int ret; | |
561 | ||
562 | devc = sdi->priv; | |
563 | ||
564 | devc->cur_voltage_range = VOLTAGE_RANGE_UNKNOWN; | |
565 | ||
566 | if ((ret = abort_acquisition_sync(sdi)) != SR_OK) | |
567 | return ret; | |
568 | ||
569 | if ((ret = read_eeprom(sdi, 8, 8, devc->eeprom_data)) != SR_OK) | |
570 | return ret; | |
571 | ||
572 | ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range); | |
573 | if (ret != SR_OK) | |
574 | return ret; | |
575 | ||
576 | return SR_OK; | |
577 | } | |
578 | ||
579 | static void finish_acquisition(struct dev_context *devc) | |
580 | { | |
581 | struct sr_datafeed_packet packet; | |
582 | ||
583 | /* Terminate session. */ | |
584 | packet.type = SR_DF_END; | |
585 | sr_session_send(devc->cb_data, &packet); | |
586 | ||
587 | /* Remove fds from polling. */ | |
588 | usb_source_remove(devc->ctx); | |
589 | ||
590 | devc->num_transfers = 0; | |
591 | g_free(devc->transfers); | |
592 | g_free(devc->convbuffer); | |
593 | } | |
594 | ||
595 | static void free_transfer(struct libusb_transfer *transfer) | |
596 | { | |
597 | struct dev_context *devc; | |
598 | unsigned int i; | |
599 | ||
600 | devc = transfer->user_data; | |
601 | ||
602 | g_free(transfer->buffer); | |
603 | transfer->buffer = NULL; | |
604 | libusb_free_transfer(transfer); | |
605 | ||
606 | for (i = 0; i < devc->num_transfers; i++) { | |
607 | if (devc->transfers[i] == transfer) { | |
608 | devc->transfers[i] = NULL; | |
609 | break; | |
610 | } | |
611 | } | |
612 | ||
613 | devc->submitted_transfers--; | |
614 | if (devc->submitted_transfers == 0) | |
615 | finish_acquisition(devc); | |
616 | } | |
617 | ||
618 | static void resubmit_transfer(struct libusb_transfer *transfer) | |
619 | { | |
620 | int ret; | |
621 | ||
622 | if ((ret = libusb_submit_transfer(transfer)) == LIBUSB_SUCCESS) | |
623 | return; | |
624 | ||
625 | free_transfer(transfer); | |
626 | /* TODO: Stop session? */ | |
627 | ||
628 | sr_err("%s: %s", __func__, libusb_error_name(ret)); | |
629 | } | |
630 | ||
631 | static size_t convert_sample_data(struct dev_context *devc, | |
632 | uint8_t *dest, size_t destcnt, | |
633 | const uint8_t *src, size_t srccnt) | |
634 | { | |
635 | uint16_t *channel_data; | |
636 | int i, cur_channel; | |
637 | size_t ret = 0; | |
638 | uint16_t sample, channel_mask; | |
639 | ||
640 | srccnt /= 2; | |
641 | ||
642 | channel_data = devc->channel_data; | |
643 | cur_channel = devc->cur_channel; | |
644 | ||
645 | while (srccnt--) { | |
646 | sample = src[0] | (src[1] << 8); | |
647 | src += 2; | |
648 | ||
649 | channel_mask = devc->channel_masks[cur_channel]; | |
650 | ||
651 | for (i = 15; i >= 0; --i, sample >>= 1) | |
652 | if (sample & 1) | |
653 | channel_data[i] |= channel_mask; | |
654 | ||
655 | if (++cur_channel == devc->num_channels) { | |
656 | cur_channel = 0; | |
657 | if (destcnt < 16 * 2) { | |
658 | sr_err("Conversion buffer too small!"); | |
659 | break; | |
660 | } | |
661 | memcpy(dest, channel_data, 16 * 2); | |
662 | memset(channel_data, 0, 16 * 2); | |
663 | dest += 16 * 2; | |
664 | ret += 16 * 2; | |
665 | destcnt -= 16 * 2; | |
666 | } | |
667 | } | |
668 | ||
669 | devc->cur_channel = cur_channel; | |
670 | ||
671 | return ret; | |
672 | } | |
673 | ||
674 | SR_PRIV void logic16_receive_transfer(struct libusb_transfer *transfer) | |
675 | { | |
676 | gboolean packet_has_error = FALSE; | |
677 | struct sr_datafeed_packet packet; | |
678 | struct sr_datafeed_logic logic; | |
679 | struct dev_context *devc; | |
680 | size_t converted_length; | |
681 | ||
682 | devc = transfer->user_data; | |
683 | ||
684 | /* | |
685 | * If acquisition has already ended, just free any queued up | |
686 | * transfer that come in. | |
687 | */ | |
688 | if (devc->num_samples < 0) { | |
689 | free_transfer(transfer); | |
690 | return; | |
691 | } | |
692 | ||
693 | sr_info("receive_transfer(): status %d received %d bytes.", | |
694 | transfer->status, transfer->actual_length); | |
695 | ||
696 | switch (transfer->status) { | |
697 | case LIBUSB_TRANSFER_NO_DEVICE: | |
698 | devc->num_samples = -2; | |
699 | free_transfer(transfer); | |
700 | return; | |
701 | case LIBUSB_TRANSFER_COMPLETED: | |
702 | case LIBUSB_TRANSFER_TIMED_OUT: /* We may have received some data though. */ | |
703 | break; | |
704 | default: | |
705 | packet_has_error = TRUE; | |
706 | break; | |
707 | } | |
708 | ||
709 | if (transfer->actual_length & 1) { | |
710 | sr_err("Got an odd number of bytes from the device. " | |
711 | "This should not happen."); | |
712 | /* Bail out right away. */ | |
713 | packet_has_error = TRUE; | |
714 | devc->empty_transfer_count = MAX_EMPTY_TRANSFERS; | |
715 | } | |
716 | ||
717 | if (transfer->actual_length == 0 || packet_has_error) { | |
718 | devc->empty_transfer_count++; | |
719 | if (devc->empty_transfer_count > MAX_EMPTY_TRANSFERS) { | |
720 | /* | |
721 | * The FX2 gave up. End the acquisition, the frontend | |
722 | * will work out that the samplecount is short. | |
723 | */ | |
724 | devc->num_samples = -2; | |
725 | free_transfer(transfer); | |
726 | } else { | |
727 | resubmit_transfer(transfer); | |
728 | } | |
729 | return; | |
730 | } else { | |
731 | devc->empty_transfer_count = 0; | |
732 | } | |
733 | ||
734 | converted_length = convert_sample_data(devc, devc->convbuffer, | |
735 | devc->convbuffer_size, transfer->buffer, | |
736 | transfer->actual_length); | |
737 | ||
738 | if (converted_length > 0) { | |
739 | /* Cap sample count if needed */ | |
740 | if (devc->limit_samples && | |
741 | (uint64_t)devc->num_samples + converted_length / 2 | |
742 | > devc->limit_samples) { | |
743 | converted_length = | |
744 | (devc->limit_samples - devc->num_samples) * 2; | |
745 | } | |
746 | ||
747 | /* Send the incoming transfer to the session bus. */ | |
748 | packet.type = SR_DF_LOGIC; | |
749 | packet.payload = &logic; | |
750 | logic.length = converted_length; | |
751 | logic.unitsize = 2; | |
752 | logic.data = devc->convbuffer; | |
753 | sr_session_send(devc->cb_data, &packet); | |
754 | ||
755 | devc->num_samples += converted_length / 2; | |
756 | if (devc->limit_samples && | |
757 | (uint64_t)devc->num_samples >= devc->limit_samples) { | |
758 | devc->num_samples = -2; | |
759 | free_transfer(transfer); | |
760 | return; | |
761 | } | |
762 | } | |
763 | ||
764 | resubmit_transfer(transfer); | |
765 | } |