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1 | /* | |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se> | |
5 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
6 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
7 | * | |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #include <config.h> | |
23 | #include <stdint.h> | |
24 | #include <string.h> | |
25 | #include <glib.h> | |
26 | #include <glib/gstdio.h> | |
27 | #include <stdio.h> | |
28 | #include <errno.h> | |
29 | #include <math.h> | |
30 | #include <libsigrok/libsigrok.h> | |
31 | #include "libsigrok-internal.h" | |
32 | #include "protocol.h" | |
33 | ||
34 | #define FPGA_FIRMWARE_18 "saleae-logic16-fpga-18.bitstream" | |
35 | #define FPGA_FIRMWARE_33 "saleae-logic16-fpga-33.bitstream" | |
36 | ||
37 | #define MAX_SAMPLE_RATE SR_MHZ(100) | |
38 | #define MAX_SAMPLE_RATE_X_CH SR_MHZ(300) | |
39 | ||
40 | #define BASE_CLOCK_0_FREQ SR_MHZ(100) | |
41 | #define BASE_CLOCK_1_FREQ SR_MHZ(160) | |
42 | ||
43 | #define COMMAND_START_ACQUISITION 1 | |
44 | #define COMMAND_ABORT_ACQUISITION_ASYNC 2 | |
45 | #define COMMAND_WRITE_EEPROM 6 | |
46 | #define COMMAND_READ_EEPROM 7 | |
47 | #define COMMAND_WRITE_LED_TABLE 0x7a | |
48 | #define COMMAND_SET_LED_MODE 0x7b | |
49 | #define COMMAND_RETURN_TO_BOOTLOADER 0x7c | |
50 | #define COMMAND_ABORT_ACQUISITION_SYNC 0x7d | |
51 | #define COMMAND_FPGA_UPLOAD_INIT 0x7e | |
52 | #define COMMAND_FPGA_UPLOAD_SEND_DATA 0x7f | |
53 | #define COMMAND_FPGA_WRITE_REGISTER 0x80 | |
54 | #define COMMAND_FPGA_READ_REGISTER 0x81 | |
55 | #define COMMAND_GET_REVID 0x82 | |
56 | ||
57 | #define WRITE_EEPROM_COOKIE1 0x42 | |
58 | #define WRITE_EEPROM_COOKIE2 0x55 | |
59 | #define READ_EEPROM_COOKIE1 0x33 | |
60 | #define READ_EEPROM_COOKIE2 0x81 | |
61 | #define ABORT_ACQUISITION_SYNC_PATTERN 0x55 | |
62 | ||
63 | #define MAX_EMPTY_TRANSFERS 64 | |
64 | ||
65 | /* Register mappings for old and new bitstream versions */ | |
66 | ||
67 | enum fpga_register_id { | |
68 | FPGA_REGISTER_VERSION, | |
69 | FPGA_REGISTER_STATUS_CONTROL, | |
70 | FPGA_REGISTER_CHANNEL_SELECT_LOW, | |
71 | FPGA_REGISTER_CHANNEL_SELECT_HIGH, | |
72 | FPGA_REGISTER_SAMPLE_RATE_DIVISOR, | |
73 | FPGA_REGISTER_LED_BRIGHTNESS, | |
74 | FPGA_REGISTER_PRIMER_DATA1, | |
75 | FPGA_REGISTER_PRIMER_CONTROL, | |
76 | FPGA_REGISTER_MODE, | |
77 | FPGA_REGISTER_PRIMER_DATA2, | |
78 | FPGA_REGISTER_MAX = FPGA_REGISTER_PRIMER_DATA2 | |
79 | }; | |
80 | ||
81 | enum fpga_status_control_bit { | |
82 | FPGA_STATUS_CONTROL_BIT_RUNNING, | |
83 | FPGA_STATUS_CONTROL_BIT_UPDATE, | |
84 | FPGA_STATUS_CONTROL_BIT_UNKNOWN1, | |
85 | FPGA_STATUS_CONTROL_BIT_OVERFLOW, | |
86 | FPGA_STATUS_CONTROL_BIT_UNKNOWN2, | |
87 | FPGA_STATUS_CONTROL_BIT_MAX = FPGA_STATUS_CONTROL_BIT_UNKNOWN2 | |
88 | }; | |
89 | ||
90 | enum fpga_mode_bit { | |
91 | FPGA_MODE_BIT_CLOCK, | |
92 | FPGA_MODE_BIT_UNKNOWN1, | |
93 | FPGA_MODE_BIT_UNKNOWN2, | |
94 | FPGA_MODE_BIT_MAX = FPGA_MODE_BIT_UNKNOWN2 | |
95 | }; | |
96 | ||
97 | static const uint8_t fpga_register_map_old[FPGA_REGISTER_MAX + 1] = { | |
98 | [FPGA_REGISTER_VERSION] = 0, | |
99 | [FPGA_REGISTER_STATUS_CONTROL] = 1, | |
100 | [FPGA_REGISTER_CHANNEL_SELECT_LOW] = 2, | |
101 | [FPGA_REGISTER_CHANNEL_SELECT_HIGH] = 3, | |
102 | [FPGA_REGISTER_SAMPLE_RATE_DIVISOR] = 4, | |
103 | [FPGA_REGISTER_LED_BRIGHTNESS] = 5, | |
104 | [FPGA_REGISTER_PRIMER_DATA1] = 6, | |
105 | [FPGA_REGISTER_PRIMER_CONTROL] = 7, | |
106 | [FPGA_REGISTER_MODE] = 10, | |
107 | [FPGA_REGISTER_PRIMER_DATA2] = 12, | |
108 | }; | |
109 | ||
110 | static const uint8_t fpga_register_map_new[FPGA_REGISTER_MAX + 1] = { | |
111 | [FPGA_REGISTER_VERSION] = 7, | |
112 | [FPGA_REGISTER_STATUS_CONTROL] = 15, | |
113 | [FPGA_REGISTER_CHANNEL_SELECT_LOW] = 1, | |
114 | [FPGA_REGISTER_CHANNEL_SELECT_HIGH] = 6, | |
115 | [FPGA_REGISTER_SAMPLE_RATE_DIVISOR] = 11, | |
116 | [FPGA_REGISTER_LED_BRIGHTNESS] = 5, | |
117 | [FPGA_REGISTER_PRIMER_DATA1] = 14, | |
118 | [FPGA_REGISTER_PRIMER_CONTROL] = 2, | |
119 | [FPGA_REGISTER_MODE] = 4, | |
120 | [FPGA_REGISTER_PRIMER_DATA2] = 3, | |
121 | }; | |
122 | ||
123 | static const uint8_t fpga_status_control_bit_map_old[FPGA_STATUS_CONTROL_BIT_MAX + 1] = { | |
124 | [FPGA_STATUS_CONTROL_BIT_RUNNING] = 0x01, | |
125 | [FPGA_STATUS_CONTROL_BIT_UPDATE] = 0x02, | |
126 | [FPGA_STATUS_CONTROL_BIT_UNKNOWN1] = 0x08, | |
127 | [FPGA_STATUS_CONTROL_BIT_OVERFLOW] = 0x20, | |
128 | [FPGA_STATUS_CONTROL_BIT_UNKNOWN2] = 0x40, | |
129 | }; | |
130 | ||
131 | static const uint8_t fpga_status_control_bit_map_new[FPGA_STATUS_CONTROL_BIT_MAX + 1] = { | |
132 | [FPGA_STATUS_CONTROL_BIT_RUNNING] = 0x20, | |
133 | [FPGA_STATUS_CONTROL_BIT_UPDATE] = 0x08, | |
134 | [FPGA_STATUS_CONTROL_BIT_UNKNOWN1] = 0x10, | |
135 | [FPGA_STATUS_CONTROL_BIT_OVERFLOW] = 0x01, | |
136 | [FPGA_STATUS_CONTROL_BIT_UNKNOWN2] = 0x04, | |
137 | }; | |
138 | ||
139 | static const uint8_t fpga_mode_bit_map_old[FPGA_MODE_BIT_MAX + 1] = { | |
140 | [FPGA_MODE_BIT_CLOCK] = 0x01, | |
141 | [FPGA_MODE_BIT_UNKNOWN1] = 0x40, | |
142 | [FPGA_MODE_BIT_UNKNOWN2] = 0x80, | |
143 | }; | |
144 | ||
145 | static const uint8_t fpga_mode_bit_map_new[FPGA_MODE_BIT_MAX + 1] = { | |
146 | [FPGA_MODE_BIT_CLOCK] = 0x04, | |
147 | [FPGA_MODE_BIT_UNKNOWN1] = 0x80, | |
148 | [FPGA_MODE_BIT_UNKNOWN2] = 0x01, | |
149 | }; | |
150 | ||
151 | #define FPGA_REG(x) \ | |
152 | (devc->fpga_register_map[FPGA_REGISTER_ ## x]) | |
153 | ||
154 | #define FPGA_STATUS_CONTROL(x) \ | |
155 | (devc->fpga_status_control_bit_map[FPGA_STATUS_CONTROL_BIT_ ## x]) | |
156 | ||
157 | #define FPGA_MODE(x) \ | |
158 | (devc->fpga_mode_bit_map[FPGA_MODE_BIT_ ## x]) | |
159 | ||
160 | static void encrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt) | |
161 | { | |
162 | uint8_t state1 = 0x9b, state2 = 0x54; | |
163 | uint8_t t, v; | |
164 | int i; | |
165 | ||
166 | for (i = 0; i < cnt; i++) { | |
167 | v = src[i]; | |
168 | t = (((v ^ state2 ^ 0x2b) - 0x05) ^ 0x35) - 0x39; | |
169 | t = (((t ^ state1 ^ 0x5a) - 0xb0) ^ 0x38) - 0x45; | |
170 | dest[i] = state2 = t; | |
171 | state1 = v; | |
172 | } | |
173 | } | |
174 | ||
175 | static void decrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt) | |
176 | { | |
177 | uint8_t state1 = 0x9b, state2 = 0x54; | |
178 | uint8_t t, v; | |
179 | int i; | |
180 | ||
181 | for (i = 0; i < cnt; i++) { | |
182 | v = src[i]; | |
183 | t = (((v + 0x45) ^ 0x38) + 0xb0) ^ 0x5a ^ state1; | |
184 | t = (((t + 0x39) ^ 0x35) + 0x05) ^ 0x2b ^ state2; | |
185 | dest[i] = state1 = t; | |
186 | state2 = v; | |
187 | } | |
188 | } | |
189 | ||
190 | static int do_ep1_command(const struct sr_dev_inst *sdi, | |
191 | const uint8_t *command, uint8_t cmd_len, | |
192 | uint8_t *reply, uint8_t reply_len) | |
193 | { | |
194 | uint8_t buf[64]; | |
195 | struct sr_usb_dev_inst *usb; | |
196 | int ret, xfer; | |
197 | ||
198 | usb = sdi->conn; | |
199 | ||
200 | if (cmd_len < 1 || cmd_len > 64 || reply_len > 64 || | |
201 | !command || (reply_len > 0 && !reply)) | |
202 | return SR_ERR_ARG; | |
203 | ||
204 | encrypt(buf, command, cmd_len); | |
205 | ||
206 | ret = libusb_bulk_transfer(usb->devhdl, 1, buf, cmd_len, &xfer, 1000); | |
207 | if (ret != 0) { | |
208 | sr_dbg("Failed to send EP1 command 0x%02x: %s.", | |
209 | command[0], libusb_error_name(ret)); | |
210 | return SR_ERR; | |
211 | } | |
212 | if (xfer != cmd_len) { | |
213 | sr_dbg("Failed to send EP1 command 0x%02x: incorrect length " | |
214 | "%d != %d.", command[0], xfer, cmd_len); | |
215 | return SR_ERR; | |
216 | } | |
217 | ||
218 | if (reply_len == 0) | |
219 | return SR_OK; | |
220 | ||
221 | ret = libusb_bulk_transfer(usb->devhdl, 0x80 | 1, buf, reply_len, | |
222 | &xfer, 1000); | |
223 | if (ret != 0) { | |
224 | sr_dbg("Failed to receive reply to EP1 command 0x%02x: %s.", | |
225 | command[0], libusb_error_name(ret)); | |
226 | return SR_ERR; | |
227 | } | |
228 | if (xfer != reply_len) { | |
229 | sr_dbg("Failed to receive reply to EP1 command 0x%02x: " | |
230 | "incorrect length %d != %d.", command[0], xfer, reply_len); | |
231 | return SR_ERR; | |
232 | } | |
233 | ||
234 | decrypt(reply, buf, reply_len); | |
235 | ||
236 | return SR_OK; | |
237 | } | |
238 | ||
239 | static int read_eeprom(const struct sr_dev_inst *sdi, | |
240 | uint8_t address, uint8_t length, uint8_t *buf) | |
241 | { | |
242 | uint8_t command[5] = { | |
243 | COMMAND_READ_EEPROM, | |
244 | READ_EEPROM_COOKIE1, | |
245 | READ_EEPROM_COOKIE2, | |
246 | address, | |
247 | length, | |
248 | }; | |
249 | ||
250 | return do_ep1_command(sdi, command, 5, buf, length); | |
251 | } | |
252 | ||
253 | static int upload_led_table(const struct sr_dev_inst *sdi, | |
254 | const uint8_t *table, uint8_t offset, uint8_t cnt) | |
255 | { | |
256 | uint8_t chunk, command[64]; | |
257 | int ret; | |
258 | ||
259 | if (cnt < 1 || cnt + offset > 64 || !table) | |
260 | return SR_ERR_ARG; | |
261 | ||
262 | while (cnt > 0) { | |
263 | chunk = (cnt > 32 ? 32 : cnt); | |
264 | ||
265 | command[0] = COMMAND_WRITE_LED_TABLE; | |
266 | command[1] = offset; | |
267 | command[2] = chunk; | |
268 | memcpy(command + 3, table, chunk); | |
269 | ||
270 | ret = do_ep1_command(sdi, command, 3 + chunk, NULL, 0); | |
271 | if (ret != SR_OK) | |
272 | return ret; | |
273 | ||
274 | table += chunk; | |
275 | offset += chunk; | |
276 | cnt -= chunk; | |
277 | } | |
278 | ||
279 | return SR_OK; | |
280 | } | |
281 | ||
282 | static int set_led_mode(const struct sr_dev_inst *sdi, | |
283 | uint8_t animate, uint16_t t2reload, uint8_t div, | |
284 | uint8_t repeat) | |
285 | { | |
286 | uint8_t command[6] = { | |
287 | COMMAND_SET_LED_MODE, | |
288 | animate, | |
289 | t2reload & 0xff, | |
290 | t2reload >> 8, | |
291 | div, | |
292 | repeat, | |
293 | }; | |
294 | ||
295 | return do_ep1_command(sdi, command, 6, NULL, 0); | |
296 | } | |
297 | ||
298 | static int read_fpga_register(const struct sr_dev_inst *sdi, | |
299 | uint8_t address, uint8_t *value) | |
300 | { | |
301 | uint8_t command[3] = { | |
302 | COMMAND_FPGA_READ_REGISTER, | |
303 | 1, | |
304 | address, | |
305 | }; | |
306 | ||
307 | return do_ep1_command(sdi, command, 3, value, 1); | |
308 | } | |
309 | ||
310 | static int write_fpga_registers(const struct sr_dev_inst *sdi, | |
311 | uint8_t (*regs)[2], uint8_t cnt) | |
312 | { | |
313 | uint8_t command[64]; | |
314 | int i; | |
315 | ||
316 | if (cnt < 1 || cnt > 31) | |
317 | return SR_ERR_ARG; | |
318 | ||
319 | command[0] = COMMAND_FPGA_WRITE_REGISTER; | |
320 | command[1] = cnt; | |
321 | for (i = 0; i < cnt; i++) { | |
322 | command[2 + 2 * i] = regs[i][0]; | |
323 | command[3 + 2 * i] = regs[i][1]; | |
324 | } | |
325 | ||
326 | return do_ep1_command(sdi, command, 2 * (cnt + 1), NULL, 0); | |
327 | } | |
328 | ||
329 | static int write_fpga_register(const struct sr_dev_inst *sdi, | |
330 | uint8_t address, uint8_t value) | |
331 | { | |
332 | uint8_t regs[2] = { address, value }; | |
333 | ||
334 | return write_fpga_registers(sdi, ®s, 1); | |
335 | } | |
336 | ||
337 | static uint8_t map_eeprom_data(uint8_t v) | |
338 | { | |
339 | return (((v ^ 0x80) + 0x44) ^ 0xd5) + 0x69; | |
340 | } | |
341 | ||
342 | static int setup_register_mapping(const struct sr_dev_inst *sdi) | |
343 | { | |
344 | struct dev_context *devc; | |
345 | int ret; | |
346 | ||
347 | devc = sdi->priv; | |
348 | ||
349 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO) { | |
350 | uint8_t reg0, reg7; | |
351 | ||
352 | /* | |
353 | * Check for newer bitstream version by polling the | |
354 | * version register at the old and new location. | |
355 | */ | |
356 | ||
357 | if ((ret = read_fpga_register(sdi, 0 /* No mapping */, ®0)) != SR_OK) | |
358 | return ret; | |
359 | ||
360 | if ((ret = read_fpga_register(sdi, 7 /* No mapping */, ®7)) != SR_OK) | |
361 | return ret; | |
362 | ||
363 | if (reg0 == 0 && reg7 > 0x10) { | |
364 | sr_info("Original Saleae Logic16 using new bitstream."); | |
365 | devc->fpga_variant = FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM; | |
366 | } else { | |
367 | sr_info("Original Saleae Logic16 using old bitstream."); | |
368 | devc->fpga_variant = FPGA_VARIANT_ORIGINAL; | |
369 | } | |
370 | } | |
371 | ||
372 | if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM) { | |
373 | devc->fpga_register_map = fpga_register_map_new; | |
374 | devc->fpga_status_control_bit_map = fpga_status_control_bit_map_new; | |
375 | devc->fpga_mode_bit_map = fpga_mode_bit_map_new; | |
376 | } else { | |
377 | devc->fpga_register_map = fpga_register_map_old; | |
378 | devc->fpga_status_control_bit_map = fpga_status_control_bit_map_old; | |
379 | devc->fpga_mode_bit_map = fpga_mode_bit_map_old; | |
380 | } | |
381 | ||
382 | return SR_OK; | |
383 | } | |
384 | ||
385 | static int prime_fpga(const struct sr_dev_inst *sdi) | |
386 | { | |
387 | struct dev_context *devc = sdi->priv; | |
388 | uint8_t eeprom_data[16]; | |
389 | uint8_t old_mode_reg, version; | |
390 | uint8_t regs[8][2] = { | |
391 | {FPGA_REG(MODE), 0x00}, | |
392 | {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1)}, | |
393 | {FPGA_REG(PRIMER_DATA2), 0}, | |
394 | {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1) | FPGA_MODE(UNKNOWN2)}, | |
395 | {FPGA_REG(MODE), FPGA_MODE(UNKNOWN1)}, | |
396 | {FPGA_REG(PRIMER_DATA1), 0}, | |
397 | {FPGA_REG(PRIMER_CONTROL), 1}, | |
398 | {FPGA_REG(PRIMER_CONTROL), 0} | |
399 | }; | |
400 | int i, ret; | |
401 | ||
402 | if ((ret = read_eeprom(sdi, 16, 16, eeprom_data)) != SR_OK) | |
403 | return ret; | |
404 | ||
405 | if ((ret = read_fpga_register(sdi, FPGA_REG(MODE), &old_mode_reg)) != SR_OK) | |
406 | return ret; | |
407 | ||
408 | regs[0][1] = (old_mode_reg &= ~FPGA_MODE(UNKNOWN2)); | |
409 | regs[1][1] |= old_mode_reg; | |
410 | regs[3][1] |= old_mode_reg; | |
411 | regs[4][1] |= old_mode_reg; | |
412 | ||
413 | for (i = 0; i < 16; i++) { | |
414 | regs[2][1] = eeprom_data[i]; | |
415 | regs[5][1] = map_eeprom_data(eeprom_data[i]); | |
416 | if (i) | |
417 | ret = write_fpga_registers(sdi, ®s[2], 6); | |
418 | else | |
419 | ret = write_fpga_registers(sdi, ®s[0], 8); | |
420 | if (ret != SR_OK) | |
421 | return ret; | |
422 | } | |
423 | ||
424 | if ((ret = write_fpga_register(sdi, FPGA_REG(MODE), old_mode_reg)) != SR_OK) | |
425 | return ret; | |
426 | ||
427 | if ((ret = read_fpga_register(sdi, FPGA_REG(VERSION), &version)) != SR_OK) | |
428 | return ret; | |
429 | ||
430 | if (version != 0x10 && version != 0x13 && version != 0x40 && version != 0x41) { | |
431 | sr_err("Unsupported FPGA version: 0x%02x.", version); | |
432 | return SR_ERR; | |
433 | } | |
434 | ||
435 | return SR_OK; | |
436 | } | |
437 | ||
438 | static void make_heartbeat(uint8_t *table, int len) | |
439 | { | |
440 | int i, j; | |
441 | ||
442 | memset(table, 0, len); | |
443 | len >>= 3; | |
444 | for (i = 0; i < 2; i++) | |
445 | for (j = 0; j < len; j++) | |
446 | *table++ = sin(j * G_PI / len) * 255; | |
447 | } | |
448 | ||
449 | static int configure_led(const struct sr_dev_inst *sdi) | |
450 | { | |
451 | uint8_t table[64]; | |
452 | int ret; | |
453 | ||
454 | make_heartbeat(table, 64); | |
455 | if ((ret = upload_led_table(sdi, table, 0, 64)) != SR_OK) | |
456 | return ret; | |
457 | ||
458 | return set_led_mode(sdi, 1, 6250, 0, 1); | |
459 | } | |
460 | ||
461 | static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, | |
462 | enum voltage_range vrange) | |
463 | { | |
464 | uint64_t sum; | |
465 | struct sr_resource bitstream; | |
466 | struct dev_context *devc; | |
467 | struct drv_context *drvc; | |
468 | const char *name; | |
469 | ssize_t chunksize; | |
470 | int ret; | |
471 | uint8_t command[64]; | |
472 | ||
473 | devc = sdi->priv; | |
474 | drvc = sdi->driver->context; | |
475 | ||
476 | if (devc->cur_voltage_range == vrange) | |
477 | return SR_OK; | |
478 | ||
479 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO) { | |
480 | switch (vrange) { | |
481 | case VOLTAGE_RANGE_18_33_V: | |
482 | name = FPGA_FIRMWARE_18; | |
483 | break; | |
484 | case VOLTAGE_RANGE_5_V: | |
485 | name = FPGA_FIRMWARE_33; | |
486 | break; | |
487 | default: | |
488 | sr_err("Unsupported voltage range."); | |
489 | return SR_ERR; | |
490 | } | |
491 | ||
492 | sr_info("Uploading FPGA bitstream '%s'.", name); | |
493 | ret = sr_resource_open(drvc->sr_ctx, &bitstream, | |
494 | SR_RESOURCE_FIRMWARE, name); | |
495 | if (ret != SR_OK) | |
496 | return ret; | |
497 | ||
498 | command[0] = COMMAND_FPGA_UPLOAD_INIT; | |
499 | if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK) { | |
500 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
501 | return ret; | |
502 | } | |
503 | ||
504 | sum = 0; | |
505 | while (1) { | |
506 | chunksize = sr_resource_read(drvc->sr_ctx, &bitstream, | |
507 | &command[2], sizeof(command) - 2); | |
508 | if (chunksize < 0) { | |
509 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
510 | return SR_ERR; | |
511 | } | |
512 | if (chunksize == 0) | |
513 | break; | |
514 | command[0] = COMMAND_FPGA_UPLOAD_SEND_DATA; | |
515 | command[1] = chunksize; | |
516 | ||
517 | ret = do_ep1_command(sdi, command, chunksize + 2, | |
518 | NULL, 0); | |
519 | if (ret != SR_OK) { | |
520 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
521 | return ret; | |
522 | } | |
523 | sum += chunksize; | |
524 | } | |
525 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
526 | sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", sum); | |
527 | } | |
528 | ||
529 | /* This needs to be called before accessing any FPGA registers. */ | |
530 | if ((ret = setup_register_mapping(sdi)) != SR_OK) | |
531 | return ret; | |
532 | ||
533 | if ((ret = prime_fpga(sdi)) != SR_OK) | |
534 | return ret; | |
535 | ||
536 | if ((ret = configure_led(sdi)) != SR_OK) | |
537 | return ret; | |
538 | ||
539 | devc->cur_voltage_range = vrange; | |
540 | return SR_OK; | |
541 | } | |
542 | ||
543 | static int abort_acquisition_sync(const struct sr_dev_inst *sdi) | |
544 | { | |
545 | static const uint8_t command[2] = { | |
546 | COMMAND_ABORT_ACQUISITION_SYNC, | |
547 | ABORT_ACQUISITION_SYNC_PATTERN, | |
548 | }; | |
549 | uint8_t reply, expected_reply; | |
550 | int ret; | |
551 | ||
552 | if ((ret = do_ep1_command(sdi, command, 2, &reply, 1)) != SR_OK) | |
553 | return ret; | |
554 | ||
555 | expected_reply = ~command[1]; | |
556 | if (reply != expected_reply) { | |
557 | sr_err("Invalid response for abort acquisition command: " | |
558 | "0x%02x != 0x%02x.", reply, expected_reply); | |
559 | return SR_ERR; | |
560 | } | |
561 | ||
562 | return SR_OK; | |
563 | } | |
564 | ||
565 | SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi, | |
566 | uint64_t samplerate, uint16_t channels) | |
567 | { | |
568 | uint8_t clock_select, sta_con_reg, mode_reg; | |
569 | uint64_t div; | |
570 | int i, ret, nchan = 0; | |
571 | struct dev_context *devc; | |
572 | ||
573 | devc = sdi->priv; | |
574 | ||
575 | if (samplerate == 0 || samplerate > MAX_SAMPLE_RATE) { | |
576 | sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate); | |
577 | return SR_ERR; | |
578 | } | |
579 | ||
580 | if (BASE_CLOCK_0_FREQ % samplerate == 0 && | |
581 | (div = BASE_CLOCK_0_FREQ / samplerate) <= 256) { | |
582 | clock_select = 0; | |
583 | } else if (BASE_CLOCK_1_FREQ % samplerate == 0 && | |
584 | (div = BASE_CLOCK_1_FREQ / samplerate) <= 256) { | |
585 | clock_select = 1; | |
586 | } else { | |
587 | sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate); | |
588 | return SR_ERR; | |
589 | } | |
590 | ||
591 | for (i = 0; i < 16; i++) | |
592 | if (channels & (1U << i)) | |
593 | nchan++; | |
594 | ||
595 | if (nchan * samplerate > MAX_SAMPLE_RATE_X_CH) { | |
596 | sr_err("Unable to sample at %" PRIu64 "Hz " | |
597 | "with this many channels.", samplerate); | |
598 | return SR_ERR; | |
599 | } | |
600 | ||
601 | ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range); | |
602 | if (ret != SR_OK) | |
603 | return ret; | |
604 | ||
605 | if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK) | |
606 | return ret; | |
607 | ||
608 | /* Ignore FIFO overflow on previous capture */ | |
609 | sta_con_reg &= ~FPGA_STATUS_CONTROL(OVERFLOW); | |
610 | ||
611 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg != FPGA_STATUS_CONTROL(UNKNOWN1)) { | |
612 | sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x%02x. " | |
613 | "Proceeding anyway.", sta_con_reg, FPGA_STATUS_CONTROL(UNKNOWN1)); | |
614 | } | |
615 | ||
616 | if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2))) != SR_OK) | |
617 | return ret; | |
618 | ||
619 | if ((ret = write_fpga_register(sdi, FPGA_REG(MODE), (clock_select? FPGA_MODE(CLOCK) : 0))) != SR_OK) | |
620 | return ret; | |
621 | ||
622 | if ((ret = write_fpga_register(sdi, FPGA_REG(SAMPLE_RATE_DIVISOR), (uint8_t)(div - 1))) != SR_OK) | |
623 | return ret; | |
624 | ||
625 | if ((ret = write_fpga_register(sdi, FPGA_REG(CHANNEL_SELECT_LOW), (uint8_t)(channels & 0xff))) != SR_OK) | |
626 | return ret; | |
627 | ||
628 | if ((ret = write_fpga_register(sdi, FPGA_REG(CHANNEL_SELECT_HIGH), (uint8_t)(channels >> 8))) != SR_OK) | |
629 | return ret; | |
630 | ||
631 | if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UPDATE))) != SR_OK) | |
632 | return ret; | |
633 | ||
634 | if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2))) != SR_OK) | |
635 | return ret; | |
636 | ||
637 | if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK) | |
638 | return ret; | |
639 | ||
640 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg != (FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UNKNOWN1))) { | |
641 | sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x%02x. " | |
642 | "Proceeding anyway.", sta_con_reg, FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(UNKNOWN1)); | |
643 | } | |
644 | ||
645 | if ((ret = read_fpga_register(sdi, FPGA_REG(MODE), &mode_reg)) != SR_OK) | |
646 | return ret; | |
647 | ||
648 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && mode_reg != (clock_select? FPGA_MODE(CLOCK) : 0)) { | |
649 | sr_dbg("Invalid state at acquisition setup register 10: 0x%02x != 0x%02x. " | |
650 | "Proceeding anyway.", mode_reg, (clock_select? FPGA_MODE(CLOCK) : 0)); | |
651 | } | |
652 | ||
653 | return SR_OK; | |
654 | } | |
655 | ||
656 | SR_PRIV int logic16_start_acquisition(const struct sr_dev_inst *sdi) | |
657 | { | |
658 | static const uint8_t command[1] = { | |
659 | COMMAND_START_ACQUISITION, | |
660 | }; | |
661 | int ret; | |
662 | struct dev_context *devc; | |
663 | ||
664 | devc = sdi->priv; | |
665 | ||
666 | if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK) | |
667 | return ret; | |
668 | ||
669 | return write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), FPGA_STATUS_CONTROL(UNKNOWN2) | FPGA_STATUS_CONTROL(RUNNING)); | |
670 | } | |
671 | ||
672 | SR_PRIV int logic16_abort_acquisition(const struct sr_dev_inst *sdi) | |
673 | { | |
674 | static const uint8_t command[1] = { | |
675 | COMMAND_ABORT_ACQUISITION_ASYNC, | |
676 | }; | |
677 | int ret; | |
678 | uint8_t sta_con_reg; | |
679 | struct dev_context *devc; | |
680 | ||
681 | devc = sdi->priv; | |
682 | ||
683 | if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK) | |
684 | return ret; | |
685 | ||
686 | if ((ret = write_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), 0x00)) != SR_OK) | |
687 | return ret; | |
688 | ||
689 | if ((ret = read_fpga_register(sdi, FPGA_REG(STATUS_CONTROL), &sta_con_reg)) != SR_OK) | |
690 | return ret; | |
691 | ||
692 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && (sta_con_reg & ~FPGA_STATUS_CONTROL(OVERFLOW)) != FPGA_STATUS_CONTROL(UNKNOWN1)) { | |
693 | sr_dbg("Invalid state at acquisition stop: 0x%02x != 0x%02x.", sta_con_reg & ~0x20, FPGA_STATUS_CONTROL(UNKNOWN1)); | |
694 | return SR_ERR; | |
695 | } | |
696 | ||
697 | ||
698 | if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL) { | |
699 | uint8_t reg8, reg9; | |
700 | ||
701 | if ((ret = read_fpga_register(sdi, 8, ®8)) != SR_OK) | |
702 | return ret; | |
703 | ||
704 | if ((ret = read_fpga_register(sdi, 9, ®9)) != SR_OK) | |
705 | return ret; | |
706 | } | |
707 | ||
708 | if (devc->fpga_variant != FPGA_VARIANT_MCUPRO && sta_con_reg & FPGA_STATUS_CONTROL(OVERFLOW)) { | |
709 | sr_warn("FIFO overflow, capture data may be truncated."); | |
710 | return SR_ERR; | |
711 | } | |
712 | ||
713 | return SR_OK; | |
714 | } | |
715 | ||
716 | SR_PRIV int logic16_init_device(const struct sr_dev_inst *sdi) | |
717 | { | |
718 | uint8_t version; | |
719 | struct dev_context *devc; | |
720 | int ret; | |
721 | ||
722 | devc = sdi->priv; | |
723 | ||
724 | devc->cur_voltage_range = VOLTAGE_RANGE_UNKNOWN; | |
725 | ||
726 | if ((ret = abort_acquisition_sync(sdi)) != SR_OK) | |
727 | return ret; | |
728 | ||
729 | if ((ret = read_eeprom(sdi, 8, 8, devc->eeprom_data)) != SR_OK) | |
730 | return ret; | |
731 | ||
732 | /* mcupro Saleae16 has firmware pre-stored in FPGA. | |
733 | So, we can query it right away. */ | |
734 | if (read_fpga_register(sdi, 0 /* No mapping */, &version) == SR_OK && | |
735 | (version == 0x40 || version == 0x41)) { | |
736 | sr_info("mcupro Saleae16 detected."); | |
737 | devc->fpga_variant = FPGA_VARIANT_MCUPRO; | |
738 | } else { | |
739 | sr_info("Original Saleae Logic16 detected."); | |
740 | devc->fpga_variant = FPGA_VARIANT_ORIGINAL; | |
741 | } | |
742 | ||
743 | ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range); | |
744 | if (ret != SR_OK) | |
745 | return ret; | |
746 | ||
747 | return SR_OK; | |
748 | } | |
749 | ||
750 | static void finish_acquisition(struct sr_dev_inst *sdi) | |
751 | { | |
752 | struct dev_context *devc; | |
753 | ||
754 | devc = sdi->priv; | |
755 | ||
756 | std_session_send_df_end(sdi); | |
757 | ||
758 | usb_source_remove(sdi->session, devc->ctx); | |
759 | ||
760 | devc->num_transfers = 0; | |
761 | g_free(devc->transfers); | |
762 | g_free(devc->convbuffer); | |
763 | if (devc->stl) { | |
764 | soft_trigger_logic_free(devc->stl); | |
765 | devc->stl = NULL; | |
766 | } | |
767 | } | |
768 | ||
769 | static void free_transfer(struct libusb_transfer *transfer) | |
770 | { | |
771 | struct sr_dev_inst *sdi; | |
772 | struct dev_context *devc; | |
773 | unsigned int i; | |
774 | ||
775 | sdi = transfer->user_data; | |
776 | devc = sdi->priv; | |
777 | ||
778 | g_free(transfer->buffer); | |
779 | transfer->buffer = NULL; | |
780 | libusb_free_transfer(transfer); | |
781 | ||
782 | for (i = 0; i < devc->num_transfers; i++) { | |
783 | if (devc->transfers[i] == transfer) { | |
784 | devc->transfers[i] = NULL; | |
785 | break; | |
786 | } | |
787 | } | |
788 | ||
789 | devc->submitted_transfers--; | |
790 | if (devc->submitted_transfers == 0) | |
791 | finish_acquisition(sdi); | |
792 | } | |
793 | ||
794 | static void resubmit_transfer(struct libusb_transfer *transfer) | |
795 | { | |
796 | int ret; | |
797 | ||
798 | if ((ret = libusb_submit_transfer(transfer)) == LIBUSB_SUCCESS) | |
799 | return; | |
800 | ||
801 | free_transfer(transfer); | |
802 | /* TODO: Stop session? */ | |
803 | ||
804 | sr_err("%s: %s", __func__, libusb_error_name(ret)); | |
805 | } | |
806 | ||
807 | static size_t convert_sample_data(struct dev_context *devc, | |
808 | uint8_t *dest, size_t destcnt, const uint8_t *src, size_t srccnt) | |
809 | { | |
810 | uint16_t *channel_data; | |
811 | int i, cur_channel; | |
812 | size_t ret = 0; | |
813 | uint16_t sample, channel_mask; | |
814 | ||
815 | srccnt /= 2; | |
816 | ||
817 | channel_data = devc->channel_data; | |
818 | cur_channel = devc->cur_channel; | |
819 | ||
820 | while (srccnt--) { | |
821 | sample = src[0] | (src[1] << 8); | |
822 | src += 2; | |
823 | ||
824 | channel_mask = devc->channel_masks[cur_channel]; | |
825 | ||
826 | for (i = 15; i >= 0; --i, sample >>= 1) | |
827 | if (sample & 1) | |
828 | channel_data[i] |= channel_mask; | |
829 | ||
830 | if (++cur_channel == devc->num_channels) { | |
831 | cur_channel = 0; | |
832 | if (destcnt < 16 * 2) { | |
833 | sr_err("Conversion buffer too small!"); | |
834 | break; | |
835 | } | |
836 | memcpy(dest, channel_data, 16 * 2); | |
837 | memset(channel_data, 0, 16 * 2); | |
838 | dest += 16 * 2; | |
839 | ret += 16; | |
840 | destcnt -= 16 * 2; | |
841 | } | |
842 | } | |
843 | ||
844 | devc->cur_channel = cur_channel; | |
845 | ||
846 | return ret; | |
847 | } | |
848 | ||
849 | SR_PRIV void LIBUSB_CALL logic16_receive_transfer(struct libusb_transfer *transfer) | |
850 | { | |
851 | gboolean packet_has_error = FALSE; | |
852 | struct sr_datafeed_packet packet; | |
853 | struct sr_datafeed_logic logic; | |
854 | struct sr_dev_inst *sdi; | |
855 | struct dev_context *devc; | |
856 | size_t new_samples, num_samples; | |
857 | int trigger_offset; | |
858 | int pre_trigger_samples; | |
859 | ||
860 | sdi = transfer->user_data; | |
861 | devc = sdi->priv; | |
862 | ||
863 | /* | |
864 | * If acquisition has already ended, just free any queued up | |
865 | * transfer that come in. | |
866 | */ | |
867 | if (devc->sent_samples < 0) { | |
868 | free_transfer(transfer); | |
869 | return; | |
870 | } | |
871 | ||
872 | sr_info("receive_transfer(): status %s received %d bytes.", | |
873 | libusb_error_name(transfer->status), transfer->actual_length); | |
874 | ||
875 | switch (transfer->status) { | |
876 | case LIBUSB_TRANSFER_NO_DEVICE: | |
877 | devc->sent_samples = -2; | |
878 | free_transfer(transfer); | |
879 | return; | |
880 | case LIBUSB_TRANSFER_COMPLETED: | |
881 | case LIBUSB_TRANSFER_TIMED_OUT: /* We may have received some data though. */ | |
882 | break; | |
883 | default: | |
884 | packet_has_error = TRUE; | |
885 | break; | |
886 | } | |
887 | ||
888 | if (transfer->actual_length & 1) { | |
889 | sr_err("Got an odd number of bytes from the device. " | |
890 | "This should not happen."); | |
891 | /* Bail out right away. */ | |
892 | packet_has_error = TRUE; | |
893 | devc->empty_transfer_count = MAX_EMPTY_TRANSFERS; | |
894 | } | |
895 | ||
896 | if (transfer->actual_length == 0 || packet_has_error) { | |
897 | devc->empty_transfer_count++; | |
898 | if (devc->empty_transfer_count > MAX_EMPTY_TRANSFERS) { | |
899 | /* | |
900 | * The FX2 gave up. End the acquisition, the frontend | |
901 | * will work out that the samplecount is short. | |
902 | */ | |
903 | devc->sent_samples = -2; | |
904 | free_transfer(transfer); | |
905 | } else { | |
906 | resubmit_transfer(transfer); | |
907 | } | |
908 | return; | |
909 | } else { | |
910 | devc->empty_transfer_count = 0; | |
911 | } | |
912 | ||
913 | new_samples = convert_sample_data(devc, devc->convbuffer, | |
914 | devc->convbuffer_size, transfer->buffer, transfer->actual_length); | |
915 | ||
916 | if (new_samples > 0) { | |
917 | if (devc->trigger_fired) { | |
918 | /* Send the incoming transfer to the session bus. */ | |
919 | packet.type = SR_DF_LOGIC; | |
920 | packet.payload = &logic; | |
921 | if (devc->limit_samples && | |
922 | new_samples > devc->limit_samples - devc->sent_samples) | |
923 | new_samples = devc->limit_samples - devc->sent_samples; | |
924 | logic.length = new_samples * 2; | |
925 | logic.unitsize = 2; | |
926 | logic.data = devc->convbuffer; | |
927 | sr_session_send(sdi, &packet); | |
928 | devc->sent_samples += new_samples; | |
929 | } else { | |
930 | trigger_offset = soft_trigger_logic_check(devc->stl, | |
931 | devc->convbuffer, new_samples * 2, &pre_trigger_samples); | |
932 | if (trigger_offset > -1) { | |
933 | devc->sent_samples += pre_trigger_samples; | |
934 | packet.type = SR_DF_LOGIC; | |
935 | packet.payload = &logic; | |
936 | num_samples = new_samples - trigger_offset; | |
937 | if (devc->limit_samples && | |
938 | num_samples > devc->limit_samples - devc->sent_samples) | |
939 | num_samples = devc->limit_samples - devc->sent_samples; | |
940 | logic.length = num_samples * 2; | |
941 | logic.unitsize = 2; | |
942 | logic.data = devc->convbuffer + trigger_offset * 2; | |
943 | sr_session_send(sdi, &packet); | |
944 | devc->sent_samples += num_samples; | |
945 | ||
946 | devc->trigger_fired = TRUE; | |
947 | } | |
948 | } | |
949 | ||
950 | if (devc->limit_samples && | |
951 | (uint64_t)devc->sent_samples >= devc->limit_samples) { | |
952 | devc->sent_samples = -2; | |
953 | free_transfer(transfer); | |
954 | return; | |
955 | } | |
956 | } | |
957 | ||
958 | resubmit_transfer(transfer); | |
959 | } |