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1 | /* | |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, | |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
7 | * | |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | /* | |
23 | * ASIX SIGMA/SIGMA2 logic analyzer driver | |
24 | */ | |
25 | ||
26 | #include <config.h> | |
27 | #include "protocol.h" | |
28 | ||
29 | /* | |
30 | * The ASIX Sigma supports arbitrary integer frequency divider in | |
31 | * the 50MHz mode. The divider is in range 1...256 , allowing for | |
32 | * very precise sampling rate selection. This driver supports only | |
33 | * a subset of the sampling rates. | |
34 | */ | |
35 | SR_PRIV const uint64_t samplerates[] = { | |
36 | SR_KHZ(200), /* div=250 */ | |
37 | SR_KHZ(250), /* div=200 */ | |
38 | SR_KHZ(500), /* div=100 */ | |
39 | SR_MHZ(1), /* div=50 */ | |
40 | SR_MHZ(5), /* div=10 */ | |
41 | SR_MHZ(10), /* div=5 */ | |
42 | SR_MHZ(25), /* div=2 */ | |
43 | SR_MHZ(50), /* div=1 */ | |
44 | SR_MHZ(100), /* Special FW needed */ | |
45 | SR_MHZ(200), /* Special FW needed */ | |
46 | }; | |
47 | ||
48 | SR_PRIV const size_t samplerates_count = ARRAY_SIZE(samplerates); | |
49 | ||
50 | static const char firmware_files[][24] = { | |
51 | /* 50 MHz, supports 8 bit fractions */ | |
52 | "asix-sigma-50.fw", | |
53 | /* 100 MHz */ | |
54 | "asix-sigma-100.fw", | |
55 | /* 200 MHz */ | |
56 | "asix-sigma-200.fw", | |
57 | /* Synchronous clock from pin */ | |
58 | "asix-sigma-50sync.fw", | |
59 | /* Frequency counter */ | |
60 | "asix-sigma-phasor.fw", | |
61 | }; | |
62 | ||
63 | static int sigma_read(void *buf, size_t size, struct dev_context *devc) | |
64 | { | |
65 | int ret; | |
66 | ||
67 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); | |
68 | if (ret < 0) { | |
69 | sr_err("ftdi_read_data failed: %s", | |
70 | ftdi_get_error_string(&devc->ftdic)); | |
71 | } | |
72 | ||
73 | return ret; | |
74 | } | |
75 | ||
76 | static int sigma_write(void *buf, size_t size, struct dev_context *devc) | |
77 | { | |
78 | int ret; | |
79 | ||
80 | ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); | |
81 | if (ret < 0) | |
82 | sr_err("ftdi_write_data failed: %s", | |
83 | ftdi_get_error_string(&devc->ftdic)); | |
84 | else if ((size_t) ret != size) | |
85 | sr_err("ftdi_write_data did not complete write."); | |
86 | ||
87 | return ret; | |
88 | } | |
89 | ||
90 | /* | |
91 | * NOTE: We chose the buffer size to be large enough to hold any write to the | |
92 | * device. We still print a message just in case. | |
93 | */ | |
94 | SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, | |
95 | struct dev_context *devc) | |
96 | { | |
97 | size_t i; | |
98 | uint8_t buf[80]; | |
99 | int idx = 0; | |
100 | ||
101 | if ((2 * len + 2) > sizeof(buf)) { | |
102 | sr_err("Attempted to write %zu bytes, but buffer is too small.", | |
103 | len); | |
104 | return SR_ERR_BUG; | |
105 | } | |
106 | ||
107 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
108 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
109 | ||
110 | for (i = 0; i < len; i++) { | |
111 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); | |
112 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
113 | } | |
114 | ||
115 | return sigma_write(buf, idx, devc); | |
116 | } | |
117 | ||
118 | SR_PRIV int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc) | |
119 | { | |
120 | return sigma_write_register(reg, &value, 1, devc); | |
121 | } | |
122 | ||
123 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, | |
124 | struct dev_context *devc) | |
125 | { | |
126 | uint8_t buf[3]; | |
127 | ||
128 | buf[0] = REG_ADDR_LOW | (reg & 0xf); | |
129 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
130 | buf[2] = REG_READ_ADDR; | |
131 | ||
132 | sigma_write(buf, sizeof(buf), devc); | |
133 | ||
134 | return sigma_read(data, len, devc); | |
135 | } | |
136 | ||
137 | static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc) | |
138 | { | |
139 | uint8_t value; | |
140 | ||
141 | if (1 != sigma_read_register(reg, &value, 1, devc)) { | |
142 | sr_err("sigma_get_register: 1 byte expected"); | |
143 | return 0; | |
144 | } | |
145 | ||
146 | return value; | |
147 | } | |
148 | ||
149 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, | |
150 | struct dev_context *devc) | |
151 | { | |
152 | uint8_t buf[] = { | |
153 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
154 | ||
155 | REG_READ_ADDR | NEXT_REG, | |
156 | REG_READ_ADDR | NEXT_REG, | |
157 | REG_READ_ADDR | NEXT_REG, | |
158 | REG_READ_ADDR | NEXT_REG, | |
159 | REG_READ_ADDR | NEXT_REG, | |
160 | REG_READ_ADDR | NEXT_REG, | |
161 | }; | |
162 | uint8_t result[6]; | |
163 | ||
164 | sigma_write(buf, sizeof(buf), devc); | |
165 | ||
166 | sigma_read(result, sizeof(result), devc); | |
167 | ||
168 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
169 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
170 | ||
171 | /* Not really sure why this must be done, but according to spec. */ | |
172 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
173 | *stoppos -= 64; | |
174 | ||
175 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
176 | *triggerpos -= 64; | |
177 | ||
178 | return 1; | |
179 | } | |
180 | ||
181 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, | |
182 | uint8_t *data, struct dev_context *devc) | |
183 | { | |
184 | size_t i; | |
185 | uint8_t buf[4096]; | |
186 | int idx; | |
187 | ||
188 | /* Send the startchunk. Index start with 1. */ | |
189 | idx = 0; | |
190 | buf[idx++] = startchunk >> 8; | |
191 | buf[idx++] = startchunk & 0xff; | |
192 | sigma_write_register(WRITE_MEMROW, buf, idx, devc); | |
193 | ||
194 | /* Read the DRAM. */ | |
195 | idx = 0; | |
196 | buf[idx++] = REG_DRAM_BLOCK; | |
197 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
198 | ||
199 | for (i = 0; i < numchunks; i++) { | |
200 | /* Alternate bit to copy from DRAM to cache. */ | |
201 | if (i != (numchunks - 1)) | |
202 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
203 | ||
204 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
205 | ||
206 | if (i != (numchunks - 1)) | |
207 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
208 | } | |
209 | ||
210 | sigma_write(buf, idx, devc); | |
211 | ||
212 | return sigma_read(data, numchunks * CHUNK_SIZE, devc); | |
213 | } | |
214 | ||
215 | /* Upload trigger look-up tables to Sigma. */ | |
216 | SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc) | |
217 | { | |
218 | int i; | |
219 | uint8_t tmp[2]; | |
220 | uint16_t bit; | |
221 | ||
222 | /* Transpose the table and send to Sigma. */ | |
223 | for (i = 0; i < 16; i++) { | |
224 | bit = 1 << i; | |
225 | ||
226 | tmp[0] = tmp[1] = 0; | |
227 | ||
228 | if (lut->m2d[0] & bit) | |
229 | tmp[0] |= 0x01; | |
230 | if (lut->m2d[1] & bit) | |
231 | tmp[0] |= 0x02; | |
232 | if (lut->m2d[2] & bit) | |
233 | tmp[0] |= 0x04; | |
234 | if (lut->m2d[3] & bit) | |
235 | tmp[0] |= 0x08; | |
236 | ||
237 | if (lut->m3 & bit) | |
238 | tmp[0] |= 0x10; | |
239 | if (lut->m3s & bit) | |
240 | tmp[0] |= 0x20; | |
241 | if (lut->m4 & bit) | |
242 | tmp[0] |= 0x40; | |
243 | ||
244 | if (lut->m0d[0] & bit) | |
245 | tmp[1] |= 0x01; | |
246 | if (lut->m0d[1] & bit) | |
247 | tmp[1] |= 0x02; | |
248 | if (lut->m0d[2] & bit) | |
249 | tmp[1] |= 0x04; | |
250 | if (lut->m0d[3] & bit) | |
251 | tmp[1] |= 0x08; | |
252 | ||
253 | if (lut->m1d[0] & bit) | |
254 | tmp[1] |= 0x10; | |
255 | if (lut->m1d[1] & bit) | |
256 | tmp[1] |= 0x20; | |
257 | if (lut->m1d[2] & bit) | |
258 | tmp[1] |= 0x40; | |
259 | if (lut->m1d[3] & bit) | |
260 | tmp[1] |= 0x80; | |
261 | ||
262 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), | |
263 | devc); | |
264 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); | |
265 | } | |
266 | ||
267 | /* Send the parameters */ | |
268 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
269 | sizeof(lut->params), devc); | |
270 | ||
271 | return SR_OK; | |
272 | } | |
273 | ||
274 | /* | |
275 | * Configure the FPGA for bitbang mode. | |
276 | * This sequence is documented in section 2. of the ASIX Sigma programming | |
277 | * manual. This sequence is necessary to configure the FPGA in the Sigma | |
278 | * into Bitbang mode, in which it can be programmed with the firmware. | |
279 | */ | |
280 | static int sigma_fpga_init_bitbang(struct dev_context *devc) | |
281 | { | |
282 | uint8_t suicide[] = { | |
283 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
284 | }; | |
285 | uint8_t init_array[] = { | |
286 | 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, | |
287 | 0x01, 0x01, | |
288 | }; | |
289 | int i, ret, timeout = (10 * 1000); | |
290 | uint8_t data; | |
291 | ||
292 | /* Section 2. part 1), do the FPGA suicide. */ | |
293 | sigma_write(suicide, sizeof(suicide), devc); | |
294 | sigma_write(suicide, sizeof(suicide), devc); | |
295 | sigma_write(suicide, sizeof(suicide), devc); | |
296 | sigma_write(suicide, sizeof(suicide), devc); | |
297 | ||
298 | /* Section 2. part 2), do pulse on D1. */ | |
299 | sigma_write(init_array, sizeof(init_array), devc); | |
300 | ftdi_usb_purge_buffers(&devc->ftdic); | |
301 | ||
302 | /* Wait until the FPGA asserts D6/INIT_B. */ | |
303 | for (i = 0; i < timeout; i++) { | |
304 | ret = sigma_read(&data, 1, devc); | |
305 | if (ret < 0) | |
306 | return ret; | |
307 | /* Test if pin D6 got asserted. */ | |
308 | if (data & (1 << 5)) | |
309 | return 0; | |
310 | /* The D6 was not asserted yet, wait a bit. */ | |
311 | g_usleep(10 * 1000); | |
312 | } | |
313 | ||
314 | return SR_ERR_TIMEOUT; | |
315 | } | |
316 | ||
317 | /* | |
318 | * Configure the FPGA for logic-analyzer mode. | |
319 | */ | |
320 | static int sigma_fpga_init_la(struct dev_context *devc) | |
321 | { | |
322 | /* Initialize the logic analyzer mode. */ | |
323 | uint8_t mode_regval = WMR_SDRAMINIT; | |
324 | uint8_t logic_mode_start[] = { | |
325 | REG_ADDR_LOW | (READ_ID & 0xf), | |
326 | REG_ADDR_HIGH | (READ_ID >> 4), | |
327 | REG_READ_ADDR, /* Read ID register. */ | |
328 | ||
329 | REG_ADDR_LOW | (WRITE_TEST & 0xf), | |
330 | REG_DATA_LOW | 0x5, | |
331 | REG_DATA_HIGH_WRITE | 0x5, | |
332 | REG_READ_ADDR, /* Read scratch register. */ | |
333 | ||
334 | REG_DATA_LOW | 0xa, | |
335 | REG_DATA_HIGH_WRITE | 0xa, | |
336 | REG_READ_ADDR, /* Read scratch register. */ | |
337 | ||
338 | REG_ADDR_LOW | (WRITE_MODE & 0xf), | |
339 | REG_DATA_LOW | (mode_regval & 0xf), | |
340 | REG_DATA_HIGH_WRITE | (mode_regval >> 4), | |
341 | }; | |
342 | ||
343 | uint8_t result[3]; | |
344 | int ret; | |
345 | ||
346 | /* Initialize the logic analyzer mode. */ | |
347 | sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); | |
348 | ||
349 | /* Expect a 3 byte reply since we issued three READ requests. */ | |
350 | ret = sigma_read(result, 3, devc); | |
351 | if (ret != 3) | |
352 | goto err; | |
353 | ||
354 | if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) | |
355 | goto err; | |
356 | ||
357 | return SR_OK; | |
358 | err: | |
359 | sr_err("Configuration failed. Invalid reply received."); | |
360 | return SR_ERR; | |
361 | } | |
362 | ||
363 | /* | |
364 | * Read the firmware from a file and transform it into a series of bitbang | |
365 | * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d | |
366 | * by the caller of this function. | |
367 | */ | |
368 | static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name, | |
369 | uint8_t **bb_cmd, gsize *bb_cmd_size) | |
370 | { | |
371 | size_t i, file_size, bb_size; | |
372 | char *firmware; | |
373 | uint8_t *bb_stream, *bbs; | |
374 | uint32_t imm; | |
375 | int bit, v; | |
376 | int ret = SR_OK; | |
377 | ||
378 | /* Retrieve the on-disk firmware file content. */ | |
379 | firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE, | |
380 | name, &file_size, 256 * 1024); | |
381 | if (!firmware) | |
382 | return SR_ERR; | |
383 | ||
384 | /* Unscramble the file content (XOR with "random" sequence). */ | |
385 | imm = 0x3f6df2ab; | |
386 | for (i = 0; i < file_size; i++) { | |
387 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
388 | firmware[i] ^= imm & 0xff; | |
389 | } | |
390 | ||
391 | /* | |
392 | * Generate a sequence of bitbang samples. With two samples per | |
393 | * FPGA configuration bit, providing the level for the DIN signal | |
394 | * as well as two edges for CCLK. See Xilinx UG332 for details | |
395 | * ("slave serial" mode). | |
396 | * | |
397 | * Note that CCLK is inverted in hardware. That's why the | |
398 | * respective bit is first set and then cleared in the bitbang | |
399 | * sample sets. So that the DIN level will be stable when the | |
400 | * data gets sampled at the rising CCLK edge, and the signals' | |
401 | * setup time constraint will be met. | |
402 | * | |
403 | * The caller will put the FPGA into download mode, will send | |
404 | * the bitbang samples, and release the allocated memory. | |
405 | */ | |
406 | bb_size = file_size * 8 * 2; | |
407 | bb_stream = (uint8_t *)g_try_malloc(bb_size); | |
408 | if (!bb_stream) { | |
409 | sr_err("%s: Failed to allocate bitbang stream", __func__); | |
410 | ret = SR_ERR_MALLOC; | |
411 | goto exit; | |
412 | } | |
413 | bbs = bb_stream; | |
414 | for (i = 0; i < file_size; i++) { | |
415 | for (bit = 7; bit >= 0; bit--) { | |
416 | v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00; | |
417 | *bbs++ = v | 0x01; | |
418 | *bbs++ = v; | |
419 | } | |
420 | } | |
421 | ||
422 | /* The transformation completed successfully, return the result. */ | |
423 | *bb_cmd = bb_stream; | |
424 | *bb_cmd_size = bb_size; | |
425 | ||
426 | exit: | |
427 | g_free(firmware); | |
428 | return ret; | |
429 | } | |
430 | ||
431 | static int upload_firmware(struct sr_context *ctx, | |
432 | int firmware_idx, struct dev_context *devc) | |
433 | { | |
434 | int ret; | |
435 | unsigned char *buf; | |
436 | unsigned char pins; | |
437 | size_t buf_size; | |
438 | const char *firmware; | |
439 | ||
440 | /* Avoid downloading the same firmware multiple times. */ | |
441 | firmware = firmware_files[firmware_idx]; | |
442 | if (devc->cur_firmware == firmware_idx) { | |
443 | sr_info("Not uploading firmware file '%s' again.", firmware); | |
444 | return SR_OK; | |
445 | } | |
446 | ||
447 | ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG); | |
448 | if (ret < 0) { | |
449 | sr_err("ftdi_set_bitmode failed: %s", | |
450 | ftdi_get_error_string(&devc->ftdic)); | |
451 | return SR_ERR; | |
452 | } | |
453 | ||
454 | /* Four times the speed of sigmalogan - Works well. */ | |
455 | ret = ftdi_set_baudrate(&devc->ftdic, 750 * 1000); | |
456 | if (ret < 0) { | |
457 | sr_err("ftdi_set_baudrate failed: %s", | |
458 | ftdi_get_error_string(&devc->ftdic)); | |
459 | return SR_ERR; | |
460 | } | |
461 | ||
462 | /* Initialize the FPGA for firmware upload. */ | |
463 | ret = sigma_fpga_init_bitbang(devc); | |
464 | if (ret) | |
465 | return ret; | |
466 | ||
467 | /* Prepare firmware. */ | |
468 | ret = sigma_fw_2_bitbang(ctx, firmware, &buf, &buf_size); | |
469 | if (ret != SR_OK) { | |
470 | sr_err("An error occurred while reading the firmware: %s", | |
471 | firmware); | |
472 | return ret; | |
473 | } | |
474 | ||
475 | /* Upload firmware. */ | |
476 | sr_info("Uploading firmware file '%s'.", firmware); | |
477 | sigma_write(buf, buf_size, devc); | |
478 | ||
479 | g_free(buf); | |
480 | ||
481 | ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET); | |
482 | if (ret < 0) { | |
483 | sr_err("ftdi_set_bitmode failed: %s", | |
484 | ftdi_get_error_string(&devc->ftdic)); | |
485 | return SR_ERR; | |
486 | } | |
487 | ||
488 | ftdi_usb_purge_buffers(&devc->ftdic); | |
489 | ||
490 | /* Discard garbage. */ | |
491 | while (sigma_read(&pins, 1, devc) == 1) | |
492 | ; | |
493 | ||
494 | /* Initialize the FPGA for logic-analyzer mode. */ | |
495 | ret = sigma_fpga_init_la(devc); | |
496 | if (ret != SR_OK) | |
497 | return ret; | |
498 | ||
499 | devc->cur_firmware = firmware_idx; | |
500 | ||
501 | sr_info("Firmware uploaded."); | |
502 | ||
503 | return SR_OK; | |
504 | } | |
505 | ||
506 | /* | |
507 | * Sigma doesn't support limiting the number of samples, so we have to | |
508 | * translate the number and the samplerate to an elapsed time. | |
509 | * | |
510 | * In addition we need to ensure that the last data cluster has passed | |
511 | * the hardware pipeline, and became available to the PC side. With RLE | |
512 | * compression up to 327ms could pass before another cluster accumulates | |
513 | * at 200kHz samplerate when input pins don't change. | |
514 | */ | |
515 | SR_PRIV uint64_t sigma_limit_samples_to_msec(const struct dev_context *devc, | |
516 | uint64_t limit_samples) | |
517 | { | |
518 | uint64_t limit_msec; | |
519 | uint64_t worst_cluster_time_ms; | |
520 | ||
521 | limit_msec = limit_samples * 1000 / devc->cur_samplerate; | |
522 | worst_cluster_time_ms = 65536 * 1000 / devc->cur_samplerate; | |
523 | /* | |
524 | * One cluster time is not enough to flush pipeline when sampling | |
525 | * grounded pins with 1 sample limit at 200kHz. Hence the 2* fix. | |
526 | */ | |
527 | return limit_msec + 2 * worst_cluster_time_ms; | |
528 | } | |
529 | ||
530 | SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) | |
531 | { | |
532 | struct dev_context *devc; | |
533 | struct drv_context *drvc; | |
534 | size_t i; | |
535 | int ret; | |
536 | int num_channels; | |
537 | ||
538 | devc = sdi->priv; | |
539 | drvc = sdi->driver->context; | |
540 | ret = SR_OK; | |
541 | ||
542 | /* Reject rates that are not in the list of supported rates. */ | |
543 | for (i = 0; i < samplerates_count; i++) { | |
544 | if (samplerates[i] == samplerate) | |
545 | break; | |
546 | } | |
547 | if (i >= samplerates_count || samplerates[i] == 0) | |
548 | return SR_ERR_SAMPLERATE; | |
549 | ||
550 | /* | |
551 | * Depending on the samplerates of 200/100/50- MHz, specific | |
552 | * firmware is required and higher rates might limit the set | |
553 | * of available channels. | |
554 | */ | |
555 | num_channels = devc->num_channels; | |
556 | if (samplerate <= SR_MHZ(50)) { | |
557 | ret = upload_firmware(drvc->sr_ctx, 0, devc); | |
558 | num_channels = 16; | |
559 | } else if (samplerate == SR_MHZ(100)) { | |
560 | ret = upload_firmware(drvc->sr_ctx, 1, devc); | |
561 | num_channels = 8; | |
562 | } else if (samplerate == SR_MHZ(200)) { | |
563 | ret = upload_firmware(drvc->sr_ctx, 2, devc); | |
564 | num_channels = 4; | |
565 | } | |
566 | ||
567 | /* | |
568 | * Derive the sample period from the sample rate as well as the | |
569 | * number of samples that the device will communicate within | |
570 | * an "event" (memory organization internal to the device). | |
571 | */ | |
572 | if (ret == SR_OK) { | |
573 | devc->num_channels = num_channels; | |
574 | devc->cur_samplerate = samplerate; | |
575 | devc->samples_per_event = 16 / devc->num_channels; | |
576 | devc->state.state = SIGMA_IDLE; | |
577 | } | |
578 | ||
579 | /* | |
580 | * Support for "limit_samples" is implemented by stopping | |
581 | * acquisition after a corresponding period of time. | |
582 | * Re-calculate that period of time, in case the limit is | |
583 | * set first and the samplerate gets (re-)configured later. | |
584 | */ | |
585 | if (ret == SR_OK && devc->limit_samples) { | |
586 | uint64_t msecs; | |
587 | msecs = sigma_limit_samples_to_msec(devc, devc->limit_samples); | |
588 | devc->limit_msec = msecs; | |
589 | } | |
590 | ||
591 | return ret; | |
592 | } | |
593 | ||
594 | /* | |
595 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
596 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
597 | * in addition to value/mask trigger for any number of channels. | |
598 | * | |
599 | * The Sigma supports complex triggers using boolean expressions, but this | |
600 | * has not been implemented yet. | |
601 | */ | |
602 | SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi) | |
603 | { | |
604 | struct dev_context *devc; | |
605 | struct sr_trigger *trigger; | |
606 | struct sr_trigger_stage *stage; | |
607 | struct sr_trigger_match *match; | |
608 | const GSList *l, *m; | |
609 | int channelbit, trigger_set; | |
610 | ||
611 | devc = sdi->priv; | |
612 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); | |
613 | if (!(trigger = sr_session_trigger_get(sdi->session))) | |
614 | return SR_OK; | |
615 | ||
616 | trigger_set = 0; | |
617 | for (l = trigger->stages; l; l = l->next) { | |
618 | stage = l->data; | |
619 | for (m = stage->matches; m; m = m->next) { | |
620 | match = m->data; | |
621 | if (!match->channel->enabled) | |
622 | /* Ignore disabled channels with a trigger. */ | |
623 | continue; | |
624 | channelbit = 1 << (match->channel->index); | |
625 | if (devc->cur_samplerate >= SR_MHZ(100)) { | |
626 | /* Fast trigger support. */ | |
627 | if (trigger_set) { | |
628 | sr_err("Only a single pin trigger is " | |
629 | "supported in 100 and 200MHz mode."); | |
630 | return SR_ERR; | |
631 | } | |
632 | if (match->match == SR_TRIGGER_FALLING) | |
633 | devc->trigger.fallingmask |= channelbit; | |
634 | else if (match->match == SR_TRIGGER_RISING) | |
635 | devc->trigger.risingmask |= channelbit; | |
636 | else { | |
637 | sr_err("Only rising/falling trigger is " | |
638 | "supported in 100 and 200MHz mode."); | |
639 | return SR_ERR; | |
640 | } | |
641 | ||
642 | trigger_set++; | |
643 | } else { | |
644 | /* Simple trigger support (event). */ | |
645 | if (match->match == SR_TRIGGER_ONE) { | |
646 | devc->trigger.simplevalue |= channelbit; | |
647 | devc->trigger.simplemask |= channelbit; | |
648 | } else if (match->match == SR_TRIGGER_ZERO) { | |
649 | devc->trigger.simplevalue &= ~channelbit; | |
650 | devc->trigger.simplemask |= channelbit; | |
651 | } else if (match->match == SR_TRIGGER_FALLING) { | |
652 | devc->trigger.fallingmask |= channelbit; | |
653 | trigger_set++; | |
654 | } else if (match->match == SR_TRIGGER_RISING) { | |
655 | devc->trigger.risingmask |= channelbit; | |
656 | trigger_set++; | |
657 | } | |
658 | ||
659 | /* | |
660 | * Actually, Sigma supports 2 rising/falling triggers, | |
661 | * but they are ORed and the current trigger syntax | |
662 | * does not permit ORed triggers. | |
663 | */ | |
664 | if (trigger_set > 1) { | |
665 | sr_err("Only 1 rising/falling trigger " | |
666 | "is supported."); | |
667 | return SR_ERR; | |
668 | } | |
669 | } | |
670 | } | |
671 | } | |
672 | ||
673 | return SR_OK; | |
674 | } | |
675 | ||
676 | /* Software trigger to determine exact trigger position. */ | |
677 | static int get_trigger_offset(uint8_t *samples, uint16_t last_sample, | |
678 | struct sigma_trigger *t) | |
679 | { | |
680 | int i; | |
681 | uint16_t sample = 0; | |
682 | ||
683 | for (i = 0; i < 8; i++) { | |
684 | if (i > 0) | |
685 | last_sample = sample; | |
686 | sample = samples[2 * i] | (samples[2 * i + 1] << 8); | |
687 | ||
688 | /* Simple triggers. */ | |
689 | if ((sample & t->simplemask) != t->simplevalue) | |
690 | continue; | |
691 | ||
692 | /* Rising edge. */ | |
693 | if (((last_sample & t->risingmask) != 0) || | |
694 | ((sample & t->risingmask) != t->risingmask)) | |
695 | continue; | |
696 | ||
697 | /* Falling edge. */ | |
698 | if ((last_sample & t->fallingmask) != t->fallingmask || | |
699 | (sample & t->fallingmask) != 0) | |
700 | continue; | |
701 | ||
702 | break; | |
703 | } | |
704 | ||
705 | /* If we did not match, return original trigger pos. */ | |
706 | return i & 0x7; | |
707 | } | |
708 | ||
709 | /* | |
710 | * Return the timestamp of "DRAM cluster". | |
711 | */ | |
712 | static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster) | |
713 | { | |
714 | return (cluster->timestamp_hi << 8) | cluster->timestamp_lo; | |
715 | } | |
716 | ||
717 | /* | |
718 | * Return one 16bit data entity of a DRAM cluster at the specified index. | |
719 | */ | |
720 | static uint16_t sigma_dram_cluster_data(struct sigma_dram_cluster *cl, int idx) | |
721 | { | |
722 | uint16_t sample; | |
723 | ||
724 | sample = 0; | |
725 | sample |= cl->samples[idx].sample_lo << 0; | |
726 | sample |= cl->samples[idx].sample_hi << 8; | |
727 | sample = (sample >> 8) | (sample << 8); | |
728 | return sample; | |
729 | } | |
730 | ||
731 | /* | |
732 | * Deinterlace sample data that was retrieved at 100MHz samplerate. | |
733 | * One 16bit item contains two samples of 8bits each. The bits of | |
734 | * multiple samples are interleaved. | |
735 | */ | |
736 | static uint16_t sigma_deinterlace_100mhz_data(uint16_t indata, int idx) | |
737 | { | |
738 | uint16_t outdata; | |
739 | ||
740 | indata >>= idx; | |
741 | outdata = 0; | |
742 | outdata |= (indata >> (0 * 2 - 0)) & (1 << 0); | |
743 | outdata |= (indata >> (1 * 2 - 1)) & (1 << 1); | |
744 | outdata |= (indata >> (2 * 2 - 2)) & (1 << 2); | |
745 | outdata |= (indata >> (3 * 2 - 3)) & (1 << 3); | |
746 | outdata |= (indata >> (4 * 2 - 4)) & (1 << 4); | |
747 | outdata |= (indata >> (5 * 2 - 5)) & (1 << 5); | |
748 | outdata |= (indata >> (6 * 2 - 6)) & (1 << 6); | |
749 | outdata |= (indata >> (7 * 2 - 7)) & (1 << 7); | |
750 | return outdata; | |
751 | } | |
752 | ||
753 | /* | |
754 | * Deinterlace sample data that was retrieved at 200MHz samplerate. | |
755 | * One 16bit item contains four samples of 4bits each. The bits of | |
756 | * multiple samples are interleaved. | |
757 | */ | |
758 | static uint16_t sigma_deinterlace_200mhz_data(uint16_t indata, int idx) | |
759 | { | |
760 | uint16_t outdata; | |
761 | ||
762 | indata >>= idx; | |
763 | outdata = 0; | |
764 | outdata |= (indata >> (0 * 4 - 0)) & (1 << 0); | |
765 | outdata |= (indata >> (1 * 4 - 1)) & (1 << 1); | |
766 | outdata |= (indata >> (2 * 4 - 2)) & (1 << 2); | |
767 | outdata |= (indata >> (3 * 4 - 3)) & (1 << 3); | |
768 | return outdata; | |
769 | } | |
770 | ||
771 | static void store_sr_sample(uint8_t *samples, int idx, uint16_t data) | |
772 | { | |
773 | samples[2 * idx + 0] = (data >> 0) & 0xff; | |
774 | samples[2 * idx + 1] = (data >> 8) & 0xff; | |
775 | } | |
776 | ||
777 | /* | |
778 | * Local wrapper around sr_session_send() calls. Make sure to not send | |
779 | * more samples to the session's datafeed than what was requested by a | |
780 | * previously configured (optional) sample count. | |
781 | */ | |
782 | static void sigma_session_send(struct sr_dev_inst *sdi, | |
783 | struct sr_datafeed_packet *packet) | |
784 | { | |
785 | struct dev_context *devc; | |
786 | struct sr_datafeed_logic *logic; | |
787 | uint64_t send_now; | |
788 | ||
789 | devc = sdi->priv; | |
790 | if (devc->limit_samples) { | |
791 | logic = (void *)packet->payload; | |
792 | send_now = logic->length / logic->unitsize; | |
793 | if (devc->sent_samples + send_now > devc->limit_samples) { | |
794 | send_now = devc->limit_samples - devc->sent_samples; | |
795 | logic->length = send_now * logic->unitsize; | |
796 | } | |
797 | if (!send_now) | |
798 | return; | |
799 | devc->sent_samples += send_now; | |
800 | } | |
801 | ||
802 | sr_session_send(sdi, packet); | |
803 | } | |
804 | ||
805 | /* | |
806 | * This size translates to: event count (1K events per cluster), times | |
807 | * the sample width (unitsize, 16bits per event), times the maximum | |
808 | * number of samples per event. | |
809 | */ | |
810 | #define SAMPLES_BUFFER_SIZE (1024 * 2 * 4) | |
811 | ||
812 | static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster, | |
813 | unsigned int events_in_cluster, | |
814 | unsigned int triggered, | |
815 | struct sr_dev_inst *sdi) | |
816 | { | |
817 | struct dev_context *devc = sdi->priv; | |
818 | struct sigma_state *ss = &devc->state; | |
819 | struct sr_datafeed_packet packet; | |
820 | struct sr_datafeed_logic logic; | |
821 | uint16_t tsdiff, ts, sample, item16; | |
822 | uint8_t samples[SAMPLES_BUFFER_SIZE]; | |
823 | uint8_t *send_ptr; | |
824 | size_t send_count, trig_count; | |
825 | unsigned int i; | |
826 | int j; | |
827 | ||
828 | ts = sigma_dram_cluster_ts(dram_cluster); | |
829 | tsdiff = ts - ss->lastts; | |
830 | ss->lastts = ts + EVENTS_PER_CLUSTER; | |
831 | ||
832 | packet.type = SR_DF_LOGIC; | |
833 | packet.payload = &logic; | |
834 | logic.unitsize = 2; | |
835 | logic.data = samples; | |
836 | ||
837 | /* | |
838 | * If this cluster is not adjacent to the previously received | |
839 | * cluster, then send the appropriate number of samples with the | |
840 | * previous values to the sigrok session. This "decodes RLE". | |
841 | */ | |
842 | for (ts = 0; ts < tsdiff; ts++) { | |
843 | i = ts % 1024; | |
844 | store_sr_sample(samples, i, ss->lastsample); | |
845 | ||
846 | /* | |
847 | * If we have 1024 samples ready or we're at the | |
848 | * end of submitting the padding samples, submit | |
849 | * the packet to Sigrok. Since constant data is | |
850 | * sent, duplication of data for rates above 50MHz | |
851 | * is simple. | |
852 | */ | |
853 | if ((i == 1023) || (ts == tsdiff - 1)) { | |
854 | logic.length = (i + 1) * logic.unitsize; | |
855 | for (j = 0; j < devc->samples_per_event; j++) | |
856 | sigma_session_send(sdi, &packet); | |
857 | } | |
858 | } | |
859 | ||
860 | /* | |
861 | * Parse the samples in current cluster and prepare them | |
862 | * to be submitted to Sigrok. Cope with memory layouts that | |
863 | * vary with the samplerate. | |
864 | */ | |
865 | send_ptr = &samples[0]; | |
866 | send_count = 0; | |
867 | sample = 0; | |
868 | for (i = 0; i < events_in_cluster; i++) { | |
869 | item16 = sigma_dram_cluster_data(dram_cluster, i); | |
870 | if (devc->cur_samplerate == SR_MHZ(200)) { | |
871 | sample = sigma_deinterlace_200mhz_data(item16, 0); | |
872 | store_sr_sample(samples, send_count++, sample); | |
873 | sample = sigma_deinterlace_200mhz_data(item16, 1); | |
874 | store_sr_sample(samples, send_count++, sample); | |
875 | sample = sigma_deinterlace_200mhz_data(item16, 2); | |
876 | store_sr_sample(samples, send_count++, sample); | |
877 | sample = sigma_deinterlace_200mhz_data(item16, 3); | |
878 | store_sr_sample(samples, send_count++, sample); | |
879 | } else if (devc->cur_samplerate == SR_MHZ(100)) { | |
880 | sample = sigma_deinterlace_100mhz_data(item16, 0); | |
881 | store_sr_sample(samples, send_count++, sample); | |
882 | sample = sigma_deinterlace_100mhz_data(item16, 1); | |
883 | store_sr_sample(samples, send_count++, sample); | |
884 | } else { | |
885 | sample = item16; | |
886 | store_sr_sample(samples, send_count++, sample); | |
887 | } | |
888 | } | |
889 | ||
890 | /* | |
891 | * If a trigger position applies, then provide the datafeed with | |
892 | * the first part of data up to that position, then send the | |
893 | * trigger marker. | |
894 | */ | |
895 | int trigger_offset = 0; | |
896 | if (triggered) { | |
897 | /* | |
898 | * Trigger is not always accurate to sample because of | |
899 | * pipeline delay. However, it always triggers before | |
900 | * the actual event. We therefore look at the next | |
901 | * samples to pinpoint the exact position of the trigger. | |
902 | */ | |
903 | trigger_offset = get_trigger_offset(samples, | |
904 | ss->lastsample, &devc->trigger); | |
905 | ||
906 | if (trigger_offset > 0) { | |
907 | trig_count = trigger_offset * devc->samples_per_event; | |
908 | packet.type = SR_DF_LOGIC; | |
909 | logic.length = trig_count * logic.unitsize; | |
910 | sigma_session_send(sdi, &packet); | |
911 | send_ptr += trig_count * logic.unitsize; | |
912 | send_count -= trig_count; | |
913 | } | |
914 | ||
915 | /* Only send trigger if explicitly enabled. */ | |
916 | if (devc->use_triggers) { | |
917 | packet.type = SR_DF_TRIGGER; | |
918 | sr_session_send(sdi, &packet); | |
919 | } | |
920 | } | |
921 | ||
922 | /* | |
923 | * Send the data after the trigger, or all of the received data | |
924 | * if no trigger position applies. | |
925 | */ | |
926 | if (send_count) { | |
927 | packet.type = SR_DF_LOGIC; | |
928 | logic.length = send_count * logic.unitsize; | |
929 | logic.data = send_ptr; | |
930 | sigma_session_send(sdi, &packet); | |
931 | } | |
932 | ||
933 | ss->lastsample = sample; | |
934 | } | |
935 | ||
936 | /* | |
937 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. | |
938 | * Each event is 20ns apart, and can contain multiple samples. | |
939 | * | |
940 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
941 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
942 | * For 50 MHz and below, events contain one sample for each channel, | |
943 | * spread 20 ns apart. | |
944 | */ | |
945 | static int decode_chunk_ts(struct sigma_dram_line *dram_line, | |
946 | uint16_t events_in_line, | |
947 | uint32_t trigger_event, | |
948 | struct sr_dev_inst *sdi) | |
949 | { | |
950 | struct sigma_dram_cluster *dram_cluster; | |
951 | struct dev_context *devc; | |
952 | unsigned int clusters_in_line; | |
953 | unsigned int events_in_cluster; | |
954 | unsigned int i; | |
955 | uint32_t trigger_cluster, triggered; | |
956 | ||
957 | devc = sdi->priv; | |
958 | clusters_in_line = events_in_line; | |
959 | clusters_in_line += EVENTS_PER_CLUSTER - 1; | |
960 | clusters_in_line /= EVENTS_PER_CLUSTER; | |
961 | trigger_cluster = ~0; | |
962 | triggered = 0; | |
963 | ||
964 | /* Check if trigger is in this chunk. */ | |
965 | if (trigger_event < (64 * 7)) { | |
966 | if (devc->cur_samplerate <= SR_MHZ(50)) { | |
967 | trigger_event -= MIN(EVENTS_PER_CLUSTER - 1, | |
968 | trigger_event); | |
969 | } | |
970 | ||
971 | /* Find in which cluster the trigger occurred. */ | |
972 | trigger_cluster = trigger_event / EVENTS_PER_CLUSTER; | |
973 | } | |
974 | ||
975 | /* For each full DRAM cluster. */ | |
976 | for (i = 0; i < clusters_in_line; i++) { | |
977 | dram_cluster = &dram_line->cluster[i]; | |
978 | ||
979 | /* The last cluster might not be full. */ | |
980 | if ((i == clusters_in_line - 1) && | |
981 | (events_in_line % EVENTS_PER_CLUSTER)) { | |
982 | events_in_cluster = events_in_line % EVENTS_PER_CLUSTER; | |
983 | } else { | |
984 | events_in_cluster = EVENTS_PER_CLUSTER; | |
985 | } | |
986 | ||
987 | triggered = (i == trigger_cluster); | |
988 | sigma_decode_dram_cluster(dram_cluster, events_in_cluster, | |
989 | triggered, sdi); | |
990 | } | |
991 | ||
992 | return SR_OK; | |
993 | } | |
994 | ||
995 | static int download_capture(struct sr_dev_inst *sdi) | |
996 | { | |
997 | const uint32_t chunks_per_read = 32; | |
998 | ||
999 | struct dev_context *devc; | |
1000 | struct sigma_dram_line *dram_line; | |
1001 | int bufsz; | |
1002 | uint32_t stoppos, triggerpos; | |
1003 | uint8_t modestatus; | |
1004 | uint32_t i; | |
1005 | uint32_t dl_lines_total, dl_lines_curr, dl_lines_done; | |
1006 | uint32_t dl_first_line, dl_line; | |
1007 | uint32_t dl_events_in_line; | |
1008 | uint32_t trg_line, trg_event; | |
1009 | ||
1010 | devc = sdi->priv; | |
1011 | dl_events_in_line = 64 * 7; | |
1012 | trg_line = ~0; | |
1013 | trg_event = ~0; | |
1014 | ||
1015 | dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line)); | |
1016 | if (!dram_line) | |
1017 | return FALSE; | |
1018 | ||
1019 | sr_info("Downloading sample data."); | |
1020 | devc->state.state = SIGMA_DOWNLOAD; | |
1021 | ||
1022 | /* | |
1023 | * Ask the hardware to stop data acquisition. Reception of the | |
1024 | * FORCESTOP request makes the hardware "disable RLE" (store | |
1025 | * clusters to DRAM regardless of whether pin state changes) and | |
1026 | * raise the POSTTRIGGERED flag. | |
1027 | */ | |
1028 | sigma_set_register(WRITE_MODE, WMR_FORCESTOP | WMR_SDRAMWRITEEN, devc); | |
1029 | do { | |
1030 | modestatus = sigma_get_register(READ_MODE, devc); | |
1031 | } while (!(modestatus & RMR_POSTTRIGGERED)); | |
1032 | ||
1033 | /* Set SDRAM Read Enable. */ | |
1034 | sigma_set_register(WRITE_MODE, WMR_SDRAMREADEN, devc); | |
1035 | ||
1036 | /* Get the current position. */ | |
1037 | sigma_read_pos(&stoppos, &triggerpos, devc); | |
1038 | ||
1039 | /* Check if trigger has fired. */ | |
1040 | modestatus = sigma_get_register(READ_MODE, devc); | |
1041 | if (modestatus & RMR_TRIGGERED) { | |
1042 | trg_line = triggerpos >> 9; | |
1043 | trg_event = triggerpos & 0x1ff; | |
1044 | } | |
1045 | ||
1046 | devc->sent_samples = 0; | |
1047 | ||
1048 | /* | |
1049 | * Determine how many "DRAM lines" of 1024 bytes each we need to | |
1050 | * retrieve from the Sigma hardware, so that we have a complete | |
1051 | * set of samples. Note that the last line need not contain 64 | |
1052 | * clusters, it might be partially filled only. | |
1053 | * | |
1054 | * When RMR_ROUND is set, the circular buffer in DRAM has wrapped | |
1055 | * around. Since the status of the very next line is uncertain in | |
1056 | * that case, we skip it and start reading from the next line. The | |
1057 | * circular buffer has 32K lines (0x8000). | |
1058 | */ | |
1059 | dl_lines_total = (stoppos >> 9) + 1; | |
1060 | if (modestatus & RMR_ROUND) { | |
1061 | dl_first_line = dl_lines_total + 1; | |
1062 | dl_lines_total = 0x8000 - 2; | |
1063 | } else { | |
1064 | dl_first_line = 0; | |
1065 | } | |
1066 | dl_lines_done = 0; | |
1067 | while (dl_lines_total > dl_lines_done) { | |
1068 | /* We can download only up-to 32 DRAM lines in one go! */ | |
1069 | dl_lines_curr = MIN(chunks_per_read, dl_lines_total - dl_lines_done); | |
1070 | ||
1071 | dl_line = dl_first_line + dl_lines_done; | |
1072 | dl_line %= 0x8000; | |
1073 | bufsz = sigma_read_dram(dl_line, dl_lines_curr, | |
1074 | (uint8_t *)dram_line, devc); | |
1075 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ | |
1076 | (void)bufsz; | |
1077 | ||
1078 | /* This is the first DRAM line, so find the initial timestamp. */ | |
1079 | if (dl_lines_done == 0) { | |
1080 | devc->state.lastts = | |
1081 | sigma_dram_cluster_ts(&dram_line[0].cluster[0]); | |
1082 | devc->state.lastsample = 0; | |
1083 | } | |
1084 | ||
1085 | for (i = 0; i < dl_lines_curr; i++) { | |
1086 | uint32_t trigger_event = ~0; | |
1087 | /* The last "DRAM line" can be only partially full. */ | |
1088 | if (dl_lines_done + i == dl_lines_total - 1) | |
1089 | dl_events_in_line = stoppos & 0x1ff; | |
1090 | ||
1091 | /* Test if the trigger happened on this line. */ | |
1092 | if (dl_lines_done + i == trg_line) | |
1093 | trigger_event = trg_event; | |
1094 | ||
1095 | decode_chunk_ts(dram_line + i, dl_events_in_line, | |
1096 | trigger_event, sdi); | |
1097 | } | |
1098 | ||
1099 | dl_lines_done += dl_lines_curr; | |
1100 | } | |
1101 | g_free(dram_line); | |
1102 | ||
1103 | std_session_send_df_end(sdi); | |
1104 | ||
1105 | devc->state.state = SIGMA_IDLE; | |
1106 | sr_dev_acquisition_stop(sdi); | |
1107 | ||
1108 | return TRUE; | |
1109 | } | |
1110 | ||
1111 | /* | |
1112 | * Periodically check the Sigma status when in CAPTURE mode. This routine | |
1113 | * checks whether the configured sample count or sample time have passed, | |
1114 | * and will stop acquisition and download the acquired samples. | |
1115 | */ | |
1116 | static int sigma_capture_mode(struct sr_dev_inst *sdi) | |
1117 | { | |
1118 | struct dev_context *devc; | |
1119 | uint64_t running_msec; | |
1120 | uint64_t current_time; | |
1121 | ||
1122 | devc = sdi->priv; | |
1123 | ||
1124 | /* | |
1125 | * Check if the selected sampling duration passed. Sample count | |
1126 | * limits are covered by this enforced timeout as well. | |
1127 | */ | |
1128 | current_time = g_get_monotonic_time(); | |
1129 | running_msec = (current_time - devc->start_time) / 1000; | |
1130 | if (running_msec >= devc->limit_msec) | |
1131 | return download_capture(sdi); | |
1132 | ||
1133 | return TRUE; | |
1134 | } | |
1135 | ||
1136 | SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data) | |
1137 | { | |
1138 | struct sr_dev_inst *sdi; | |
1139 | struct dev_context *devc; | |
1140 | ||
1141 | (void)fd; | |
1142 | (void)revents; | |
1143 | ||
1144 | sdi = cb_data; | |
1145 | devc = sdi->priv; | |
1146 | ||
1147 | if (devc->state.state == SIGMA_IDLE) | |
1148 | return TRUE; | |
1149 | ||
1150 | /* | |
1151 | * When the application has requested to stop the acquisition, | |
1152 | * then immediately start downloading sample data. Otherwise | |
1153 | * keep checking configured limits which will terminate the | |
1154 | * acquisition and initiate download. | |
1155 | */ | |
1156 | if (devc->state.state == SIGMA_STOPPING) | |
1157 | return download_capture(sdi); | |
1158 | if (devc->state.state == SIGMA_CAPTURE) | |
1159 | return sigma_capture_mode(sdi); | |
1160 | ||
1161 | return TRUE; | |
1162 | } | |
1163 | ||
1164 | /* Build a LUT entry used by the trigger functions. */ | |
1165 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
1166 | { | |
1167 | int i, j, k, bit; | |
1168 | ||
1169 | /* For each quad channel. */ | |
1170 | for (i = 0; i < 4; i++) { | |
1171 | entry[i] = 0xffff; | |
1172 | ||
1173 | /* For each bit in LUT. */ | |
1174 | for (j = 0; j < 16; j++) | |
1175 | ||
1176 | /* For each channel in quad. */ | |
1177 | for (k = 0; k < 4; k++) { | |
1178 | bit = 1 << (i * 4 + k); | |
1179 | ||
1180 | /* Set bit in entry */ | |
1181 | if ((mask & bit) && ((!(value & bit)) != | |
1182 | (!(j & (1 << k))))) | |
1183 | entry[i] &= ~(1 << j); | |
1184 | } | |
1185 | } | |
1186 | } | |
1187 | ||
1188 | /* Add a logical function to LUT mask. */ | |
1189 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1190 | int index, int neg, uint16_t *mask) | |
1191 | { | |
1192 | int i, j; | |
1193 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1194 | ||
1195 | memset(x, 0, 4 * sizeof(int)); | |
1196 | ||
1197 | /* Trigger detect condition. */ | |
1198 | switch (oper) { | |
1199 | case OP_LEVEL: | |
1200 | x[0][1] = 1; | |
1201 | x[1][1] = 1; | |
1202 | break; | |
1203 | case OP_NOT: | |
1204 | x[0][0] = 1; | |
1205 | x[1][0] = 1; | |
1206 | break; | |
1207 | case OP_RISE: | |
1208 | x[0][1] = 1; | |
1209 | break; | |
1210 | case OP_FALL: | |
1211 | x[1][0] = 1; | |
1212 | break; | |
1213 | case OP_RISEFALL: | |
1214 | x[0][1] = 1; | |
1215 | x[1][0] = 1; | |
1216 | break; | |
1217 | case OP_NOTRISE: | |
1218 | x[1][1] = 1; | |
1219 | x[0][0] = 1; | |
1220 | x[1][0] = 1; | |
1221 | break; | |
1222 | case OP_NOTFALL: | |
1223 | x[1][1] = 1; | |
1224 | x[0][0] = 1; | |
1225 | x[0][1] = 1; | |
1226 | break; | |
1227 | case OP_NOTRISEFALL: | |
1228 | x[1][1] = 1; | |
1229 | x[0][0] = 1; | |
1230 | break; | |
1231 | } | |
1232 | ||
1233 | /* Transpose if neg is set. */ | |
1234 | if (neg) { | |
1235 | for (i = 0; i < 2; i++) { | |
1236 | for (j = 0; j < 2; j++) { | |
1237 | tmp = x[i][j]; | |
1238 | x[i][j] = x[1 - i][1 - j]; | |
1239 | x[1 - i][1 - j] = tmp; | |
1240 | } | |
1241 | } | |
1242 | } | |
1243 | ||
1244 | /* Update mask with function. */ | |
1245 | for (i = 0; i < 16; i++) { | |
1246 | a = (i >> (2 * index + 0)) & 1; | |
1247 | b = (i >> (2 * index + 1)) & 1; | |
1248 | ||
1249 | aset = (*mask >> i) & 1; | |
1250 | bset = x[b][a]; | |
1251 | ||
1252 | rset = 0; | |
1253 | if (func == FUNC_AND || func == FUNC_NAND) | |
1254 | rset = aset & bset; | |
1255 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1256 | rset = aset | bset; | |
1257 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1258 | rset = aset ^ bset; | |
1259 | ||
1260 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1261 | rset = !rset; | |
1262 | ||
1263 | *mask &= ~(1 << i); | |
1264 | ||
1265 | if (rset) | |
1266 | *mask |= 1 << i; | |
1267 | } | |
1268 | } | |
1269 | ||
1270 | /* | |
1271 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1272 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1273 | * set at any time, but a full mask and value can be set (0/1). | |
1274 | */ | |
1275 | SR_PRIV int sigma_build_basic_trigger(struct triggerlut *lut, struct dev_context *devc) | |
1276 | { | |
1277 | int i,j; | |
1278 | uint16_t masks[2] = { 0, 0 }; | |
1279 | ||
1280 | memset(lut, 0, sizeof(struct triggerlut)); | |
1281 | ||
1282 | /* Constant for simple triggers. */ | |
1283 | lut->m4 = 0xa000; | |
1284 | ||
1285 | /* Value/mask trigger support. */ | |
1286 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, | |
1287 | lut->m2d); | |
1288 | ||
1289 | /* Rise/fall trigger support. */ | |
1290 | for (i = 0, j = 0; i < 16; i++) { | |
1291 | if (devc->trigger.risingmask & (1 << i) || | |
1292 | devc->trigger.fallingmask & (1 << i)) | |
1293 | masks[j++] = 1 << i; | |
1294 | } | |
1295 | ||
1296 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1297 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1298 | ||
1299 | /* Add glue logic */ | |
1300 | if (masks[0] || masks[1]) { | |
1301 | /* Transition trigger. */ | |
1302 | if (masks[0] & devc->trigger.risingmask) | |
1303 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); | |
1304 | if (masks[0] & devc->trigger.fallingmask) | |
1305 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); | |
1306 | if (masks[1] & devc->trigger.risingmask) | |
1307 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); | |
1308 | if (masks[1] & devc->trigger.fallingmask) | |
1309 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); | |
1310 | } else { | |
1311 | /* Only value/mask trigger. */ | |
1312 | lut->m3 = 0xffff; | |
1313 | } | |
1314 | ||
1315 | /* Triggertype: event. */ | |
1316 | lut->params.selres = 3; | |
1317 | ||
1318 | return SR_OK; | |
1319 | } |