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1/*
2 * This file is part of the sigrok project.
3 *
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22/*
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
24 */
25
26#include <glib.h>
27#include <glib/gstdio.h>
28#include <ftdi.h>
29#include <string.h>
30#include "libsigrok.h"
31#include "libsigrok-internal.h"
32#include "asix-sigma.h"
33
34#define USB_VENDOR 0xa600
35#define USB_PRODUCT 0xa000
36#define USB_DESCRIPTION "ASIX SIGMA"
37#define USB_VENDOR_NAME "ASIX"
38#define USB_MODEL_NAME "SIGMA"
39#define USB_MODEL_VERSION ""
40#define TRIGGER_TYPES "rf10"
41#define NUM_PROBES 16
42
43SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
44static struct sr_dev_driver *adi = &asix_sigma_driver_info;
45static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
46
47static const uint64_t supported_samplerates[] = {
48 SR_KHZ(200),
49 SR_KHZ(250),
50 SR_KHZ(500),
51 SR_MHZ(1),
52 SR_MHZ(5),
53 SR_MHZ(10),
54 SR_MHZ(25),
55 SR_MHZ(50),
56 SR_MHZ(100),
57 SR_MHZ(200),
58 0,
59};
60
61/*
62 * Probe numbers seem to go from 1-16, according to this image:
63 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
64 * (the cable has two additional GND pins, and a TI and TO pin)
65 */
66static const char *probe_names[NUM_PROBES + 1] = {
67 "1",
68 "2",
69 "3",
70 "4",
71 "5",
72 "6",
73 "7",
74 "8",
75 "9",
76 "10",
77 "11",
78 "12",
79 "13",
80 "14",
81 "15",
82 "16",
83 NULL,
84};
85
86static const struct sr_samplerates samplerates = {
87 0,
88 0,
89 0,
90 supported_samplerates,
91};
92
93static const int hwcaps[] = {
94 SR_HWCAP_LOGIC_ANALYZER,
95 SR_HWCAP_SAMPLERATE,
96 SR_HWCAP_CAPTURE_RATIO,
97
98 SR_HWCAP_LIMIT_MSEC,
99 0,
100};
101
102/* Force the FPGA to reboot. */
103static uint8_t suicide[] = {
104 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
105};
106
107/* Prepare to upload firmware (FPGA specific). */
108static uint8_t init[] = {
109 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
110};
111
112/* Initialize the logic analyzer mode. */
113static uint8_t logic_mode_start[] = {
114 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
115 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
116};
117
118static const char *firmware_files[] = {
119 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
120 "asix-sigma-100.fw", /* 100 MHz */
121 "asix-sigma-200.fw", /* 200 MHz */
122 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
123 "asix-sigma-phasor.fw", /* Frequency counter */
124};
125
126static int sigma_read(void *buf, size_t size, struct dev_context *devc)
127{
128 int ret;
129
130 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
131 if (ret < 0) {
132 sr_err("ftdi_read_data failed: %s",
133 ftdi_get_error_string(&devc->ftdic));
134 }
135
136 return ret;
137}
138
139static int sigma_write(void *buf, size_t size, struct dev_context *devc)
140{
141 int ret;
142
143 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
144 if (ret < 0) {
145 sr_err("ftdi_write_data failed: %s",
146 ftdi_get_error_string(&devc->ftdic));
147 } else if ((size_t) ret != size) {
148 sr_err("ftdi_write_data did not complete write.");
149 }
150
151 return ret;
152}
153
154static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
155 struct dev_context *devc)
156{
157 size_t i;
158 uint8_t buf[len + 2];
159 int idx = 0;
160
161 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
162 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
163
164 for (i = 0; i < len; ++i) {
165 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
166 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
167 }
168
169 return sigma_write(buf, idx, devc);
170}
171
172static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
173{
174 return sigma_write_register(reg, &value, 1, devc);
175}
176
177static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
178 struct dev_context *devc)
179{
180 uint8_t buf[3];
181
182 buf[0] = REG_ADDR_LOW | (reg & 0xf);
183 buf[1] = REG_ADDR_HIGH | (reg >> 4);
184 buf[2] = REG_READ_ADDR;
185
186 sigma_write(buf, sizeof(buf), devc);
187
188 return sigma_read(data, len, devc);
189}
190
191static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
192{
193 uint8_t value;
194
195 if (1 != sigma_read_register(reg, &value, 1, devc)) {
196 sr_err("sigma_get_register: 1 byte expected");
197 return 0;
198 }
199
200 return value;
201}
202
203static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
204 struct dev_context *devc)
205{
206 uint8_t buf[] = {
207 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
208
209 REG_READ_ADDR | NEXT_REG,
210 REG_READ_ADDR | NEXT_REG,
211 REG_READ_ADDR | NEXT_REG,
212 REG_READ_ADDR | NEXT_REG,
213 REG_READ_ADDR | NEXT_REG,
214 REG_READ_ADDR | NEXT_REG,
215 };
216 uint8_t result[6];
217
218 sigma_write(buf, sizeof(buf), devc);
219
220 sigma_read(result, sizeof(result), devc);
221
222 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
223 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
224
225 /* Not really sure why this must be done, but according to spec. */
226 if ((--*stoppos & 0x1ff) == 0x1ff)
227 stoppos -= 64;
228
229 if ((*--triggerpos & 0x1ff) == 0x1ff)
230 triggerpos -= 64;
231
232 return 1;
233}
234
235static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
236 uint8_t *data, struct dev_context *devc)
237{
238 size_t i;
239 uint8_t buf[4096];
240 int idx = 0;
241
242 /* Send the startchunk. Index start with 1. */
243 buf[0] = startchunk >> 8;
244 buf[1] = startchunk & 0xff;
245 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
246
247 /* Read the DRAM. */
248 buf[idx++] = REG_DRAM_BLOCK;
249 buf[idx++] = REG_DRAM_WAIT_ACK;
250
251 for (i = 0; i < numchunks; ++i) {
252 /* Alternate bit to copy from DRAM to cache. */
253 if (i != (numchunks - 1))
254 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
255
256 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
257
258 if (i != (numchunks - 1))
259 buf[idx++] = REG_DRAM_WAIT_ACK;
260 }
261
262 sigma_write(buf, idx, devc);
263
264 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
265}
266
267/* Upload trigger look-up tables to Sigma. */
268static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
269{
270 int i;
271 uint8_t tmp[2];
272 uint16_t bit;
273
274 /* Transpose the table and send to Sigma. */
275 for (i = 0; i < 16; ++i) {
276 bit = 1 << i;
277
278 tmp[0] = tmp[1] = 0;
279
280 if (lut->m2d[0] & bit)
281 tmp[0] |= 0x01;
282 if (lut->m2d[1] & bit)
283 tmp[0] |= 0x02;
284 if (lut->m2d[2] & bit)
285 tmp[0] |= 0x04;
286 if (lut->m2d[3] & bit)
287 tmp[0] |= 0x08;
288
289 if (lut->m3 & bit)
290 tmp[0] |= 0x10;
291 if (lut->m3s & bit)
292 tmp[0] |= 0x20;
293 if (lut->m4 & bit)
294 tmp[0] |= 0x40;
295
296 if (lut->m0d[0] & bit)
297 tmp[1] |= 0x01;
298 if (lut->m0d[1] & bit)
299 tmp[1] |= 0x02;
300 if (lut->m0d[2] & bit)
301 tmp[1] |= 0x04;
302 if (lut->m0d[3] & bit)
303 tmp[1] |= 0x08;
304
305 if (lut->m1d[0] & bit)
306 tmp[1] |= 0x10;
307 if (lut->m1d[1] & bit)
308 tmp[1] |= 0x20;
309 if (lut->m1d[2] & bit)
310 tmp[1] |= 0x40;
311 if (lut->m1d[3] & bit)
312 tmp[1] |= 0x80;
313
314 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
315 devc);
316 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
317 }
318
319 /* Send the parameters */
320 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
321 sizeof(lut->params), devc);
322
323 return SR_OK;
324}
325
326/* Generate the bitbang stream for programming the FPGA. */
327static int bin2bitbang(const char *filename,
328 unsigned char **buf, size_t *buf_size)
329{
330 FILE *f;
331 unsigned long file_size;
332 unsigned long offset = 0;
333 unsigned char *p;
334 uint8_t *firmware;
335 unsigned long fwsize = 0;
336 const int buffer_size = 65536;
337 size_t i;
338 int c, bit, v;
339 uint32_t imm = 0x3f6df2ab;
340
341 f = g_fopen(filename, "rb");
342 if (!f) {
343 sr_err("g_fopen(\"%s\", \"rb\")", filename);
344 return SR_ERR;
345 }
346
347 if (-1 == fseek(f, 0, SEEK_END)) {
348 sr_err("fseek on %s failed", filename);
349 fclose(f);
350 return SR_ERR;
351 }
352
353 file_size = ftell(f);
354
355 fseek(f, 0, SEEK_SET);
356
357 if (!(firmware = g_try_malloc(buffer_size))) {
358 sr_err("%s: firmware malloc failed", __func__);
359 fclose(f);
360 return SR_ERR_MALLOC;
361 }
362
363 while ((c = getc(f)) != EOF) {
364 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
365 firmware[fwsize++] = c ^ imm;
366 }
367 fclose(f);
368
369 if(fwsize != file_size) {
370 sr_err("%s: Error reading firmware", filename);
371 fclose(f);
372 g_free(firmware);
373 return SR_ERR;
374 }
375
376 *buf_size = fwsize * 2 * 8;
377
378 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
379 if (!p) {
380 sr_err("%s: buf/p malloc failed", __func__);
381 g_free(firmware);
382 return SR_ERR_MALLOC;
383 }
384
385 for (i = 0; i < fwsize; ++i) {
386 for (bit = 7; bit >= 0; --bit) {
387 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
388 p[offset++] = v | 0x01;
389 p[offset++] = v;
390 }
391 }
392
393 g_free(firmware);
394
395 if (offset != *buf_size) {
396 g_free(*buf);
397 sr_err("Error reading firmware %s "
398 "offset=%ld, file_size=%ld, buf_size=%zd.",
399 filename, offset, file_size, *buf_size);
400
401 return SR_ERR;
402 }
403
404 return SR_OK;
405}
406
407static int clear_instances(void)
408{
409 GSList *l;
410 struct sr_dev_inst *sdi;
411 struct drv_context *drvc;
412 struct dev_context *devc;
413
414 drvc = adi->priv;
415
416 /* Properly close all devices. */
417 for (l = drvc->instances; l; l = l->next) {
418 if (!(sdi = l->data)) {
419 /* Log error, but continue cleaning up the rest. */
420 sr_err("%s: sdi was NULL, continuing", __func__);
421 continue;
422 }
423 if (sdi->priv) {
424 devc = sdi->priv;
425 ftdi_free(&devc->ftdic);
426 }
427 sr_dev_inst_free(sdi);
428 }
429 g_slist_free(drvc->instances);
430 drvc->instances = NULL;
431
432 return SR_OK;
433}
434
435static int hw_init(void)
436{
437 struct drv_context *drvc;
438
439 if (!(drvc = g_try_malloc0(sizeof(struct drv_context)))) {
440 sr_err("Driver context malloc failed.");
441 return SR_ERR_MALLOC;
442 }
443 adi->priv = drvc;
444
445 return SR_OK;
446}
447
448static GSList *hw_scan(GSList *options)
449{
450 struct sr_dev_inst *sdi;
451 struct sr_probe *probe;
452 struct drv_context *drvc;
453 struct dev_context *devc;
454 GSList *devices;
455 struct ftdi_device_list *devlist;
456 char serial_txt[10];
457 uint32_t serial;
458 int ret, i;
459
460 (void)options;
461 drvc = adi->priv;
462 devices = NULL;
463 clear_instances();
464
465 if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
466 sr_err("%s: devc malloc failed", __func__);
467 return NULL;
468 }
469
470 ftdi_init(&devc->ftdic);
471
472 /* Look for SIGMAs. */
473
474 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
475 USB_VENDOR, USB_PRODUCT)) <= 0) {
476 if (ret < 0)
477 sr_err("ftdi_usb_find_all(): %d", ret);
478 goto free;
479 }
480
481 /* Make sure it's a version 1 or 2 SIGMA. */
482 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
483 serial_txt, sizeof(serial_txt));
484 sscanf(serial_txt, "%x", &serial);
485
486 if (serial < 0xa6010000 || serial > 0xa602ffff) {
487 sr_err("Only SIGMA and SIGMA2 are supported "
488 "in this version of libsigrok.");
489 goto free;
490 }
491
492 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
493
494 devc->cur_samplerate = 0;
495 devc->period_ps = 0;
496 devc->limit_msec = 0;
497 devc->cur_firmware = -1;
498 devc->num_probes = 0;
499 devc->samples_per_event = 0;
500 devc->capture_ratio = 50;
501 devc->use_triggers = 0;
502
503 /* Register SIGMA device. */
504 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
505 USB_MODEL_NAME, USB_MODEL_VERSION))) {
506 sr_err("%s: sdi was NULL", __func__);
507 goto free;
508 }
509 sdi->driver = adi;
510
511 for (i = 0; probe_names[i]; i++) {
512 if (!(probe = sr_probe_new(i, SR_PROBE_ANALOG, TRUE,
513 probe_names[i])))
514 return NULL;
515 sdi->probes = g_slist_append(sdi->probes, probe);
516 }
517
518 devices = g_slist_append(devices, sdi);
519 drvc->instances = g_slist_append(drvc->instances, sdi);
520 sdi->priv = devc;
521
522 /* We will open the device again when we need it. */
523 ftdi_list_free(&devlist);
524
525 return devices;
526
527free:
528 ftdi_deinit(&devc->ftdic);
529 g_free(devc);
530 return NULL;
531}
532
533static GSList *hw_dev_list(void)
534{
535 struct drv_context *drvc;
536
537 drvc = adi->priv;
538
539 return drvc->instances;
540}
541
542static int upload_firmware(int firmware_idx, struct dev_context *devc)
543{
544 int ret;
545 unsigned char *buf;
546 unsigned char pins;
547 size_t buf_size;
548 unsigned char result[32];
549 char firmware_path[128];
550
551 /* Make sure it's an ASIX SIGMA. */
552 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
553 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
554 sr_err("ftdi_usb_open failed: %s",
555 ftdi_get_error_string(&devc->ftdic));
556 return 0;
557 }
558
559 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
560 sr_err("ftdi_set_bitmode failed: %s",
561 ftdi_get_error_string(&devc->ftdic));
562 return 0;
563 }
564
565 /* Four times the speed of sigmalogan - Works well. */
566 if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) {
567 sr_err("ftdi_set_baudrate failed: %s",
568 ftdi_get_error_string(&devc->ftdic));
569 return 0;
570 }
571
572 /* Force the FPGA to reboot. */
573 sigma_write(suicide, sizeof(suicide), devc);
574 sigma_write(suicide, sizeof(suicide), devc);
575 sigma_write(suicide, sizeof(suicide), devc);
576 sigma_write(suicide, sizeof(suicide), devc);
577
578 /* Prepare to upload firmware (FPGA specific). */
579 sigma_write(init, sizeof(init), devc);
580
581 ftdi_usb_purge_buffers(&devc->ftdic);
582
583 /* Wait until the FPGA asserts INIT_B. */
584 while (1) {
585 ret = sigma_read(result, 1, devc);
586 if (result[0] & 0x20)
587 break;
588 }
589
590 /* Prepare firmware. */
591 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
592 firmware_files[firmware_idx]);
593
594 if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
595 sr_err("An error occured while reading the firmware: %s",
596 firmware_path);
597 return ret;
598 }
599
600 /* Upload firmare. */
601 sr_info("Uploading firmware file '%s'.", firmware_files[firmware_idx]);
602 sigma_write(buf, buf_size, devc);
603
604 g_free(buf);
605
606 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) {
607 sr_err("ftdi_set_bitmode failed: %s",
608 ftdi_get_error_string(&devc->ftdic));
609 return SR_ERR;
610 }
611
612 ftdi_usb_purge_buffers(&devc->ftdic);
613
614 /* Discard garbage. */
615 while (1 == sigma_read(&pins, 1, devc))
616 ;
617
618 /* Initialize the logic analyzer mode. */
619 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
620
621 /* Expect a 3 byte reply. */
622 ret = sigma_read(result, 3, devc);
623 if (ret != 3 ||
624 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
625 sr_err("Configuration failed. Invalid reply received.");
626 return SR_ERR;
627 }
628
629 devc->cur_firmware = firmware_idx;
630
631 sr_info("Firmware uploaded.");
632
633 return SR_OK;
634}
635
636static int hw_dev_open(struct sr_dev_inst *sdi)
637{
638 struct dev_context *devc;
639 int ret;
640
641 devc = sdi->priv;
642
643 /* Make sure it's an ASIX SIGMA. */
644 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
645 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
646
647 sr_err("ftdi_usb_open failed: %s",
648 ftdi_get_error_string(&devc->ftdic));
649
650 return 0;
651 }
652
653 sdi->status = SR_ST_ACTIVE;
654
655 return SR_OK;
656}
657
658static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
659{
660 int i, ret;
661 struct dev_context *devc = sdi->priv;
662
663 for (i = 0; supported_samplerates[i]; i++) {
664 if (supported_samplerates[i] == samplerate)
665 break;
666 }
667 if (supported_samplerates[i] == 0)
668 return SR_ERR_SAMPLERATE;
669
670 if (samplerate <= SR_MHZ(50)) {
671 ret = upload_firmware(0, devc);
672 devc->num_probes = 16;
673 }
674 if (samplerate == SR_MHZ(100)) {
675 ret = upload_firmware(1, devc);
676 devc->num_probes = 8;
677 }
678 else if (samplerate == SR_MHZ(200)) {
679 ret = upload_firmware(2, devc);
680 devc->num_probes = 4;
681 }
682
683 devc->cur_samplerate = samplerate;
684 devc->period_ps = 1000000000000 / samplerate;
685 devc->samples_per_event = 16 / devc->num_probes;
686 devc->state.state = SIGMA_IDLE;
687
688 return ret;
689}
690
691/*
692 * In 100 and 200 MHz mode, only a single pin rising/falling can be
693 * set as trigger. In other modes, two rising/falling triggers can be set,
694 * in addition to value/mask trigger for any number of probes.
695 *
696 * The Sigma supports complex triggers using boolean expressions, but this
697 * has not been implemented yet.
698 */
699static int configure_probes(const struct sr_dev_inst *sdi)
700{
701 struct dev_context *devc = sdi->priv;
702 const struct sr_probe *probe;
703 const GSList *l;
704 int trigger_set = 0;
705 int probebit;
706
707 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
708
709 for (l = sdi->probes; l; l = l->next) {
710 probe = (struct sr_probe *)l->data;
711 probebit = 1 << (probe->index);
712
713 if (!probe->enabled || !probe->trigger)
714 continue;
715
716 if (devc->cur_samplerate >= SR_MHZ(100)) {
717 /* Fast trigger support. */
718 if (trigger_set) {
719 sr_err("Only a single pin trigger in 100 and "
720 "200MHz mode is supported.");
721 return SR_ERR;
722 }
723 if (probe->trigger[0] == 'f')
724 devc->trigger.fallingmask |= probebit;
725 else if (probe->trigger[0] == 'r')
726 devc->trigger.risingmask |= probebit;
727 else {
728 sr_err("Only rising/falling trigger in 100 "
729 "and 200MHz mode is supported.");
730 return SR_ERR;
731 }
732
733 ++trigger_set;
734 } else {
735 /* Simple trigger support (event). */
736 if (probe->trigger[0] == '1') {
737 devc->trigger.simplevalue |= probebit;
738 devc->trigger.simplemask |= probebit;
739 }
740 else if (probe->trigger[0] == '0') {
741 devc->trigger.simplevalue &= ~probebit;
742 devc->trigger.simplemask |= probebit;
743 }
744 else if (probe->trigger[0] == 'f') {
745 devc->trigger.fallingmask |= probebit;
746 ++trigger_set;
747 }
748 else if (probe->trigger[0] == 'r') {
749 devc->trigger.risingmask |= probebit;
750 ++trigger_set;
751 }
752
753 /*
754 * Actually, Sigma supports 2 rising/falling triggers,
755 * but they are ORed and the current trigger syntax
756 * does not permit ORed triggers.
757 */
758 if (trigger_set > 1) {
759 sr_err("Only 1 rising/falling trigger "
760 "is supported.");
761 return SR_ERR;
762 }
763 }
764
765 if (trigger_set)
766 devc->use_triggers = 1;
767 }
768
769 return SR_OK;
770}
771
772static int hw_dev_close(struct sr_dev_inst *sdi)
773{
774 struct dev_context *devc;
775
776 if (!(devc = sdi->priv)) {
777 sr_err("%s: sdi->priv was NULL", __func__);
778 return SR_ERR_BUG;
779 }
780
781 /* TODO */
782 if (sdi->status == SR_ST_ACTIVE)
783 ftdi_usb_close(&devc->ftdic);
784
785 sdi->status = SR_ST_INACTIVE;
786
787 return SR_OK;
788}
789
790static int hw_cleanup(void)
791{
792 if (!adi->priv)
793 return SR_OK;
794
795 clear_instances();
796
797 return SR_OK;
798}
799
800static int hw_info_get(int info_id, const void **data,
801 const struct sr_dev_inst *sdi)
802{
803 struct dev_context *devc;
804
805 switch (info_id) {
806 case SR_DI_HWCAPS:
807 *data = hwcaps;
808 break;
809 case SR_DI_NUM_PROBES:
810 *data = GINT_TO_POINTER(NUM_PROBES);
811 break;
812 case SR_DI_PROBE_NAMES:
813 *data = probe_names;
814 break;
815 case SR_DI_SAMPLERATES:
816 *data = &samplerates;
817 break;
818 case SR_DI_TRIGGER_TYPES:
819 *data = (char *)TRIGGER_TYPES;
820 break;
821 case SR_DI_CUR_SAMPLERATE:
822 if (sdi) {
823 devc = sdi->priv;
824 *data = &devc->cur_samplerate;
825 } else
826 return SR_ERR;
827 break;
828 default:
829 return SR_ERR_ARG;
830 }
831
832 return SR_OK;
833}
834
835static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap,
836 const void *value)
837{
838 struct dev_context *devc;
839 int ret;
840
841 devc = sdi->priv;
842
843 if (hwcap == SR_HWCAP_SAMPLERATE) {
844 ret = set_samplerate(sdi, *(const uint64_t *)value);
845 } else if (hwcap == SR_HWCAP_LIMIT_MSEC) {
846 devc->limit_msec = *(const uint64_t *)value;
847 if (devc->limit_msec > 0)
848 ret = SR_OK;
849 else
850 ret = SR_ERR;
851 } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) {
852 devc->capture_ratio = *(const uint64_t *)value;
853 if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
854 ret = SR_ERR;
855 else
856 ret = SR_OK;
857 } else {
858 ret = SR_ERR;
859 }
860
861 return ret;
862}
863
864/* Software trigger to determine exact trigger position. */
865static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
866 struct sigma_trigger *t)
867{
868 int i;
869
870 for (i = 0; i < 8; ++i) {
871 if (i > 0)
872 last_sample = samples[i-1];
873
874 /* Simple triggers. */
875 if ((samples[i] & t->simplemask) != t->simplevalue)
876 continue;
877
878 /* Rising edge. */
879 if ((last_sample & t->risingmask) != 0 || (samples[i] &
880 t->risingmask) != t->risingmask)
881 continue;
882
883 /* Falling edge. */
884 if ((last_sample & t->fallingmask) != t->fallingmask ||
885 (samples[i] & t->fallingmask) != 0)
886 continue;
887
888 break;
889 }
890
891 /* If we did not match, return original trigger pos. */
892 return i & 0x7;
893}
894
895/*
896 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
897 * Each event is 20ns apart, and can contain multiple samples.
898 *
899 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
900 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
901 * For 50 MHz and below, events contain one sample for each channel,
902 * spread 20 ns apart.
903 */
904static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
905 uint16_t *lastsample, int triggerpos,
906 uint16_t limit_chunk, void *cb_data)
907{
908 struct sr_dev_inst *sdi = cb_data;
909 struct dev_context *devc = sdi->priv;
910 uint16_t tsdiff, ts;
911 uint16_t samples[65536 * devc->samples_per_event];
912 struct sr_datafeed_packet packet;
913 struct sr_datafeed_logic logic;
914 int i, j, k, l, numpad, tosend;
915 size_t n = 0, sent = 0;
916 int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event;
917 uint16_t *event;
918 uint16_t cur_sample;
919 int triggerts = -1;
920
921 /* Check if trigger is in this chunk. */
922 if (triggerpos != -1) {
923 if (devc->cur_samplerate <= SR_MHZ(50))
924 triggerpos -= EVENTS_PER_CLUSTER - 1;
925
926 if (triggerpos < 0)
927 triggerpos = 0;
928
929 /* Find in which cluster the trigger occured. */
930 triggerts = triggerpos / 7;
931 }
932
933 /* For each ts. */
934 for (i = 0; i < 64; ++i) {
935 ts = *(uint16_t *) &buf[i * 16];
936 tsdiff = ts - *lastts;
937 *lastts = ts;
938
939 /* Decode partial chunk. */
940 if (limit_chunk && ts > limit_chunk)
941 return SR_OK;
942
943 /* Pad last sample up to current point. */
944 numpad = tsdiff * devc->samples_per_event - clustersize;
945 if (numpad > 0) {
946 for (j = 0; j < numpad; ++j)
947 samples[j] = *lastsample;
948
949 n = numpad;
950 }
951
952 /* Send samples between previous and this timestamp to sigrok. */
953 sent = 0;
954 while (sent < n) {
955 tosend = MIN(2048, n - sent);
956
957 packet.type = SR_DF_LOGIC;
958 packet.payload = &logic;
959 logic.length = tosend * sizeof(uint16_t);
960 logic.unitsize = 2;
961 logic.data = samples + sent;
962 sr_session_send(devc->session_dev_id, &packet);
963
964 sent += tosend;
965 }
966 n = 0;
967
968 event = (uint16_t *) &buf[i * 16 + 2];
969 cur_sample = 0;
970
971 /* For each event in cluster. */
972 for (j = 0; j < 7; ++j) {
973
974 /* For each sample in event. */
975 for (k = 0; k < devc->samples_per_event; ++k) {
976 cur_sample = 0;
977
978 /* For each probe. */
979 for (l = 0; l < devc->num_probes; ++l)
980 cur_sample |= (!!(event[j] & (1 << (l *
981 devc->samples_per_event + k)))) << l;
982
983 samples[n++] = cur_sample;
984 }
985 }
986
987 /* Send data up to trigger point (if triggered). */
988 sent = 0;
989 if (i == triggerts) {
990 /*
991 * Trigger is not always accurate to sample because of
992 * pipeline delay. However, it always triggers before
993 * the actual event. We therefore look at the next
994 * samples to pinpoint the exact position of the trigger.
995 */
996 tosend = get_trigger_offset(samples, *lastsample,
997 &devc->trigger);
998
999 if (tosend > 0) {
1000 packet.type = SR_DF_LOGIC;
1001 packet.payload = &logic;
1002 logic.length = tosend * sizeof(uint16_t);
1003 logic.unitsize = 2;
1004 logic.data = samples;
1005 sr_session_send(devc->session_dev_id, &packet);
1006
1007 sent += tosend;
1008 }
1009
1010 /* Only send trigger if explicitly enabled. */
1011 if (devc->use_triggers) {
1012 packet.type = SR_DF_TRIGGER;
1013 sr_session_send(devc->session_dev_id, &packet);
1014 }
1015 }
1016
1017 /* Send rest of the chunk to sigrok. */
1018 tosend = n - sent;
1019
1020 if (tosend > 0) {
1021 packet.type = SR_DF_LOGIC;
1022 packet.payload = &logic;
1023 logic.length = tosend * sizeof(uint16_t);
1024 logic.unitsize = 2;
1025 logic.data = samples + sent;
1026 sr_session_send(devc->session_dev_id, &packet);
1027 }
1028
1029 *lastsample = samples[n - 1];
1030 }
1031
1032 return SR_OK;
1033}
1034
1035static int receive_data(int fd, int revents, void *cb_data)
1036{
1037 struct sr_dev_inst *sdi = cb_data;
1038 struct dev_context *devc = sdi->priv;
1039 struct sr_datafeed_packet packet;
1040 const int chunks_per_read = 32;
1041 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1042 int bufsz, numchunks, i, newchunks;
1043 uint64_t running_msec;
1044 struct timeval tv;
1045
1046 (void)fd;
1047 (void)revents;
1048
1049 /* Get the current position. */
1050 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1051
1052 numchunks = (devc->state.stoppos + 511) / 512;
1053
1054 if (devc->state.state == SIGMA_IDLE)
1055 return TRUE;
1056
1057 if (devc->state.state == SIGMA_CAPTURE) {
1058 /* Check if the timer has expired, or memory is full. */
1059 gettimeofday(&tv, 0);
1060 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1061 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1062
1063 if (running_msec < devc->limit_msec && numchunks < 32767)
1064 return TRUE; /* While capturing... */
1065 else
1066 hw_dev_acquisition_stop(sdi, sdi);
1067
1068 } else if (devc->state.state == SIGMA_DOWNLOAD) {
1069 if (devc->state.chunks_downloaded >= numchunks) {
1070 /* End of samples. */
1071 packet.type = SR_DF_END;
1072 sr_session_send(devc->session_dev_id, &packet);
1073
1074 devc->state.state = SIGMA_IDLE;
1075
1076 return TRUE;
1077 }
1078
1079 newchunks = MIN(chunks_per_read,
1080 numchunks - devc->state.chunks_downloaded);
1081
1082 sr_info("Downloading sample data: %.0f %%.",
1083 100.0 * devc->state.chunks_downloaded / numchunks);
1084
1085 bufsz = sigma_read_dram(devc->state.chunks_downloaded,
1086 newchunks, buf, devc);
1087 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1088 (void)bufsz;
1089
1090 /* Find first ts. */
1091 if (devc->state.chunks_downloaded == 0) {
1092 devc->state.lastts = *(uint16_t *) buf - 1;
1093 devc->state.lastsample = 0;
1094 }
1095
1096 /* Decode chunks and send them to sigrok. */
1097 for (i = 0; i < newchunks; ++i) {
1098 int limit_chunk = 0;
1099
1100 /* The last chunk may potentially be only in part. */
1101 if (devc->state.chunks_downloaded == numchunks - 1) {
1102 /* Find the last valid timestamp */
1103 limit_chunk = devc->state.stoppos % 512 + devc->state.lastts;
1104 }
1105
1106 if (devc->state.chunks_downloaded + i == devc->state.triggerchunk)
1107 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1108 &devc->state.lastts,
1109 &devc->state.lastsample,
1110 devc->state.triggerpos & 0x1ff,
1111 limit_chunk, sdi);
1112 else
1113 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1114 &devc->state.lastts,
1115 &devc->state.lastsample,
1116 -1, limit_chunk, sdi);
1117
1118 ++devc->state.chunks_downloaded;
1119 }
1120 }
1121
1122 return TRUE;
1123}
1124
1125/* Build a LUT entry used by the trigger functions. */
1126static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1127{
1128 int i, j, k, bit;
1129
1130 /* For each quad probe. */
1131 for (i = 0; i < 4; ++i) {
1132 entry[i] = 0xffff;
1133
1134 /* For each bit in LUT. */
1135 for (j = 0; j < 16; ++j)
1136
1137 /* For each probe in quad. */
1138 for (k = 0; k < 4; ++k) {
1139 bit = 1 << (i * 4 + k);
1140
1141 /* Set bit in entry */
1142 if ((mask & bit) &&
1143 ((!(value & bit)) !=
1144 (!(j & (1 << k)))))
1145 entry[i] &= ~(1 << j);
1146 }
1147 }
1148}
1149
1150/* Add a logical function to LUT mask. */
1151static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1152 int index, int neg, uint16_t *mask)
1153{
1154 int i, j;
1155 int x[2][2], tmp, a, b, aset, bset, rset;
1156
1157 memset(x, 0, 4 * sizeof(int));
1158
1159 /* Trigger detect condition. */
1160 switch (oper) {
1161 case OP_LEVEL:
1162 x[0][1] = 1;
1163 x[1][1] = 1;
1164 break;
1165 case OP_NOT:
1166 x[0][0] = 1;
1167 x[1][0] = 1;
1168 break;
1169 case OP_RISE:
1170 x[0][1] = 1;
1171 break;
1172 case OP_FALL:
1173 x[1][0] = 1;
1174 break;
1175 case OP_RISEFALL:
1176 x[0][1] = 1;
1177 x[1][0] = 1;
1178 break;
1179 case OP_NOTRISE:
1180 x[1][1] = 1;
1181 x[0][0] = 1;
1182 x[1][0] = 1;
1183 break;
1184 case OP_NOTFALL:
1185 x[1][1] = 1;
1186 x[0][0] = 1;
1187 x[0][1] = 1;
1188 break;
1189 case OP_NOTRISEFALL:
1190 x[1][1] = 1;
1191 x[0][0] = 1;
1192 break;
1193 }
1194
1195 /* Transpose if neg is set. */
1196 if (neg) {
1197 for (i = 0; i < 2; ++i) {
1198 for (j = 0; j < 2; ++j) {
1199 tmp = x[i][j];
1200 x[i][j] = x[1-i][1-j];
1201 x[1-i][1-j] = tmp;
1202 }
1203 }
1204 }
1205
1206 /* Update mask with function. */
1207 for (i = 0; i < 16; ++i) {
1208 a = (i >> (2 * index + 0)) & 1;
1209 b = (i >> (2 * index + 1)) & 1;
1210
1211 aset = (*mask >> i) & 1;
1212 bset = x[b][a];
1213
1214 if (func == FUNC_AND || func == FUNC_NAND)
1215 rset = aset & bset;
1216 else if (func == FUNC_OR || func == FUNC_NOR)
1217 rset = aset | bset;
1218 else if (func == FUNC_XOR || func == FUNC_NXOR)
1219 rset = aset ^ bset;
1220
1221 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1222 rset = !rset;
1223
1224 *mask &= ~(1 << i);
1225
1226 if (rset)
1227 *mask |= 1 << i;
1228 }
1229}
1230
1231/*
1232 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1233 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1234 * set at any time, but a full mask and value can be set (0/1).
1235 */
1236static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1237{
1238 int i,j;
1239 uint16_t masks[2] = { 0, 0 };
1240
1241 memset(lut, 0, sizeof(struct triggerlut));
1242
1243 /* Contant for simple triggers. */
1244 lut->m4 = 0xa000;
1245
1246 /* Value/mask trigger support. */
1247 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1248 lut->m2d);
1249
1250 /* Rise/fall trigger support. */
1251 for (i = 0, j = 0; i < 16; ++i) {
1252 if (devc->trigger.risingmask & (1 << i) ||
1253 devc->trigger.fallingmask & (1 << i))
1254 masks[j++] = 1 << i;
1255 }
1256
1257 build_lut_entry(masks[0], masks[0], lut->m0d);
1258 build_lut_entry(masks[1], masks[1], lut->m1d);
1259
1260 /* Add glue logic */
1261 if (masks[0] || masks[1]) {
1262 /* Transition trigger. */
1263 if (masks[0] & devc->trigger.risingmask)
1264 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1265 if (masks[0] & devc->trigger.fallingmask)
1266 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1267 if (masks[1] & devc->trigger.risingmask)
1268 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1269 if (masks[1] & devc->trigger.fallingmask)
1270 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1271 } else {
1272 /* Only value/mask trigger. */
1273 lut->m3 = 0xffff;
1274 }
1275
1276 /* Triggertype: event. */
1277 lut->params.selres = 3;
1278
1279 return SR_OK;
1280}
1281
1282static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
1283 void *cb_data)
1284{
1285 struct dev_context *devc;
1286 struct sr_datafeed_packet *packet;
1287 struct sr_datafeed_header *header;
1288 struct sr_datafeed_meta_logic meta;
1289 struct clockselect_50 clockselect;
1290 int frac, triggerpin, ret;
1291 uint8_t triggerselect;
1292 struct triggerinout triggerinout_conf;
1293 struct triggerlut lut;
1294
1295 devc = sdi->priv;
1296
1297 if (configure_probes(sdi) != SR_OK) {
1298 sr_err("Failed to configure probes.");
1299 return SR_ERR;
1300 }
1301
1302 /* If the samplerate has not been set, default to 200 kHz. */
1303 if (devc->cur_firmware == -1) {
1304 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1305 return ret;
1306 }
1307
1308 /* Enter trigger programming mode. */
1309 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1310
1311 /* 100 and 200 MHz mode. */
1312 if (devc->cur_samplerate >= SR_MHZ(100)) {
1313 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1314
1315 /* Find which pin to trigger on from mask. */
1316 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1317 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1318 (1 << triggerpin))
1319 break;
1320
1321 /* Set trigger pin and light LED on trigger. */
1322 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1323
1324 /* Default rising edge. */
1325 if (devc->trigger.fallingmask)
1326 triggerselect |= 1 << 3;
1327
1328 /* All other modes. */
1329 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1330 build_basic_trigger(&lut, devc);
1331
1332 sigma_write_trigger_lut(&lut, devc);
1333
1334 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1335 }
1336
1337 /* Setup trigger in and out pins to default values. */
1338 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1339 triggerinout_conf.trgout_bytrigger = 1;
1340 triggerinout_conf.trgout_enable = 1;
1341
1342 sigma_write_register(WRITE_TRIGGER_OPTION,
1343 (uint8_t *) &triggerinout_conf,
1344 sizeof(struct triggerinout), devc);
1345
1346 /* Go back to normal mode. */
1347 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1348
1349 /* Set clock select register. */
1350 if (devc->cur_samplerate == SR_MHZ(200))
1351 /* Enable 4 probes. */
1352 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1353 else if (devc->cur_samplerate == SR_MHZ(100))
1354 /* Enable 8 probes. */
1355 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1356 else {
1357 /*
1358 * 50 MHz mode (or fraction thereof). Any fraction down to
1359 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1360 */
1361 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1362
1363 clockselect.async = 0;
1364 clockselect.fraction = frac;
1365 clockselect.disabled_probes = 0;
1366
1367 sigma_write_register(WRITE_CLOCK_SELECT,
1368 (uint8_t *) &clockselect,
1369 sizeof(clockselect), devc);
1370 }
1371
1372 /* Setup maximum post trigger time. */
1373 sigma_set_register(WRITE_POST_TRIGGER,
1374 (devc->capture_ratio * 255) / 100, devc);
1375
1376 /* Start acqusition. */
1377 gettimeofday(&devc->start_tv, 0);
1378 sigma_set_register(WRITE_MODE, 0x0d, devc);
1379
1380 devc->session_dev_id = cb_data;
1381
1382 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1383 sr_err("%s: packet malloc failed.", __func__);
1384 return SR_ERR_MALLOC;
1385 }
1386
1387 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1388 sr_err("%s: header malloc failed.", __func__);
1389 return SR_ERR_MALLOC;
1390 }
1391
1392 /* Send header packet to the session bus. */
1393 packet->type = SR_DF_HEADER;
1394 packet->payload = header;
1395 header->feed_version = 1;
1396 gettimeofday(&header->starttime, NULL);
1397 sr_session_send(devc->session_dev_id, packet);
1398
1399 /* Send metadata about the SR_DF_LOGIC packets to come. */
1400 packet->type = SR_DF_META_LOGIC;
1401 packet->payload = &meta;
1402 meta.samplerate = devc->cur_samplerate;
1403 meta.num_probes = devc->num_probes;
1404 sr_session_send(devc->session_dev_id, packet);
1405
1406 /* Add capture source. */
1407 sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
1408
1409 g_free(header);
1410 g_free(packet);
1411
1412 devc->state.state = SIGMA_CAPTURE;
1413
1414 return SR_OK;
1415}
1416
1417static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1418{
1419 struct dev_context *devc;
1420 uint8_t modestatus;
1421
1422 /* Avoid compiler warnings. */
1423 (void)cb_data;
1424
1425 sr_source_remove(0);
1426
1427 if (!(devc = sdi->priv)) {
1428 sr_err("%s: sdi->priv was NULL", __func__);
1429 return SR_ERR_BUG;
1430 }
1431
1432 /* Stop acquisition. */
1433 sigma_set_register(WRITE_MODE, 0x11, devc);
1434
1435 /* Set SDRAM Read Enable. */
1436 sigma_set_register(WRITE_MODE, 0x02, devc);
1437
1438 /* Get the current position. */
1439 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1440
1441 /* Check if trigger has fired. */
1442 modestatus = sigma_get_register(READ_MODE, devc);
1443 if (modestatus & 0x20)
1444 devc->state.triggerchunk = devc->state.triggerpos / 512;
1445 else
1446 devc->state.triggerchunk = -1;
1447
1448 devc->state.chunks_downloaded = 0;
1449
1450 devc->state.state = SIGMA_DOWNLOAD;
1451
1452 return SR_OK;
1453}
1454
1455SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1456 .name = "asix-sigma",
1457 .longname = "ASIX SIGMA/SIGMA2",
1458 .api_version = 1,
1459 .init = hw_init,
1460 .cleanup = hw_cleanup,
1461 .scan = hw_scan,
1462 .dev_list = hw_dev_list,
1463 .dev_clear = clear_instances,
1464 .dev_open = hw_dev_open,
1465 .dev_close = hw_dev_close,
1466 .info_get = hw_info_get,
1467 .dev_config_set = hw_dev_config_set,
1468 .dev_acquisition_start = hw_dev_acquisition_start,
1469 .dev_acquisition_stop = hw_dev_acquisition_stop,
1470 .priv = NULL,
1471};
Hardware access and backend lib