]> sigrok.org Git - libsigrok.git/blame_incremental - hardware/asix-sigma/asix-sigma.c
projects / libsigrok.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
Add sr_dev_open()/sr_dev_close()
[libsigrok.git] / hardware / asix-sigma / asix-sigma.c
... / ...
CommitLineData
1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22/*
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
24 */
25
26#include <glib.h>
27#include <glib/gstdio.h>
28#include <ftdi.h>
29#include <string.h>
30#include "libsigrok.h"
31#include "libsigrok-internal.h"
32#include "asix-sigma.h"
33
34#define USB_VENDOR 0xa600
35#define USB_PRODUCT 0xa000
36#define USB_DESCRIPTION "ASIX SIGMA"
37#define USB_VENDOR_NAME "ASIX"
38#define USB_MODEL_NAME "SIGMA"
39#define USB_MODEL_VERSION ""
40#define TRIGGER_TYPE "rf10"
41#define NUM_PROBES 16
42
43SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
44static struct sr_dev_driver *di = &asix_sigma_driver_info;
45static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
46
47static const uint64_t samplerates[] = {
48 SR_KHZ(200),
49 SR_KHZ(250),
50 SR_KHZ(500),
51 SR_MHZ(1),
52 SR_MHZ(5),
53 SR_MHZ(10),
54 SR_MHZ(25),
55 SR_MHZ(50),
56 SR_MHZ(100),
57 SR_MHZ(200),
58};
59
60/*
61 * Probe numbers seem to go from 1-16, according to this image:
62 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
63 * (the cable has two additional GND pins, and a TI and TO pin)
64 */
65static const char *probe_names[NUM_PROBES + 1] = {
66 "1", "2", "3", "4", "5", "6", "7", "8",
67 "9", "10", "11", "12", "13", "14", "15", "16",
68 NULL,
69};
70
71static const int32_t hwcaps[] = {
72 SR_CONF_LOGIC_ANALYZER,
73 SR_CONF_SAMPLERATE,
74 SR_CONF_CAPTURE_RATIO,
75 SR_CONF_LIMIT_MSEC,
76};
77
78/* Force the FPGA to reboot. */
79static uint8_t suicide[] = {
80 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
81};
82
83/* Prepare to upload firmware (FPGA specific). */
84static uint8_t init[] = {
85 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
86};
87
88/* Initialize the logic analyzer mode. */
89static uint8_t logic_mode_start[] = {
90 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
91 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
92};
93
94static const char *firmware_files[] = {
95 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
96 "asix-sigma-100.fw", /* 100 MHz */
97 "asix-sigma-200.fw", /* 200 MHz */
98 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
99 "asix-sigma-phasor.fw", /* Frequency counter */
100};
101
102static int sigma_read(void *buf, size_t size, struct dev_context *devc)
103{
104 int ret;
105
106 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
107 if (ret < 0) {
108 sr_err("ftdi_read_data failed: %s",
109 ftdi_get_error_string(&devc->ftdic));
110 }
111
112 return ret;
113}
114
115static int sigma_write(void *buf, size_t size, struct dev_context *devc)
116{
117 int ret;
118
119 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
120 if (ret < 0) {
121 sr_err("ftdi_write_data failed: %s",
122 ftdi_get_error_string(&devc->ftdic));
123 } else if ((size_t) ret != size) {
124 sr_err("ftdi_write_data did not complete write.");
125 }
126
127 return ret;
128}
129
130static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
131 struct dev_context *devc)
132{
133 size_t i;
134 uint8_t buf[len + 2];
135 int idx = 0;
136
137 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
138 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
139
140 for (i = 0; i < len; ++i) {
141 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
142 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
143 }
144
145 return sigma_write(buf, idx, devc);
146}
147
148static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
149{
150 return sigma_write_register(reg, &value, 1, devc);
151}
152
153static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
154 struct dev_context *devc)
155{
156 uint8_t buf[3];
157
158 buf[0] = REG_ADDR_LOW | (reg & 0xf);
159 buf[1] = REG_ADDR_HIGH | (reg >> 4);
160 buf[2] = REG_READ_ADDR;
161
162 sigma_write(buf, sizeof(buf), devc);
163
164 return sigma_read(data, len, devc);
165}
166
167static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
168{
169 uint8_t value;
170
171 if (1 != sigma_read_register(reg, &value, 1, devc)) {
172 sr_err("sigma_get_register: 1 byte expected");
173 return 0;
174 }
175
176 return value;
177}
178
179static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
180 struct dev_context *devc)
181{
182 uint8_t buf[] = {
183 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
184
185 REG_READ_ADDR | NEXT_REG,
186 REG_READ_ADDR | NEXT_REG,
187 REG_READ_ADDR | NEXT_REG,
188 REG_READ_ADDR | NEXT_REG,
189 REG_READ_ADDR | NEXT_REG,
190 REG_READ_ADDR | NEXT_REG,
191 };
192 uint8_t result[6];
193
194 sigma_write(buf, sizeof(buf), devc);
195
196 sigma_read(result, sizeof(result), devc);
197
198 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
199 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
200
201 /* Not really sure why this must be done, but according to spec. */
202 if ((--*stoppos & 0x1ff) == 0x1ff)
203 stoppos -= 64;
204
205 if ((*--triggerpos & 0x1ff) == 0x1ff)
206 triggerpos -= 64;
207
208 return 1;
209}
210
211static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
212 uint8_t *data, struct dev_context *devc)
213{
214 size_t i;
215 uint8_t buf[4096];
216 int idx = 0;
217
218 /* Send the startchunk. Index start with 1. */
219 buf[0] = startchunk >> 8;
220 buf[1] = startchunk & 0xff;
221 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
222
223 /* Read the DRAM. */
224 buf[idx++] = REG_DRAM_BLOCK;
225 buf[idx++] = REG_DRAM_WAIT_ACK;
226
227 for (i = 0; i < numchunks; ++i) {
228 /* Alternate bit to copy from DRAM to cache. */
229 if (i != (numchunks - 1))
230 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
231
232 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
233
234 if (i != (numchunks - 1))
235 buf[idx++] = REG_DRAM_WAIT_ACK;
236 }
237
238 sigma_write(buf, idx, devc);
239
240 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
241}
242
243/* Upload trigger look-up tables to Sigma. */
244static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
245{
246 int i;
247 uint8_t tmp[2];
248 uint16_t bit;
249
250 /* Transpose the table and send to Sigma. */
251 for (i = 0; i < 16; ++i) {
252 bit = 1 << i;
253
254 tmp[0] = tmp[1] = 0;
255
256 if (lut->m2d[0] & bit)
257 tmp[0] |= 0x01;
258 if (lut->m2d[1] & bit)
259 tmp[0] |= 0x02;
260 if (lut->m2d[2] & bit)
261 tmp[0] |= 0x04;
262 if (lut->m2d[3] & bit)
263 tmp[0] |= 0x08;
264
265 if (lut->m3 & bit)
266 tmp[0] |= 0x10;
267 if (lut->m3s & bit)
268 tmp[0] |= 0x20;
269 if (lut->m4 & bit)
270 tmp[0] |= 0x40;
271
272 if (lut->m0d[0] & bit)
273 tmp[1] |= 0x01;
274 if (lut->m0d[1] & bit)
275 tmp[1] |= 0x02;
276 if (lut->m0d[2] & bit)
277 tmp[1] |= 0x04;
278 if (lut->m0d[3] & bit)
279 tmp[1] |= 0x08;
280
281 if (lut->m1d[0] & bit)
282 tmp[1] |= 0x10;
283 if (lut->m1d[1] & bit)
284 tmp[1] |= 0x20;
285 if (lut->m1d[2] & bit)
286 tmp[1] |= 0x40;
287 if (lut->m1d[3] & bit)
288 tmp[1] |= 0x80;
289
290 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
291 devc);
292 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
293 }
294
295 /* Send the parameters */
296 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
297 sizeof(lut->params), devc);
298
299 return SR_OK;
300}
301
302/* Generate the bitbang stream for programming the FPGA. */
303static int bin2bitbang(const char *filename,
304 unsigned char **buf, size_t *buf_size)
305{
306 FILE *f;
307 unsigned long file_size;
308 unsigned long offset = 0;
309 unsigned char *p;
310 uint8_t *firmware;
311 unsigned long fwsize = 0;
312 const int buffer_size = 65536;
313 size_t i;
314 int c, bit, v;
315 uint32_t imm = 0x3f6df2ab;
316
317 f = g_fopen(filename, "rb");
318 if (!f) {
319 sr_err("g_fopen(\"%s\", \"rb\")", filename);
320 return SR_ERR;
321 }
322
323 if (-1 == fseek(f, 0, SEEK_END)) {
324 sr_err("fseek on %s failed", filename);
325 fclose(f);
326 return SR_ERR;
327 }
328
329 file_size = ftell(f);
330
331 fseek(f, 0, SEEK_SET);
332
333 if (!(firmware = g_try_malloc(buffer_size))) {
334 sr_err("%s: firmware malloc failed", __func__);
335 fclose(f);
336 return SR_ERR_MALLOC;
337 }
338
339 while ((c = getc(f)) != EOF) {
340 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
341 firmware[fwsize++] = c ^ imm;
342 }
343 fclose(f);
344
345 if(fwsize != file_size) {
346 sr_err("%s: Error reading firmware", filename);
347 fclose(f);
348 g_free(firmware);
349 return SR_ERR;
350 }
351
352 *buf_size = fwsize * 2 * 8;
353
354 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
355 if (!p) {
356 sr_err("%s: buf/p malloc failed", __func__);
357 g_free(firmware);
358 return SR_ERR_MALLOC;
359 }
360
361 for (i = 0; i < fwsize; ++i) {
362 for (bit = 7; bit >= 0; --bit) {
363 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
364 p[offset++] = v | 0x01;
365 p[offset++] = v;
366 }
367 }
368
369 g_free(firmware);
370
371 if (offset != *buf_size) {
372 g_free(*buf);
373 sr_err("Error reading firmware %s "
374 "offset=%ld, file_size=%ld, buf_size=%zd.",
375 filename, offset, file_size, *buf_size);
376
377 return SR_ERR;
378 }
379
380 return SR_OK;
381}
382
383static int clear_instances(void)
384{
385 GSList *l;
386 struct sr_dev_inst *sdi;
387 struct drv_context *drvc;
388 struct dev_context *devc;
389
390 drvc = di->priv;
391
392 /* Properly close all devices. */
393 for (l = drvc->instances; l; l = l->next) {
394 if (!(sdi = l->data)) {
395 /* Log error, but continue cleaning up the rest. */
396 sr_err("%s: sdi was NULL, continuing", __func__);
397 continue;
398 }
399 if (sdi->priv) {
400 devc = sdi->priv;
401 ftdi_deinit(&devc->ftdic);
402 }
403 sr_dev_inst_free(sdi);
404 }
405 g_slist_free(drvc->instances);
406 drvc->instances = NULL;
407
408 return SR_OK;
409}
410
411static int hw_init(struct sr_context *sr_ctx)
412{
413 return std_hw_init(sr_ctx, di, DRIVER_LOG_DOMAIN);
414}
415
416static GSList *hw_scan(GSList *options)
417{
418 struct sr_dev_inst *sdi;
419 struct sr_probe *probe;
420 struct drv_context *drvc;
421 struct dev_context *devc;
422 GSList *devices;
423 struct ftdi_device_list *devlist;
424 char serial_txt[10];
425 uint32_t serial;
426 int ret, i;
427
428 (void)options;
429
430 drvc = di->priv;
431
432 devices = NULL;
433
434 clear_instances();
435
436 if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
437 sr_err("%s: devc malloc failed", __func__);
438 return NULL;
439 }
440
441 ftdi_init(&devc->ftdic);
442
443 /* Look for SIGMAs. */
444
445 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
446 USB_VENDOR, USB_PRODUCT)) <= 0) {
447 if (ret < 0)
448 sr_err("ftdi_usb_find_all(): %d", ret);
449 goto free;
450 }
451
452 /* Make sure it's a version 1 or 2 SIGMA. */
453 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
454 serial_txt, sizeof(serial_txt));
455 sscanf(serial_txt, "%x", &serial);
456
457 if (serial < 0xa6010000 || serial > 0xa602ffff) {
458 sr_err("Only SIGMA and SIGMA2 are supported "
459 "in this version of libsigrok.");
460 goto free;
461 }
462
463 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
464
465 devc->cur_samplerate = 0;
466 devc->period_ps = 0;
467 devc->limit_msec = 0;
468 devc->cur_firmware = -1;
469 devc->num_probes = 0;
470 devc->samples_per_event = 0;
471 devc->capture_ratio = 50;
472 devc->use_triggers = 0;
473
474 /* Register SIGMA device. */
475 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
476 USB_MODEL_NAME, USB_MODEL_VERSION))) {
477 sr_err("%s: sdi was NULL", __func__);
478 goto free;
479 }
480 sdi->driver = di;
481
482 for (i = 0; probe_names[i]; i++) {
483 if (!(probe = sr_probe_new(i, SR_PROBE_LOGIC, TRUE,
484 probe_names[i])))
485 return NULL;
486 sdi->probes = g_slist_append(sdi->probes, probe);
487 }
488
489 devices = g_slist_append(devices, sdi);
490 drvc->instances = g_slist_append(drvc->instances, sdi);
491 sdi->priv = devc;
492
493 /* We will open the device again when we need it. */
494 ftdi_list_free(&devlist);
495
496 return devices;
497
498free:
499 ftdi_deinit(&devc->ftdic);
500 g_free(devc);
501 return NULL;
502}
503
504static GSList *hw_dev_list(void)
505{
506 return ((struct drv_context *)(di->priv))->instances;
507}
508
509static int upload_firmware(int firmware_idx, struct dev_context *devc)
510{
511 int ret;
512 unsigned char *buf;
513 unsigned char pins;
514 size_t buf_size;
515 unsigned char result[32];
516 char firmware_path[128];
517
518 /* Make sure it's an ASIX SIGMA. */
519 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
520 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
521 sr_err("ftdi_usb_open failed: %s",
522 ftdi_get_error_string(&devc->ftdic));
523 return 0;
524 }
525
526 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
527 sr_err("ftdi_set_bitmode failed: %s",
528 ftdi_get_error_string(&devc->ftdic));
529 return 0;
530 }
531
532 /* Four times the speed of sigmalogan - Works well. */
533 if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) {
534 sr_err("ftdi_set_baudrate failed: %s",
535 ftdi_get_error_string(&devc->ftdic));
536 return 0;
537 }
538
539 /* Force the FPGA to reboot. */
540 sigma_write(suicide, sizeof(suicide), devc);
541 sigma_write(suicide, sizeof(suicide), devc);
542 sigma_write(suicide, sizeof(suicide), devc);
543 sigma_write(suicide, sizeof(suicide), devc);
544
545 /* Prepare to upload firmware (FPGA specific). */
546 sigma_write(init, sizeof(init), devc);
547
548 ftdi_usb_purge_buffers(&devc->ftdic);
549
550 /* Wait until the FPGA asserts INIT_B. */
551 while (1) {
552 ret = sigma_read(result, 1, devc);
553 if (result[0] & 0x20)
554 break;
555 }
556
557 /* Prepare firmware. */
558 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
559 firmware_files[firmware_idx]);
560
561 if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
562 sr_err("An error occured while reading the firmware: %s",
563 firmware_path);
564 return ret;
565 }
566
567 /* Upload firmare. */
568 sr_info("Uploading firmware file '%s'.", firmware_files[firmware_idx]);
569 sigma_write(buf, buf_size, devc);
570
571 g_free(buf);
572
573 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) {
574 sr_err("ftdi_set_bitmode failed: %s",
575 ftdi_get_error_string(&devc->ftdic));
576 return SR_ERR;
577 }
578
579 ftdi_usb_purge_buffers(&devc->ftdic);
580
581 /* Discard garbage. */
582 while (1 == sigma_read(&pins, 1, devc))
583 ;
584
585 /* Initialize the logic analyzer mode. */
586 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
587
588 /* Expect a 3 byte reply. */
589 ret = sigma_read(result, 3, devc);
590 if (ret != 3 ||
591 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
592 sr_err("Configuration failed. Invalid reply received.");
593 return SR_ERR;
594 }
595
596 devc->cur_firmware = firmware_idx;
597
598 sr_info("Firmware uploaded.");
599
600 return SR_OK;
601}
602
603static int hw_dev_open(struct sr_dev_inst *sdi)
604{
605 struct dev_context *devc;
606 int ret;
607
608 devc = sdi->priv;
609
610 /* Make sure it's an ASIX SIGMA. */
611 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
612 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
613
614 sr_err("ftdi_usb_open failed: %s",
615 ftdi_get_error_string(&devc->ftdic));
616
617 return 0;
618 }
619
620 sdi->status = SR_ST_ACTIVE;
621
622 return SR_OK;
623}
624
625static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
626{
627 struct dev_context *devc;
628 unsigned int i;
629 int ret;
630
631 devc = sdi->priv;
632 ret = SR_OK;
633
634 for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
635 if (samplerates[i] == samplerate)
636 break;
637 }
638 if (samplerates[i] == 0)
639 return SR_ERR_SAMPLERATE;
640
641 if (samplerate <= SR_MHZ(50)) {
642 ret = upload_firmware(0, devc);
643 devc->num_probes = 16;
644 }
645 if (samplerate == SR_MHZ(100)) {
646 ret = upload_firmware(1, devc);
647 devc->num_probes = 8;
648 }
649 else if (samplerate == SR_MHZ(200)) {
650 ret = upload_firmware(2, devc);
651 devc->num_probes = 4;
652 }
653
654 devc->cur_samplerate = samplerate;
655 devc->period_ps = 1000000000000ULL / samplerate;
656 devc->samples_per_event = 16 / devc->num_probes;
657 devc->state.state = SIGMA_IDLE;
658
659 return ret;
660}
661
662/*
663 * In 100 and 200 MHz mode, only a single pin rising/falling can be
664 * set as trigger. In other modes, two rising/falling triggers can be set,
665 * in addition to value/mask trigger for any number of probes.
666 *
667 * The Sigma supports complex triggers using boolean expressions, but this
668 * has not been implemented yet.
669 */
670static int configure_probes(const struct sr_dev_inst *sdi)
671{
672 struct dev_context *devc = sdi->priv;
673 const struct sr_probe *probe;
674 const GSList *l;
675 int trigger_set = 0;
676 int probebit;
677
678 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
679
680 for (l = sdi->probes; l; l = l->next) {
681 probe = (struct sr_probe *)l->data;
682 probebit = 1 << (probe->index);
683
684 if (!probe->enabled || !probe->trigger)
685 continue;
686
687 if (devc->cur_samplerate >= SR_MHZ(100)) {
688 /* Fast trigger support. */
689 if (trigger_set) {
690 sr_err("Only a single pin trigger in 100 and "
691 "200MHz mode is supported.");
692 return SR_ERR;
693 }
694 if (probe->trigger[0] == 'f')
695 devc->trigger.fallingmask |= probebit;
696 else if (probe->trigger[0] == 'r')
697 devc->trigger.risingmask |= probebit;
698 else {
699 sr_err("Only rising/falling trigger in 100 "
700 "and 200MHz mode is supported.");
701 return SR_ERR;
702 }
703
704 ++trigger_set;
705 } else {
706 /* Simple trigger support (event). */
707 if (probe->trigger[0] == '1') {
708 devc->trigger.simplevalue |= probebit;
709 devc->trigger.simplemask |= probebit;
710 }
711 else if (probe->trigger[0] == '0') {
712 devc->trigger.simplevalue &= ~probebit;
713 devc->trigger.simplemask |= probebit;
714 }
715 else if (probe->trigger[0] == 'f') {
716 devc->trigger.fallingmask |= probebit;
717 ++trigger_set;
718 }
719 else if (probe->trigger[0] == 'r') {
720 devc->trigger.risingmask |= probebit;
721 ++trigger_set;
722 }
723
724 /*
725 * Actually, Sigma supports 2 rising/falling triggers,
726 * but they are ORed and the current trigger syntax
727 * does not permit ORed triggers.
728 */
729 if (trigger_set > 1) {
730 sr_err("Only 1 rising/falling trigger "
731 "is supported.");
732 return SR_ERR;
733 }
734 }
735
736 if (trigger_set)
737 devc->use_triggers = 1;
738 }
739
740 return SR_OK;
741}
742
743static int hw_dev_close(struct sr_dev_inst *sdi)
744{
745 struct dev_context *devc;
746
747 devc = sdi->priv;
748
749 /* TODO */
750 if (sdi->status == SR_ST_ACTIVE)
751 ftdi_usb_close(&devc->ftdic);
752
753 sdi->status = SR_ST_INACTIVE;
754
755 return SR_OK;
756}
757
758static int hw_cleanup(void)
759{
760 if (!di->priv)
761 return SR_OK;
762
763 clear_instances();
764
765 return SR_OK;
766}
767
768static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi)
769{
770 struct dev_context *devc;
771
772 switch (id) {
773 case SR_CONF_SAMPLERATE:
774 if (sdi) {
775 devc = sdi->priv;
776 *data = g_variant_new_uint64(devc->cur_samplerate);
777 } else
778 return SR_ERR;
779 break;
780 default:
781 return SR_ERR_NA;
782 }
783
784 return SR_OK;
785}
786
787static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi)
788{
789 struct dev_context *devc;
790 int ret;
791
792 devc = sdi->priv;
793
794 if (id == SR_CONF_SAMPLERATE) {
795 ret = set_samplerate(sdi, g_variant_get_uint64(data));
796 } else if (id == SR_CONF_LIMIT_MSEC) {
797 devc->limit_msec = g_variant_get_uint64(data);
798 if (devc->limit_msec > 0)
799 ret = SR_OK;
800 else
801 ret = SR_ERR;
802 } else if (id == SR_CONF_CAPTURE_RATIO) {
803 devc->capture_ratio = g_variant_get_uint64(data);
804 if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
805 ret = SR_ERR;
806 else
807 ret = SR_OK;
808 } else {
809 ret = SR_ERR_NA;
810 }
811
812 return ret;
813}
814
815static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi)
816{
817 GVariant *gvar;
818 GVariantBuilder gvb;
819
820 (void)sdi;
821
822 switch (key) {
823 case SR_CONF_DEVICE_OPTIONS:
824 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
825 hwcaps, ARRAY_SIZE(hwcaps), sizeof(int32_t));
826 break;
827 case SR_CONF_SAMPLERATE:
828 g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
829 gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
830 ARRAY_SIZE(samplerates), sizeof(uint64_t));
831 g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
832 *data = g_variant_builder_end(&gvb);
833 break;
834 case SR_CONF_TRIGGER_TYPE:
835 *data = g_variant_new_string(TRIGGER_TYPE);
836 break;
837 default:
838 return SR_ERR_NA;
839 }
840
841 return SR_OK;
842}
843
844/* Software trigger to determine exact trigger position. */
845static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
846 struct sigma_trigger *t)
847{
848 int i;
849
850 for (i = 0; i < 8; ++i) {
851 if (i > 0)
852 last_sample = samples[i-1];
853
854 /* Simple triggers. */
855 if ((samples[i] & t->simplemask) != t->simplevalue)
856 continue;
857
858 /* Rising edge. */
859 if ((last_sample & t->risingmask) != 0 || (samples[i] &
860 t->risingmask) != t->risingmask)
861 continue;
862
863 /* Falling edge. */
864 if ((last_sample & t->fallingmask) != t->fallingmask ||
865 (samples[i] & t->fallingmask) != 0)
866 continue;
867
868 break;
869 }
870
871 /* If we did not match, return original trigger pos. */
872 return i & 0x7;
873}
874
875/*
876 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
877 * Each event is 20ns apart, and can contain multiple samples.
878 *
879 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
880 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
881 * For 50 MHz and below, events contain one sample for each channel,
882 * spread 20 ns apart.
883 */
884static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
885 uint16_t *lastsample, int triggerpos,
886 uint16_t limit_chunk, void *cb_data)
887{
888 struct sr_dev_inst *sdi = cb_data;
889 struct dev_context *devc = sdi->priv;
890 uint16_t tsdiff, ts;
891 uint16_t samples[65536 * devc->samples_per_event];
892 struct sr_datafeed_packet packet;
893 struct sr_datafeed_logic logic;
894 int i, j, k, l, numpad, tosend;
895 size_t n = 0, sent = 0;
896 int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event;
897 uint16_t *event;
898 uint16_t cur_sample;
899 int triggerts = -1;
900
901 /* Check if trigger is in this chunk. */
902 if (triggerpos != -1) {
903 if (devc->cur_samplerate <= SR_MHZ(50))
904 triggerpos -= EVENTS_PER_CLUSTER - 1;
905
906 if (triggerpos < 0)
907 triggerpos = 0;
908
909 /* Find in which cluster the trigger occured. */
910 triggerts = triggerpos / 7;
911 }
912
913 /* For each ts. */
914 for (i = 0; i < 64; ++i) {
915 ts = *(uint16_t *) &buf[i * 16];
916 tsdiff = ts - *lastts;
917 *lastts = ts;
918
919 /* Decode partial chunk. */
920 if (limit_chunk && ts > limit_chunk)
921 return SR_OK;
922
923 /* Pad last sample up to current point. */
924 numpad = tsdiff * devc->samples_per_event - clustersize;
925 if (numpad > 0) {
926 for (j = 0; j < numpad; ++j)
927 samples[j] = *lastsample;
928
929 n = numpad;
930 }
931
932 /* Send samples between previous and this timestamp to sigrok. */
933 sent = 0;
934 while (sent < n) {
935 tosend = MIN(2048, n - sent);
936
937 packet.type = SR_DF_LOGIC;
938 packet.payload = &logic;
939 logic.length = tosend * sizeof(uint16_t);
940 logic.unitsize = 2;
941 logic.data = samples + sent;
942 sr_session_send(devc->cb_data, &packet);
943
944 sent += tosend;
945 }
946 n = 0;
947
948 event = (uint16_t *) &buf[i * 16 + 2];
949 cur_sample = 0;
950
951 /* For each event in cluster. */
952 for (j = 0; j < 7; ++j) {
953
954 /* For each sample in event. */
955 for (k = 0; k < devc->samples_per_event; ++k) {
956 cur_sample = 0;
957
958 /* For each probe. */
959 for (l = 0; l < devc->num_probes; ++l)
960 cur_sample |= (!!(event[j] & (1 << (l *
961 devc->samples_per_event + k)))) << l;
962
963 samples[n++] = cur_sample;
964 }
965 }
966
967 /* Send data up to trigger point (if triggered). */
968 sent = 0;
969 if (i == triggerts) {
970 /*
971 * Trigger is not always accurate to sample because of
972 * pipeline delay. However, it always triggers before
973 * the actual event. We therefore look at the next
974 * samples to pinpoint the exact position of the trigger.
975 */
976 tosend = get_trigger_offset(samples, *lastsample,
977 &devc->trigger);
978
979 if (tosend > 0) {
980 packet.type = SR_DF_LOGIC;
981 packet.payload = &logic;
982 logic.length = tosend * sizeof(uint16_t);
983 logic.unitsize = 2;
984 logic.data = samples;
985 sr_session_send(devc->cb_data, &packet);
986
987 sent += tosend;
988 }
989
990 /* Only send trigger if explicitly enabled. */
991 if (devc->use_triggers) {
992 packet.type = SR_DF_TRIGGER;
993 sr_session_send(devc->cb_data, &packet);
994 }
995 }
996
997 /* Send rest of the chunk to sigrok. */
998 tosend = n - sent;
999
1000 if (tosend > 0) {
1001 packet.type = SR_DF_LOGIC;
1002 packet.payload = &logic;
1003 logic.length = tosend * sizeof(uint16_t);
1004 logic.unitsize = 2;
1005 logic.data = samples + sent;
1006 sr_session_send(devc->cb_data, &packet);
1007 }
1008
1009 *lastsample = samples[n - 1];
1010 }
1011
1012 return SR_OK;
1013}
1014
1015static int receive_data(int fd, int revents, void *cb_data)
1016{
1017 struct sr_dev_inst *sdi = cb_data;
1018 struct dev_context *devc = sdi->priv;
1019 struct sr_datafeed_packet packet;
1020 const int chunks_per_read = 32;
1021 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1022 int bufsz, numchunks, i, newchunks;
1023 uint64_t running_msec;
1024 struct timeval tv;
1025
1026 (void)fd;
1027 (void)revents;
1028
1029 /* Get the current position. */
1030 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1031
1032 numchunks = (devc->state.stoppos + 511) / 512;
1033
1034 if (devc->state.state == SIGMA_IDLE)
1035 return TRUE;
1036
1037 if (devc->state.state == SIGMA_CAPTURE) {
1038 /* Check if the timer has expired, or memory is full. */
1039 gettimeofday(&tv, 0);
1040 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1041 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1042
1043 if (running_msec < devc->limit_msec && numchunks < 32767)
1044 return TRUE; /* While capturing... */
1045 else
1046 hw_dev_acquisition_stop(sdi, sdi);
1047
1048 }
1049
1050 if (devc->state.state == SIGMA_DOWNLOAD) {
1051 if (devc->state.chunks_downloaded >= numchunks) {
1052 /* End of samples. */
1053 packet.type = SR_DF_END;
1054 sr_session_send(devc->cb_data, &packet);
1055
1056 devc->state.state = SIGMA_IDLE;
1057
1058 return TRUE;
1059 }
1060
1061 newchunks = MIN(chunks_per_read,
1062 numchunks - devc->state.chunks_downloaded);
1063
1064 sr_info("Downloading sample data: %.0f %%.",
1065 100.0 * devc->state.chunks_downloaded / numchunks);
1066
1067 bufsz = sigma_read_dram(devc->state.chunks_downloaded,
1068 newchunks, buf, devc);
1069 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1070 (void)bufsz;
1071
1072 /* Find first ts. */
1073 if (devc->state.chunks_downloaded == 0) {
1074 devc->state.lastts = *(uint16_t *) buf - 1;
1075 devc->state.lastsample = 0;
1076 }
1077
1078 /* Decode chunks and send them to sigrok. */
1079 for (i = 0; i < newchunks; ++i) {
1080 int limit_chunk = 0;
1081
1082 /* The last chunk may potentially be only in part. */
1083 if (devc->state.chunks_downloaded == numchunks - 1) {
1084 /* Find the last valid timestamp */
1085 limit_chunk = devc->state.stoppos % 512 + devc->state.lastts;
1086 }
1087
1088 if (devc->state.chunks_downloaded + i == devc->state.triggerchunk)
1089 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1090 &devc->state.lastts,
1091 &devc->state.lastsample,
1092 devc->state.triggerpos & 0x1ff,
1093 limit_chunk, sdi);
1094 else
1095 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1096 &devc->state.lastts,
1097 &devc->state.lastsample,
1098 -1, limit_chunk, sdi);
1099
1100 ++devc->state.chunks_downloaded;
1101 }
1102 }
1103
1104 return TRUE;
1105}
1106
1107/* Build a LUT entry used by the trigger functions. */
1108static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1109{
1110 int i, j, k, bit;
1111
1112 /* For each quad probe. */
1113 for (i = 0; i < 4; ++i) {
1114 entry[i] = 0xffff;
1115
1116 /* For each bit in LUT. */
1117 for (j = 0; j < 16; ++j)
1118
1119 /* For each probe in quad. */
1120 for (k = 0; k < 4; ++k) {
1121 bit = 1 << (i * 4 + k);
1122
1123 /* Set bit in entry */
1124 if ((mask & bit) &&
1125 ((!(value & bit)) !=
1126 (!(j & (1 << k)))))
1127 entry[i] &= ~(1 << j);
1128 }
1129 }
1130}
1131
1132/* Add a logical function to LUT mask. */
1133static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1134 int index, int neg, uint16_t *mask)
1135{
1136 int i, j;
1137 int x[2][2], tmp, a, b, aset, bset, rset;
1138
1139 memset(x, 0, 4 * sizeof(int));
1140
1141 /* Trigger detect condition. */
1142 switch (oper) {
1143 case OP_LEVEL:
1144 x[0][1] = 1;
1145 x[1][1] = 1;
1146 break;
1147 case OP_NOT:
1148 x[0][0] = 1;
1149 x[1][0] = 1;
1150 break;
1151 case OP_RISE:
1152 x[0][1] = 1;
1153 break;
1154 case OP_FALL:
1155 x[1][0] = 1;
1156 break;
1157 case OP_RISEFALL:
1158 x[0][1] = 1;
1159 x[1][0] = 1;
1160 break;
1161 case OP_NOTRISE:
1162 x[1][1] = 1;
1163 x[0][0] = 1;
1164 x[1][0] = 1;
1165 break;
1166 case OP_NOTFALL:
1167 x[1][1] = 1;
1168 x[0][0] = 1;
1169 x[0][1] = 1;
1170 break;
1171 case OP_NOTRISEFALL:
1172 x[1][1] = 1;
1173 x[0][0] = 1;
1174 break;
1175 }
1176
1177 /* Transpose if neg is set. */
1178 if (neg) {
1179 for (i = 0; i < 2; ++i) {
1180 for (j = 0; j < 2; ++j) {
1181 tmp = x[i][j];
1182 x[i][j] = x[1-i][1-j];
1183 x[1-i][1-j] = tmp;
1184 }
1185 }
1186 }
1187
1188 /* Update mask with function. */
1189 for (i = 0; i < 16; ++i) {
1190 a = (i >> (2 * index + 0)) & 1;
1191 b = (i >> (2 * index + 1)) & 1;
1192
1193 aset = (*mask >> i) & 1;
1194 bset = x[b][a];
1195
1196 if (func == FUNC_AND || func == FUNC_NAND)
1197 rset = aset & bset;
1198 else if (func == FUNC_OR || func == FUNC_NOR)
1199 rset = aset | bset;
1200 else if (func == FUNC_XOR || func == FUNC_NXOR)
1201 rset = aset ^ bset;
1202
1203 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1204 rset = !rset;
1205
1206 *mask &= ~(1 << i);
1207
1208 if (rset)
1209 *mask |= 1 << i;
1210 }
1211}
1212
1213/*
1214 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1215 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1216 * set at any time, but a full mask and value can be set (0/1).
1217 */
1218static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1219{
1220 int i,j;
1221 uint16_t masks[2] = { 0, 0 };
1222
1223 memset(lut, 0, sizeof(struct triggerlut));
1224
1225 /* Contant for simple triggers. */
1226 lut->m4 = 0xa000;
1227
1228 /* Value/mask trigger support. */
1229 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1230 lut->m2d);
1231
1232 /* Rise/fall trigger support. */
1233 for (i = 0, j = 0; i < 16; ++i) {
1234 if (devc->trigger.risingmask & (1 << i) ||
1235 devc->trigger.fallingmask & (1 << i))
1236 masks[j++] = 1 << i;
1237 }
1238
1239 build_lut_entry(masks[0], masks[0], lut->m0d);
1240 build_lut_entry(masks[1], masks[1], lut->m1d);
1241
1242 /* Add glue logic */
1243 if (masks[0] || masks[1]) {
1244 /* Transition trigger. */
1245 if (masks[0] & devc->trigger.risingmask)
1246 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1247 if (masks[0] & devc->trigger.fallingmask)
1248 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1249 if (masks[1] & devc->trigger.risingmask)
1250 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1251 if (masks[1] & devc->trigger.fallingmask)
1252 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1253 } else {
1254 /* Only value/mask trigger. */
1255 lut->m3 = 0xffff;
1256 }
1257
1258 /* Triggertype: event. */
1259 lut->params.selres = 3;
1260
1261 return SR_OK;
1262}
1263
1264static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
1265 void *cb_data)
1266{
1267 struct dev_context *devc;
1268 struct clockselect_50 clockselect;
1269 int frac, triggerpin, ret;
1270 uint8_t triggerselect = 0;
1271 struct triggerinout triggerinout_conf;
1272 struct triggerlut lut;
1273
1274 devc = sdi->priv;
1275
1276 if (configure_probes(sdi) != SR_OK) {
1277 sr_err("Failed to configure probes.");
1278 return SR_ERR;
1279 }
1280
1281 /* If the samplerate has not been set, default to 200 kHz. */
1282 if (devc->cur_firmware == -1) {
1283 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1284 return ret;
1285 }
1286
1287 /* Enter trigger programming mode. */
1288 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1289
1290 /* 100 and 200 MHz mode. */
1291 if (devc->cur_samplerate >= SR_MHZ(100)) {
1292 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1293
1294 /* Find which pin to trigger on from mask. */
1295 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1296 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1297 (1 << triggerpin))
1298 break;
1299
1300 /* Set trigger pin and light LED on trigger. */
1301 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1302
1303 /* Default rising edge. */
1304 if (devc->trigger.fallingmask)
1305 triggerselect |= 1 << 3;
1306
1307 /* All other modes. */
1308 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1309 build_basic_trigger(&lut, devc);
1310
1311 sigma_write_trigger_lut(&lut, devc);
1312
1313 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1314 }
1315
1316 /* Setup trigger in and out pins to default values. */
1317 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1318 triggerinout_conf.trgout_bytrigger = 1;
1319 triggerinout_conf.trgout_enable = 1;
1320
1321 sigma_write_register(WRITE_TRIGGER_OPTION,
1322 (uint8_t *) &triggerinout_conf,
1323 sizeof(struct triggerinout), devc);
1324
1325 /* Go back to normal mode. */
1326 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1327
1328 /* Set clock select register. */
1329 if (devc->cur_samplerate == SR_MHZ(200))
1330 /* Enable 4 probes. */
1331 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1332 else if (devc->cur_samplerate == SR_MHZ(100))
1333 /* Enable 8 probes. */
1334 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1335 else {
1336 /*
1337 * 50 MHz mode (or fraction thereof). Any fraction down to
1338 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1339 */
1340 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1341
1342 clockselect.async = 0;
1343 clockselect.fraction = frac;
1344 clockselect.disabled_probes = 0;
1345
1346 sigma_write_register(WRITE_CLOCK_SELECT,
1347 (uint8_t *) &clockselect,
1348 sizeof(clockselect), devc);
1349 }
1350
1351 /* Setup maximum post trigger time. */
1352 sigma_set_register(WRITE_POST_TRIGGER,
1353 (devc->capture_ratio * 255) / 100, devc);
1354
1355 /* Start acqusition. */
1356 gettimeofday(&devc->start_tv, 0);
1357 sigma_set_register(WRITE_MODE, 0x0d, devc);
1358
1359 devc->cb_data = cb_data;
1360
1361 /* Send header packet to the session bus. */
1362 std_session_send_df_header(cb_data, DRIVER_LOG_DOMAIN);
1363
1364 /* Add capture source. */
1365 sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
1366
1367 devc->state.state = SIGMA_CAPTURE;
1368
1369 return SR_OK;
1370}
1371
1372static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1373{
1374 struct dev_context *devc;
1375 uint8_t modestatus;
1376
1377 (void)cb_data;
1378
1379 sr_source_remove(0);
1380
1381 if (!(devc = sdi->priv)) {
1382 sr_err("%s: sdi->priv was NULL", __func__);
1383 return SR_ERR_BUG;
1384 }
1385
1386 /* Stop acquisition. */
1387 sigma_set_register(WRITE_MODE, 0x11, devc);
1388
1389 /* Set SDRAM Read Enable. */
1390 sigma_set_register(WRITE_MODE, 0x02, devc);
1391
1392 /* Get the current position. */
1393 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1394
1395 /* Check if trigger has fired. */
1396 modestatus = sigma_get_register(READ_MODE, devc);
1397 if (modestatus & 0x20)
1398 devc->state.triggerchunk = devc->state.triggerpos / 512;
1399 else
1400 devc->state.triggerchunk = -1;
1401
1402 devc->state.chunks_downloaded = 0;
1403
1404 devc->state.state = SIGMA_DOWNLOAD;
1405
1406 return SR_OK;
1407}
1408
1409SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1410 .name = "asix-sigma",
1411 .longname = "ASIX SIGMA/SIGMA2",
1412 .api_version = 1,
1413 .init = hw_init,
1414 .cleanup = hw_cleanup,
1415 .scan = hw_scan,
1416 .dev_list = hw_dev_list,
1417 .dev_clear = clear_instances,
1418 .config_get = config_get,
1419 .config_set = config_set,
1420 .config_list = config_list,
1421 .dev_open = hw_dev_open,
1422 .dev_close = hw_dev_close,
1423 .dev_acquisition_start = hw_dev_acquisition_start,
1424 .dev_acquisition_stop = hw_dev_acquisition_stop,
1425 .priv = NULL,
1426};
Hardware access and backend lib