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1/*
2 * This file is part of the sigrok project.
3 *
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22/*
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
24 */
25
26#include <glib.h>
27#include <glib/gstdio.h>
28#include <ftdi.h>
29#include <string.h>
30#include "libsigrok.h"
31#include "libsigrok-internal.h"
32#include "asix-sigma.h"
33
34#define USB_VENDOR 0xa600
35#define USB_PRODUCT 0xa000
36#define USB_DESCRIPTION "ASIX SIGMA"
37#define USB_VENDOR_NAME "ASIX"
38#define USB_MODEL_NAME "SIGMA"
39#define USB_MODEL_VERSION ""
40#define TRIGGER_TYPES "rf10"
41#define NUM_PROBES 16
42
43SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
44static struct sr_dev_driver *di = &asix_sigma_driver_info;
45static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
46
47static const uint64_t supported_samplerates[] = {
48 SR_KHZ(200),
49 SR_KHZ(250),
50 SR_KHZ(500),
51 SR_MHZ(1),
52 SR_MHZ(5),
53 SR_MHZ(10),
54 SR_MHZ(25),
55 SR_MHZ(50),
56 SR_MHZ(100),
57 SR_MHZ(200),
58 0,
59};
60
61/*
62 * Probe numbers seem to go from 1-16, according to this image:
63 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
64 * (the cable has two additional GND pins, and a TI and TO pin)
65 */
66static const char *probe_names[NUM_PROBES + 1] = {
67 "1",
68 "2",
69 "3",
70 "4",
71 "5",
72 "6",
73 "7",
74 "8",
75 "9",
76 "10",
77 "11",
78 "12",
79 "13",
80 "14",
81 "15",
82 "16",
83 NULL,
84};
85
86static const struct sr_samplerates samplerates = {
87 0,
88 0,
89 0,
90 supported_samplerates,
91};
92
93static const int hwcaps[] = {
94 SR_HWCAP_LOGIC_ANALYZER,
95 SR_HWCAP_SAMPLERATE,
96 SR_HWCAP_CAPTURE_RATIO,
97
98 SR_HWCAP_LIMIT_MSEC,
99 0,
100};
101
102/* Force the FPGA to reboot. */
103static uint8_t suicide[] = {
104 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
105};
106
107/* Prepare to upload firmware (FPGA specific). */
108static uint8_t init[] = {
109 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
110};
111
112/* Initialize the logic analyzer mode. */
113static uint8_t logic_mode_start[] = {
114 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
115 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
116};
117
118static const char *firmware_files[] = {
119 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
120 "asix-sigma-100.fw", /* 100 MHz */
121 "asix-sigma-200.fw", /* 200 MHz */
122 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
123 "asix-sigma-phasor.fw", /* Frequency counter */
124};
125
126static int sigma_read(void *buf, size_t size, struct dev_context *devc)
127{
128 int ret;
129
130 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
131 if (ret < 0) {
132 sr_err("ftdi_read_data failed: %s",
133 ftdi_get_error_string(&devc->ftdic));
134 }
135
136 return ret;
137}
138
139static int sigma_write(void *buf, size_t size, struct dev_context *devc)
140{
141 int ret;
142
143 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
144 if (ret < 0) {
145 sr_err("ftdi_write_data failed: %s",
146 ftdi_get_error_string(&devc->ftdic));
147 } else if ((size_t) ret != size) {
148 sr_err("ftdi_write_data did not complete write.");
149 }
150
151 return ret;
152}
153
154static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
155 struct dev_context *devc)
156{
157 size_t i;
158 uint8_t buf[len + 2];
159 int idx = 0;
160
161 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
162 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
163
164 for (i = 0; i < len; ++i) {
165 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
166 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
167 }
168
169 return sigma_write(buf, idx, devc);
170}
171
172static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
173{
174 return sigma_write_register(reg, &value, 1, devc);
175}
176
177static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
178 struct dev_context *devc)
179{
180 uint8_t buf[3];
181
182 buf[0] = REG_ADDR_LOW | (reg & 0xf);
183 buf[1] = REG_ADDR_HIGH | (reg >> 4);
184 buf[2] = REG_READ_ADDR;
185
186 sigma_write(buf, sizeof(buf), devc);
187
188 return sigma_read(data, len, devc);
189}
190
191static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
192{
193 uint8_t value;
194
195 if (1 != sigma_read_register(reg, &value, 1, devc)) {
196 sr_err("sigma_get_register: 1 byte expected");
197 return 0;
198 }
199
200 return value;
201}
202
203static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
204 struct dev_context *devc)
205{
206 uint8_t buf[] = {
207 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
208
209 REG_READ_ADDR | NEXT_REG,
210 REG_READ_ADDR | NEXT_REG,
211 REG_READ_ADDR | NEXT_REG,
212 REG_READ_ADDR | NEXT_REG,
213 REG_READ_ADDR | NEXT_REG,
214 REG_READ_ADDR | NEXT_REG,
215 };
216 uint8_t result[6];
217
218 sigma_write(buf, sizeof(buf), devc);
219
220 sigma_read(result, sizeof(result), devc);
221
222 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
223 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
224
225 /* Not really sure why this must be done, but according to spec. */
226 if ((--*stoppos & 0x1ff) == 0x1ff)
227 stoppos -= 64;
228
229 if ((*--triggerpos & 0x1ff) == 0x1ff)
230 triggerpos -= 64;
231
232 return 1;
233}
234
235static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
236 uint8_t *data, struct dev_context *devc)
237{
238 size_t i;
239 uint8_t buf[4096];
240 int idx = 0;
241
242 /* Send the startchunk. Index start with 1. */
243 buf[0] = startchunk >> 8;
244 buf[1] = startchunk & 0xff;
245 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
246
247 /* Read the DRAM. */
248 buf[idx++] = REG_DRAM_BLOCK;
249 buf[idx++] = REG_DRAM_WAIT_ACK;
250
251 for (i = 0; i < numchunks; ++i) {
252 /* Alternate bit to copy from DRAM to cache. */
253 if (i != (numchunks - 1))
254 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
255
256 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
257
258 if (i != (numchunks - 1))
259 buf[idx++] = REG_DRAM_WAIT_ACK;
260 }
261
262 sigma_write(buf, idx, devc);
263
264 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
265}
266
267/* Upload trigger look-up tables to Sigma. */
268static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
269{
270 int i;
271 uint8_t tmp[2];
272 uint16_t bit;
273
274 /* Transpose the table and send to Sigma. */
275 for (i = 0; i < 16; ++i) {
276 bit = 1 << i;
277
278 tmp[0] = tmp[1] = 0;
279
280 if (lut->m2d[0] & bit)
281 tmp[0] |= 0x01;
282 if (lut->m2d[1] & bit)
283 tmp[0] |= 0x02;
284 if (lut->m2d[2] & bit)
285 tmp[0] |= 0x04;
286 if (lut->m2d[3] & bit)
287 tmp[0] |= 0x08;
288
289 if (lut->m3 & bit)
290 tmp[0] |= 0x10;
291 if (lut->m3s & bit)
292 tmp[0] |= 0x20;
293 if (lut->m4 & bit)
294 tmp[0] |= 0x40;
295
296 if (lut->m0d[0] & bit)
297 tmp[1] |= 0x01;
298 if (lut->m0d[1] & bit)
299 tmp[1] |= 0x02;
300 if (lut->m0d[2] & bit)
301 tmp[1] |= 0x04;
302 if (lut->m0d[3] & bit)
303 tmp[1] |= 0x08;
304
305 if (lut->m1d[0] & bit)
306 tmp[1] |= 0x10;
307 if (lut->m1d[1] & bit)
308 tmp[1] |= 0x20;
309 if (lut->m1d[2] & bit)
310 tmp[1] |= 0x40;
311 if (lut->m1d[3] & bit)
312 tmp[1] |= 0x80;
313
314 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
315 devc);
316 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
317 }
318
319 /* Send the parameters */
320 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
321 sizeof(lut->params), devc);
322
323 return SR_OK;
324}
325
326/* Generate the bitbang stream for programming the FPGA. */
327static int bin2bitbang(const char *filename,
328 unsigned char **buf, size_t *buf_size)
329{
330 FILE *f;
331 unsigned long file_size;
332 unsigned long offset = 0;
333 unsigned char *p;
334 uint8_t *firmware;
335 unsigned long fwsize = 0;
336 const int buffer_size = 65536;
337 size_t i;
338 int c, bit, v;
339 uint32_t imm = 0x3f6df2ab;
340
341 f = g_fopen(filename, "rb");
342 if (!f) {
343 sr_err("g_fopen(\"%s\", \"rb\")", filename);
344 return SR_ERR;
345 }
346
347 if (-1 == fseek(f, 0, SEEK_END)) {
348 sr_err("fseek on %s failed", filename);
349 fclose(f);
350 return SR_ERR;
351 }
352
353 file_size = ftell(f);
354
355 fseek(f, 0, SEEK_SET);
356
357 if (!(firmware = g_try_malloc(buffer_size))) {
358 sr_err("%s: firmware malloc failed", __func__);
359 fclose(f);
360 return SR_ERR_MALLOC;
361 }
362
363 while ((c = getc(f)) != EOF) {
364 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
365 firmware[fwsize++] = c ^ imm;
366 }
367 fclose(f);
368
369 if(fwsize != file_size) {
370 sr_err("%s: Error reading firmware", filename);
371 fclose(f);
372 g_free(firmware);
373 return SR_ERR;
374 }
375
376 *buf_size = fwsize * 2 * 8;
377
378 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
379 if (!p) {
380 sr_err("%s: buf/p malloc failed", __func__);
381 g_free(firmware);
382 return SR_ERR_MALLOC;
383 }
384
385 for (i = 0; i < fwsize; ++i) {
386 for (bit = 7; bit >= 0; --bit) {
387 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
388 p[offset++] = v | 0x01;
389 p[offset++] = v;
390 }
391 }
392
393 g_free(firmware);
394
395 if (offset != *buf_size) {
396 g_free(*buf);
397 sr_err("Error reading firmware %s "
398 "offset=%ld, file_size=%ld, buf_size=%zd.",
399 filename, offset, file_size, *buf_size);
400
401 return SR_ERR;
402 }
403
404 return SR_OK;
405}
406
407static int clear_instances(void)
408{
409 GSList *l;
410 struct sr_dev_inst *sdi;
411 struct drv_context *drvc;
412 struct dev_context *devc;
413
414 drvc = di->priv;
415
416 /* Properly close all devices. */
417 for (l = drvc->instances; l; l = l->next) {
418 if (!(sdi = l->data)) {
419 /* Log error, but continue cleaning up the rest. */
420 sr_err("%s: sdi was NULL, continuing", __func__);
421 continue;
422 }
423 if (sdi->priv) {
424 devc = sdi->priv;
425 ftdi_free(&devc->ftdic);
426 }
427 sr_dev_inst_free(sdi);
428 }
429 g_slist_free(drvc->instances);
430 drvc->instances = NULL;
431
432 return SR_OK;
433}
434
435static int hw_init(struct sr_context *sr_ctx)
436{
437 struct drv_context *drvc;
438
439 if (!(drvc = g_try_malloc0(sizeof(struct drv_context)))) {
440 sr_err("Driver context malloc failed.");
441 return SR_ERR_MALLOC;
442 }
443 drvc->sr_ctx = sr_ctx;
444 di->priv = drvc;
445
446 return SR_OK;
447}
448
449static GSList *hw_scan(GSList *options)
450{
451 struct sr_dev_inst *sdi;
452 struct sr_probe *probe;
453 struct drv_context *drvc;
454 struct dev_context *devc;
455 GSList *devices;
456 struct ftdi_device_list *devlist;
457 char serial_txt[10];
458 uint32_t serial;
459 int ret, i;
460
461 (void)options;
462
463 drvc = di->priv;
464 devices = NULL;
465 clear_instances();
466
467 if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
468 sr_err("%s: devc malloc failed", __func__);
469 return NULL;
470 }
471
472 ftdi_init(&devc->ftdic);
473
474 /* Look for SIGMAs. */
475
476 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
477 USB_VENDOR, USB_PRODUCT)) <= 0) {
478 if (ret < 0)
479 sr_err("ftdi_usb_find_all(): %d", ret);
480 goto free;
481 }
482
483 /* Make sure it's a version 1 or 2 SIGMA. */
484 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
485 serial_txt, sizeof(serial_txt));
486 sscanf(serial_txt, "%x", &serial);
487
488 if (serial < 0xa6010000 || serial > 0xa602ffff) {
489 sr_err("Only SIGMA and SIGMA2 are supported "
490 "in this version of libsigrok.");
491 goto free;
492 }
493
494 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
495
496 devc->cur_samplerate = 0;
497 devc->period_ps = 0;
498 devc->limit_msec = 0;
499 devc->cur_firmware = -1;
500 devc->num_probes = 0;
501 devc->samples_per_event = 0;
502 devc->capture_ratio = 50;
503 devc->use_triggers = 0;
504
505 /* Register SIGMA device. */
506 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
507 USB_MODEL_NAME, USB_MODEL_VERSION))) {
508 sr_err("%s: sdi was NULL", __func__);
509 goto free;
510 }
511 sdi->driver = di;
512
513 for (i = 0; probe_names[i]; i++) {
514 if (!(probe = sr_probe_new(i, SR_PROBE_LOGIC, TRUE,
515 probe_names[i])))
516 return NULL;
517 sdi->probes = g_slist_append(sdi->probes, probe);
518 }
519
520 devices = g_slist_append(devices, sdi);
521 drvc->instances = g_slist_append(drvc->instances, sdi);
522 sdi->priv = devc;
523
524 /* We will open the device again when we need it. */
525 ftdi_list_free(&devlist);
526
527 return devices;
528
529free:
530 ftdi_deinit(&devc->ftdic);
531 g_free(devc);
532 return NULL;
533}
534
535static GSList *hw_dev_list(void)
536{
537 struct drv_context *drvc;
538
539 drvc = di->priv;
540
541 return drvc->instances;
542}
543
544static int upload_firmware(int firmware_idx, struct dev_context *devc)
545{
546 int ret;
547 unsigned char *buf;
548 unsigned char pins;
549 size_t buf_size;
550 unsigned char result[32];
551 char firmware_path[128];
552
553 /* Make sure it's an ASIX SIGMA. */
554 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
555 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
556 sr_err("ftdi_usb_open failed: %s",
557 ftdi_get_error_string(&devc->ftdic));
558 return 0;
559 }
560
561 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
562 sr_err("ftdi_set_bitmode failed: %s",
563 ftdi_get_error_string(&devc->ftdic));
564 return 0;
565 }
566
567 /* Four times the speed of sigmalogan - Works well. */
568 if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) {
569 sr_err("ftdi_set_baudrate failed: %s",
570 ftdi_get_error_string(&devc->ftdic));
571 return 0;
572 }
573
574 /* Force the FPGA to reboot. */
575 sigma_write(suicide, sizeof(suicide), devc);
576 sigma_write(suicide, sizeof(suicide), devc);
577 sigma_write(suicide, sizeof(suicide), devc);
578 sigma_write(suicide, sizeof(suicide), devc);
579
580 /* Prepare to upload firmware (FPGA specific). */
581 sigma_write(init, sizeof(init), devc);
582
583 ftdi_usb_purge_buffers(&devc->ftdic);
584
585 /* Wait until the FPGA asserts INIT_B. */
586 while (1) {
587 ret = sigma_read(result, 1, devc);
588 if (result[0] & 0x20)
589 break;
590 }
591
592 /* Prepare firmware. */
593 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
594 firmware_files[firmware_idx]);
595
596 if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
597 sr_err("An error occured while reading the firmware: %s",
598 firmware_path);
599 return ret;
600 }
601
602 /* Upload firmare. */
603 sr_info("Uploading firmware file '%s'.", firmware_files[firmware_idx]);
604 sigma_write(buf, buf_size, devc);
605
606 g_free(buf);
607
608 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) {
609 sr_err("ftdi_set_bitmode failed: %s",
610 ftdi_get_error_string(&devc->ftdic));
611 return SR_ERR;
612 }
613
614 ftdi_usb_purge_buffers(&devc->ftdic);
615
616 /* Discard garbage. */
617 while (1 == sigma_read(&pins, 1, devc))
618 ;
619
620 /* Initialize the logic analyzer mode. */
621 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
622
623 /* Expect a 3 byte reply. */
624 ret = sigma_read(result, 3, devc);
625 if (ret != 3 ||
626 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
627 sr_err("Configuration failed. Invalid reply received.");
628 return SR_ERR;
629 }
630
631 devc->cur_firmware = firmware_idx;
632
633 sr_info("Firmware uploaded.");
634
635 return SR_OK;
636}
637
638static int hw_dev_open(struct sr_dev_inst *sdi)
639{
640 struct dev_context *devc;
641 int ret;
642
643 devc = sdi->priv;
644
645 /* Make sure it's an ASIX SIGMA. */
646 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
647 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
648
649 sr_err("ftdi_usb_open failed: %s",
650 ftdi_get_error_string(&devc->ftdic));
651
652 return 0;
653 }
654
655 sdi->status = SR_ST_ACTIVE;
656
657 return SR_OK;
658}
659
660static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
661{
662 int i, ret;
663 struct dev_context *devc = sdi->priv;
664
665 for (i = 0; supported_samplerates[i]; i++) {
666 if (supported_samplerates[i] == samplerate)
667 break;
668 }
669 if (supported_samplerates[i] == 0)
670 return SR_ERR_SAMPLERATE;
671
672 if (samplerate <= SR_MHZ(50)) {
673 ret = upload_firmware(0, devc);
674 devc->num_probes = 16;
675 }
676 if (samplerate == SR_MHZ(100)) {
677 ret = upload_firmware(1, devc);
678 devc->num_probes = 8;
679 }
680 else if (samplerate == SR_MHZ(200)) {
681 ret = upload_firmware(2, devc);
682 devc->num_probes = 4;
683 }
684
685 devc->cur_samplerate = samplerate;
686 devc->period_ps = 1000000000000 / samplerate;
687 devc->samples_per_event = 16 / devc->num_probes;
688 devc->state.state = SIGMA_IDLE;
689
690 return ret;
691}
692
693/*
694 * In 100 and 200 MHz mode, only a single pin rising/falling can be
695 * set as trigger. In other modes, two rising/falling triggers can be set,
696 * in addition to value/mask trigger for any number of probes.
697 *
698 * The Sigma supports complex triggers using boolean expressions, but this
699 * has not been implemented yet.
700 */
701static int configure_probes(const struct sr_dev_inst *sdi)
702{
703 struct dev_context *devc = sdi->priv;
704 const struct sr_probe *probe;
705 const GSList *l;
706 int trigger_set = 0;
707 int probebit;
708
709 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
710
711 for (l = sdi->probes; l; l = l->next) {
712 probe = (struct sr_probe *)l->data;
713 probebit = 1 << (probe->index);
714
715 if (!probe->enabled || !probe->trigger)
716 continue;
717
718 if (devc->cur_samplerate >= SR_MHZ(100)) {
719 /* Fast trigger support. */
720 if (trigger_set) {
721 sr_err("Only a single pin trigger in 100 and "
722 "200MHz mode is supported.");
723 return SR_ERR;
724 }
725 if (probe->trigger[0] == 'f')
726 devc->trigger.fallingmask |= probebit;
727 else if (probe->trigger[0] == 'r')
728 devc->trigger.risingmask |= probebit;
729 else {
730 sr_err("Only rising/falling trigger in 100 "
731 "and 200MHz mode is supported.");
732 return SR_ERR;
733 }
734
735 ++trigger_set;
736 } else {
737 /* Simple trigger support (event). */
738 if (probe->trigger[0] == '1') {
739 devc->trigger.simplevalue |= probebit;
740 devc->trigger.simplemask |= probebit;
741 }
742 else if (probe->trigger[0] == '0') {
743 devc->trigger.simplevalue &= ~probebit;
744 devc->trigger.simplemask |= probebit;
745 }
746 else if (probe->trigger[0] == 'f') {
747 devc->trigger.fallingmask |= probebit;
748 ++trigger_set;
749 }
750 else if (probe->trigger[0] == 'r') {
751 devc->trigger.risingmask |= probebit;
752 ++trigger_set;
753 }
754
755 /*
756 * Actually, Sigma supports 2 rising/falling triggers,
757 * but they are ORed and the current trigger syntax
758 * does not permit ORed triggers.
759 */
760 if (trigger_set > 1) {
761 sr_err("Only 1 rising/falling trigger "
762 "is supported.");
763 return SR_ERR;
764 }
765 }
766
767 if (trigger_set)
768 devc->use_triggers = 1;
769 }
770
771 return SR_OK;
772}
773
774static int hw_dev_close(struct sr_dev_inst *sdi)
775{
776 struct dev_context *devc;
777
778 if (!(devc = sdi->priv)) {
779 sr_err("%s: sdi->priv was NULL", __func__);
780 return SR_ERR_BUG;
781 }
782
783 /* TODO */
784 if (sdi->status == SR_ST_ACTIVE)
785 ftdi_usb_close(&devc->ftdic);
786
787 sdi->status = SR_ST_INACTIVE;
788
789 return SR_OK;
790}
791
792static int hw_cleanup(void)
793{
794 if (!di->priv)
795 return SR_OK;
796
797 clear_instances();
798
799 return SR_OK;
800}
801
802static int hw_info_get(int info_id, const void **data,
803 const struct sr_dev_inst *sdi)
804{
805 struct dev_context *devc;
806
807 switch (info_id) {
808 case SR_DI_HWCAPS:
809 *data = hwcaps;
810 break;
811 case SR_DI_NUM_PROBES:
812 *data = GINT_TO_POINTER(NUM_PROBES);
813 break;
814 case SR_DI_PROBE_NAMES:
815 *data = probe_names;
816 break;
817 case SR_DI_SAMPLERATES:
818 *data = &samplerates;
819 break;
820 case SR_DI_TRIGGER_TYPES:
821 *data = (char *)TRIGGER_TYPES;
822 break;
823 case SR_DI_CUR_SAMPLERATE:
824 if (sdi) {
825 devc = sdi->priv;
826 *data = &devc->cur_samplerate;
827 } else
828 return SR_ERR;
829 break;
830 default:
831 return SR_ERR_ARG;
832 }
833
834 return SR_OK;
835}
836
837static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap,
838 const void *value)
839{
840 struct dev_context *devc;
841 int ret;
842
843 devc = sdi->priv;
844
845 if (hwcap == SR_HWCAP_SAMPLERATE) {
846 ret = set_samplerate(sdi, *(const uint64_t *)value);
847 } else if (hwcap == SR_HWCAP_LIMIT_MSEC) {
848 devc->limit_msec = *(const uint64_t *)value;
849 if (devc->limit_msec > 0)
850 ret = SR_OK;
851 else
852 ret = SR_ERR;
853 } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) {
854 devc->capture_ratio = *(const uint64_t *)value;
855 if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
856 ret = SR_ERR;
857 else
858 ret = SR_OK;
859 } else {
860 ret = SR_ERR;
861 }
862
863 return ret;
864}
865
866/* Software trigger to determine exact trigger position. */
867static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
868 struct sigma_trigger *t)
869{
870 int i;
871
872 for (i = 0; i < 8; ++i) {
873 if (i > 0)
874 last_sample = samples[i-1];
875
876 /* Simple triggers. */
877 if ((samples[i] & t->simplemask) != t->simplevalue)
878 continue;
879
880 /* Rising edge. */
881 if ((last_sample & t->risingmask) != 0 || (samples[i] &
882 t->risingmask) != t->risingmask)
883 continue;
884
885 /* Falling edge. */
886 if ((last_sample & t->fallingmask) != t->fallingmask ||
887 (samples[i] & t->fallingmask) != 0)
888 continue;
889
890 break;
891 }
892
893 /* If we did not match, return original trigger pos. */
894 return i & 0x7;
895}
896
897/*
898 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
899 * Each event is 20ns apart, and can contain multiple samples.
900 *
901 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
902 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
903 * For 50 MHz and below, events contain one sample for each channel,
904 * spread 20 ns apart.
905 */
906static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
907 uint16_t *lastsample, int triggerpos,
908 uint16_t limit_chunk, void *cb_data)
909{
910 struct sr_dev_inst *sdi = cb_data;
911 struct dev_context *devc = sdi->priv;
912 uint16_t tsdiff, ts;
913 uint16_t samples[65536 * devc->samples_per_event];
914 struct sr_datafeed_packet packet;
915 struct sr_datafeed_logic logic;
916 int i, j, k, l, numpad, tosend;
917 size_t n = 0, sent = 0;
918 int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event;
919 uint16_t *event;
920 uint16_t cur_sample;
921 int triggerts = -1;
922
923 /* Check if trigger is in this chunk. */
924 if (triggerpos != -1) {
925 if (devc->cur_samplerate <= SR_MHZ(50))
926 triggerpos -= EVENTS_PER_CLUSTER - 1;
927
928 if (triggerpos < 0)
929 triggerpos = 0;
930
931 /* Find in which cluster the trigger occured. */
932 triggerts = triggerpos / 7;
933 }
934
935 /* For each ts. */
936 for (i = 0; i < 64; ++i) {
937 ts = *(uint16_t *) &buf[i * 16];
938 tsdiff = ts - *lastts;
939 *lastts = ts;
940
941 /* Decode partial chunk. */
942 if (limit_chunk && ts > limit_chunk)
943 return SR_OK;
944
945 /* Pad last sample up to current point. */
946 numpad = tsdiff * devc->samples_per_event - clustersize;
947 if (numpad > 0) {
948 for (j = 0; j < numpad; ++j)
949 samples[j] = *lastsample;
950
951 n = numpad;
952 }
953
954 /* Send samples between previous and this timestamp to sigrok. */
955 sent = 0;
956 while (sent < n) {
957 tosend = MIN(2048, n - sent);
958
959 packet.type = SR_DF_LOGIC;
960 packet.payload = &logic;
961 logic.length = tosend * sizeof(uint16_t);
962 logic.unitsize = 2;
963 logic.data = samples + sent;
964 sr_session_send(devc->session_dev_id, &packet);
965
966 sent += tosend;
967 }
968 n = 0;
969
970 event = (uint16_t *) &buf[i * 16 + 2];
971 cur_sample = 0;
972
973 /* For each event in cluster. */
974 for (j = 0; j < 7; ++j) {
975
976 /* For each sample in event. */
977 for (k = 0; k < devc->samples_per_event; ++k) {
978 cur_sample = 0;
979
980 /* For each probe. */
981 for (l = 0; l < devc->num_probes; ++l)
982 cur_sample |= (!!(event[j] & (1 << (l *
983 devc->samples_per_event + k)))) << l;
984
985 samples[n++] = cur_sample;
986 }
987 }
988
989 /* Send data up to trigger point (if triggered). */
990 sent = 0;
991 if (i == triggerts) {
992 /*
993 * Trigger is not always accurate to sample because of
994 * pipeline delay. However, it always triggers before
995 * the actual event. We therefore look at the next
996 * samples to pinpoint the exact position of the trigger.
997 */
998 tosend = get_trigger_offset(samples, *lastsample,
999 &devc->trigger);
1000
1001 if (tosend > 0) {
1002 packet.type = SR_DF_LOGIC;
1003 packet.payload = &logic;
1004 logic.length = tosend * sizeof(uint16_t);
1005 logic.unitsize = 2;
1006 logic.data = samples;
1007 sr_session_send(devc->session_dev_id, &packet);
1008
1009 sent += tosend;
1010 }
1011
1012 /* Only send trigger if explicitly enabled. */
1013 if (devc->use_triggers) {
1014 packet.type = SR_DF_TRIGGER;
1015 sr_session_send(devc->session_dev_id, &packet);
1016 }
1017 }
1018
1019 /* Send rest of the chunk to sigrok. */
1020 tosend = n - sent;
1021
1022 if (tosend > 0) {
1023 packet.type = SR_DF_LOGIC;
1024 packet.payload = &logic;
1025 logic.length = tosend * sizeof(uint16_t);
1026 logic.unitsize = 2;
1027 logic.data = samples + sent;
1028 sr_session_send(devc->session_dev_id, &packet);
1029 }
1030
1031 *lastsample = samples[n - 1];
1032 }
1033
1034 return SR_OK;
1035}
1036
1037static int receive_data(int fd, int revents, void *cb_data)
1038{
1039 struct sr_dev_inst *sdi = cb_data;
1040 struct dev_context *devc = sdi->priv;
1041 struct sr_datafeed_packet packet;
1042 const int chunks_per_read = 32;
1043 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1044 int bufsz, numchunks, i, newchunks;
1045 uint64_t running_msec;
1046 struct timeval tv;
1047
1048 (void)fd;
1049 (void)revents;
1050
1051 /* Get the current position. */
1052 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1053
1054 numchunks = (devc->state.stoppos + 511) / 512;
1055
1056 if (devc->state.state == SIGMA_IDLE)
1057 return TRUE;
1058
1059 if (devc->state.state == SIGMA_CAPTURE) {
1060 /* Check if the timer has expired, or memory is full. */
1061 gettimeofday(&tv, 0);
1062 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1063 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1064
1065 if (running_msec < devc->limit_msec && numchunks < 32767)
1066 return TRUE; /* While capturing... */
1067 else
1068 hw_dev_acquisition_stop(sdi, sdi);
1069
1070 } else if (devc->state.state == SIGMA_DOWNLOAD) {
1071 if (devc->state.chunks_downloaded >= numchunks) {
1072 /* End of samples. */
1073 packet.type = SR_DF_END;
1074 sr_session_send(devc->session_dev_id, &packet);
1075
1076 devc->state.state = SIGMA_IDLE;
1077
1078 return TRUE;
1079 }
1080
1081 newchunks = MIN(chunks_per_read,
1082 numchunks - devc->state.chunks_downloaded);
1083
1084 sr_info("Downloading sample data: %.0f %%.",
1085 100.0 * devc->state.chunks_downloaded / numchunks);
1086
1087 bufsz = sigma_read_dram(devc->state.chunks_downloaded,
1088 newchunks, buf, devc);
1089 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1090 (void)bufsz;
1091
1092 /* Find first ts. */
1093 if (devc->state.chunks_downloaded == 0) {
1094 devc->state.lastts = *(uint16_t *) buf - 1;
1095 devc->state.lastsample = 0;
1096 }
1097
1098 /* Decode chunks and send them to sigrok. */
1099 for (i = 0; i < newchunks; ++i) {
1100 int limit_chunk = 0;
1101
1102 /* The last chunk may potentially be only in part. */
1103 if (devc->state.chunks_downloaded == numchunks - 1) {
1104 /* Find the last valid timestamp */
1105 limit_chunk = devc->state.stoppos % 512 + devc->state.lastts;
1106 }
1107
1108 if (devc->state.chunks_downloaded + i == devc->state.triggerchunk)
1109 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1110 &devc->state.lastts,
1111 &devc->state.lastsample,
1112 devc->state.triggerpos & 0x1ff,
1113 limit_chunk, sdi);
1114 else
1115 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1116 &devc->state.lastts,
1117 &devc->state.lastsample,
1118 -1, limit_chunk, sdi);
1119
1120 ++devc->state.chunks_downloaded;
1121 }
1122 }
1123
1124 return TRUE;
1125}
1126
1127/* Build a LUT entry used by the trigger functions. */
1128static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1129{
1130 int i, j, k, bit;
1131
1132 /* For each quad probe. */
1133 for (i = 0; i < 4; ++i) {
1134 entry[i] = 0xffff;
1135
1136 /* For each bit in LUT. */
1137 for (j = 0; j < 16; ++j)
1138
1139 /* For each probe in quad. */
1140 for (k = 0; k < 4; ++k) {
1141 bit = 1 << (i * 4 + k);
1142
1143 /* Set bit in entry */
1144 if ((mask & bit) &&
1145 ((!(value & bit)) !=
1146 (!(j & (1 << k)))))
1147 entry[i] &= ~(1 << j);
1148 }
1149 }
1150}
1151
1152/* Add a logical function to LUT mask. */
1153static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1154 int index, int neg, uint16_t *mask)
1155{
1156 int i, j;
1157 int x[2][2], tmp, a, b, aset, bset, rset;
1158
1159 memset(x, 0, 4 * sizeof(int));
1160
1161 /* Trigger detect condition. */
1162 switch (oper) {
1163 case OP_LEVEL:
1164 x[0][1] = 1;
1165 x[1][1] = 1;
1166 break;
1167 case OP_NOT:
1168 x[0][0] = 1;
1169 x[1][0] = 1;
1170 break;
1171 case OP_RISE:
1172 x[0][1] = 1;
1173 break;
1174 case OP_FALL:
1175 x[1][0] = 1;
1176 break;
1177 case OP_RISEFALL:
1178 x[0][1] = 1;
1179 x[1][0] = 1;
1180 break;
1181 case OP_NOTRISE:
1182 x[1][1] = 1;
1183 x[0][0] = 1;
1184 x[1][0] = 1;
1185 break;
1186 case OP_NOTFALL:
1187 x[1][1] = 1;
1188 x[0][0] = 1;
1189 x[0][1] = 1;
1190 break;
1191 case OP_NOTRISEFALL:
1192 x[1][1] = 1;
1193 x[0][0] = 1;
1194 break;
1195 }
1196
1197 /* Transpose if neg is set. */
1198 if (neg) {
1199 for (i = 0; i < 2; ++i) {
1200 for (j = 0; j < 2; ++j) {
1201 tmp = x[i][j];
1202 x[i][j] = x[1-i][1-j];
1203 x[1-i][1-j] = tmp;
1204 }
1205 }
1206 }
1207
1208 /* Update mask with function. */
1209 for (i = 0; i < 16; ++i) {
1210 a = (i >> (2 * index + 0)) & 1;
1211 b = (i >> (2 * index + 1)) & 1;
1212
1213 aset = (*mask >> i) & 1;
1214 bset = x[b][a];
1215
1216 if (func == FUNC_AND || func == FUNC_NAND)
1217 rset = aset & bset;
1218 else if (func == FUNC_OR || func == FUNC_NOR)
1219 rset = aset | bset;
1220 else if (func == FUNC_XOR || func == FUNC_NXOR)
1221 rset = aset ^ bset;
1222
1223 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1224 rset = !rset;
1225
1226 *mask &= ~(1 << i);
1227
1228 if (rset)
1229 *mask |= 1 << i;
1230 }
1231}
1232
1233/*
1234 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1235 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1236 * set at any time, but a full mask and value can be set (0/1).
1237 */
1238static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1239{
1240 int i,j;
1241 uint16_t masks[2] = { 0, 0 };
1242
1243 memset(lut, 0, sizeof(struct triggerlut));
1244
1245 /* Contant for simple triggers. */
1246 lut->m4 = 0xa000;
1247
1248 /* Value/mask trigger support. */
1249 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1250 lut->m2d);
1251
1252 /* Rise/fall trigger support. */
1253 for (i = 0, j = 0; i < 16; ++i) {
1254 if (devc->trigger.risingmask & (1 << i) ||
1255 devc->trigger.fallingmask & (1 << i))
1256 masks[j++] = 1 << i;
1257 }
1258
1259 build_lut_entry(masks[0], masks[0], lut->m0d);
1260 build_lut_entry(masks[1], masks[1], lut->m1d);
1261
1262 /* Add glue logic */
1263 if (masks[0] || masks[1]) {
1264 /* Transition trigger. */
1265 if (masks[0] & devc->trigger.risingmask)
1266 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1267 if (masks[0] & devc->trigger.fallingmask)
1268 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1269 if (masks[1] & devc->trigger.risingmask)
1270 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1271 if (masks[1] & devc->trigger.fallingmask)
1272 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1273 } else {
1274 /* Only value/mask trigger. */
1275 lut->m3 = 0xffff;
1276 }
1277
1278 /* Triggertype: event. */
1279 lut->params.selres = 3;
1280
1281 return SR_OK;
1282}
1283
1284static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
1285 void *cb_data)
1286{
1287 struct dev_context *devc;
1288 struct sr_datafeed_packet *packet;
1289 struct sr_datafeed_header *header;
1290 struct sr_datafeed_meta_logic meta;
1291 struct clockselect_50 clockselect;
1292 int frac, triggerpin, ret;
1293 uint8_t triggerselect;
1294 struct triggerinout triggerinout_conf;
1295 struct triggerlut lut;
1296
1297 devc = sdi->priv;
1298
1299 if (configure_probes(sdi) != SR_OK) {
1300 sr_err("Failed to configure probes.");
1301 return SR_ERR;
1302 }
1303
1304 /* If the samplerate has not been set, default to 200 kHz. */
1305 if (devc->cur_firmware == -1) {
1306 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1307 return ret;
1308 }
1309
1310 /* Enter trigger programming mode. */
1311 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1312
1313 /* 100 and 200 MHz mode. */
1314 if (devc->cur_samplerate >= SR_MHZ(100)) {
1315 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1316
1317 /* Find which pin to trigger on from mask. */
1318 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1319 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1320 (1 << triggerpin))
1321 break;
1322
1323 /* Set trigger pin and light LED on trigger. */
1324 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1325
1326 /* Default rising edge. */
1327 if (devc->trigger.fallingmask)
1328 triggerselect |= 1 << 3;
1329
1330 /* All other modes. */
1331 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1332 build_basic_trigger(&lut, devc);
1333
1334 sigma_write_trigger_lut(&lut, devc);
1335
1336 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1337 }
1338
1339 /* Setup trigger in and out pins to default values. */
1340 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1341 triggerinout_conf.trgout_bytrigger = 1;
1342 triggerinout_conf.trgout_enable = 1;
1343
1344 sigma_write_register(WRITE_TRIGGER_OPTION,
1345 (uint8_t *) &triggerinout_conf,
1346 sizeof(struct triggerinout), devc);
1347
1348 /* Go back to normal mode. */
1349 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1350
1351 /* Set clock select register. */
1352 if (devc->cur_samplerate == SR_MHZ(200))
1353 /* Enable 4 probes. */
1354 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1355 else if (devc->cur_samplerate == SR_MHZ(100))
1356 /* Enable 8 probes. */
1357 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1358 else {
1359 /*
1360 * 50 MHz mode (or fraction thereof). Any fraction down to
1361 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1362 */
1363 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1364
1365 clockselect.async = 0;
1366 clockselect.fraction = frac;
1367 clockselect.disabled_probes = 0;
1368
1369 sigma_write_register(WRITE_CLOCK_SELECT,
1370 (uint8_t *) &clockselect,
1371 sizeof(clockselect), devc);
1372 }
1373
1374 /* Setup maximum post trigger time. */
1375 sigma_set_register(WRITE_POST_TRIGGER,
1376 (devc->capture_ratio * 255) / 100, devc);
1377
1378 /* Start acqusition. */
1379 gettimeofday(&devc->start_tv, 0);
1380 sigma_set_register(WRITE_MODE, 0x0d, devc);
1381
1382 devc->session_dev_id = cb_data;
1383
1384 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1385 sr_err("%s: packet malloc failed.", __func__);
1386 return SR_ERR_MALLOC;
1387 }
1388
1389 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1390 sr_err("%s: header malloc failed.", __func__);
1391 return SR_ERR_MALLOC;
1392 }
1393
1394 /* Send header packet to the session bus. */
1395 packet->type = SR_DF_HEADER;
1396 packet->payload = header;
1397 header->feed_version = 1;
1398 gettimeofday(&header->starttime, NULL);
1399 sr_session_send(devc->session_dev_id, packet);
1400
1401 /* Send metadata about the SR_DF_LOGIC packets to come. */
1402 packet->type = SR_DF_META_LOGIC;
1403 packet->payload = &meta;
1404 meta.samplerate = devc->cur_samplerate;
1405 meta.num_probes = devc->num_probes;
1406 sr_session_send(devc->session_dev_id, packet);
1407
1408 /* Add capture source. */
1409 sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
1410
1411 g_free(header);
1412 g_free(packet);
1413
1414 devc->state.state = SIGMA_CAPTURE;
1415
1416 return SR_OK;
1417}
1418
1419static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1420{
1421 struct dev_context *devc;
1422 uint8_t modestatus;
1423
1424 (void)cb_data;
1425
1426 sr_source_remove(0);
1427
1428 if (!(devc = sdi->priv)) {
1429 sr_err("%s: sdi->priv was NULL", __func__);
1430 return SR_ERR_BUG;
1431 }
1432
1433 /* Stop acquisition. */
1434 sigma_set_register(WRITE_MODE, 0x11, devc);
1435
1436 /* Set SDRAM Read Enable. */
1437 sigma_set_register(WRITE_MODE, 0x02, devc);
1438
1439 /* Get the current position. */
1440 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1441
1442 /* Check if trigger has fired. */
1443 modestatus = sigma_get_register(READ_MODE, devc);
1444 if (modestatus & 0x20)
1445 devc->state.triggerchunk = devc->state.triggerpos / 512;
1446 else
1447 devc->state.triggerchunk = -1;
1448
1449 devc->state.chunks_downloaded = 0;
1450
1451 devc->state.state = SIGMA_DOWNLOAD;
1452
1453 return SR_OK;
1454}
1455
1456SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1457 .name = "asix-sigma",
1458 .longname = "ASIX SIGMA/SIGMA2",
1459 .api_version = 1,
1460 .init = hw_init,
1461 .cleanup = hw_cleanup,
1462 .scan = hw_scan,
1463 .dev_list = hw_dev_list,
1464 .dev_clear = clear_instances,
1465 .dev_open = hw_dev_open,
1466 .dev_close = hw_dev_close,
1467 .info_get = hw_info_get,
1468 .dev_config_set = hw_dev_config_set,
1469 .dev_acquisition_start = hw_dev_acquisition_start,
1470 .dev_acquisition_stop = hw_dev_acquisition_stop,
1471 .priv = NULL,
1472};
Hardware access and backend lib