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1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22/*
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
24 */
25
26#include <glib.h>
27#include <glib/gstdio.h>
28#include <ftdi.h>
29#include <string.h>
30#include "libsigrok.h"
31#include "libsigrok-internal.h"
32#include "asix-sigma.h"
33
34#define USB_VENDOR 0xa600
35#define USB_PRODUCT 0xa000
36#define USB_DESCRIPTION "ASIX SIGMA"
37#define USB_VENDOR_NAME "ASIX"
38#define USB_MODEL_NAME "SIGMA"
39#define TRIGGER_TYPE "rf10"
40
41SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
42static struct sr_dev_driver *di = &asix_sigma_driver_info;
43static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
44
45/*
46 * The ASIX Sigma supports arbitrary integer frequency divider in
47 * the 50MHz mode. The divider is in range 1...256 , allowing for
48 * very precise sampling rate selection. This driver supports only
49 * a subset of the sampling rates.
50 */
51static const uint64_t samplerates[] = {
52 SR_KHZ(200), /* div=250 */
53 SR_KHZ(250), /* div=200 */
54 SR_KHZ(500), /* div=100 */
55 SR_MHZ(1), /* div=50 */
56 SR_MHZ(5), /* div=10 */
57 SR_MHZ(10), /* div=5 */
58 SR_MHZ(25), /* div=2 */
59 SR_MHZ(50), /* div=1 */
60 SR_MHZ(100), /* Special FW needed */
61 SR_MHZ(200), /* Special FW needed */
62};
63
64/*
65 * Channel numbers seem to go from 1-16, according to this image:
66 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
67 * (the cable has two additional GND pins, and a TI and TO pin)
68 */
69static const char *channel_names[] = {
70 "1", "2", "3", "4", "5", "6", "7", "8",
71 "9", "10", "11", "12", "13", "14", "15", "16",
72};
73
74static const int32_t hwcaps[] = {
75 SR_CONF_LOGIC_ANALYZER,
76 SR_CONF_SAMPLERATE,
77 SR_CONF_TRIGGER_TYPE,
78 SR_CONF_CAPTURE_RATIO,
79 SR_CONF_LIMIT_MSEC,
80};
81
82static const char *sigma_firmware_files[] = {
83 /* 50 MHz, supports 8 bit fractions */
84 FIRMWARE_DIR "/asix-sigma-50.fw",
85 /* 100 MHz */
86 FIRMWARE_DIR "/asix-sigma-100.fw",
87 /* 200 MHz */
88 FIRMWARE_DIR "/asix-sigma-200.fw",
89 /* Synchronous clock from pin */
90 FIRMWARE_DIR "/asix-sigma-50sync.fw",
91 /* Frequency counter */
92 FIRMWARE_DIR "/asix-sigma-phasor.fw",
93};
94
95static int sigma_read(void *buf, size_t size, struct dev_context *devc)
96{
97 int ret;
98
99 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
100 if (ret < 0) {
101 sr_err("ftdi_read_data failed: %s",
102 ftdi_get_error_string(&devc->ftdic));
103 }
104
105 return ret;
106}
107
108static int sigma_write(void *buf, size_t size, struct dev_context *devc)
109{
110 int ret;
111
112 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
113 if (ret < 0) {
114 sr_err("ftdi_write_data failed: %s",
115 ftdi_get_error_string(&devc->ftdic));
116 } else if ((size_t) ret != size) {
117 sr_err("ftdi_write_data did not complete write.");
118 }
119
120 return ret;
121}
122
123static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
124 struct dev_context *devc)
125{
126 size_t i;
127 uint8_t buf[len + 2];
128 int idx = 0;
129
130 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
131 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
132
133 for (i = 0; i < len; ++i) {
134 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
135 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
136 }
137
138 return sigma_write(buf, idx, devc);
139}
140
141static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
142{
143 return sigma_write_register(reg, &value, 1, devc);
144}
145
146static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
147 struct dev_context *devc)
148{
149 uint8_t buf[3];
150
151 buf[0] = REG_ADDR_LOW | (reg & 0xf);
152 buf[1] = REG_ADDR_HIGH | (reg >> 4);
153 buf[2] = REG_READ_ADDR;
154
155 sigma_write(buf, sizeof(buf), devc);
156
157 return sigma_read(data, len, devc);
158}
159
160static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
161{
162 uint8_t value;
163
164 if (1 != sigma_read_register(reg, &value, 1, devc)) {
165 sr_err("sigma_get_register: 1 byte expected");
166 return 0;
167 }
168
169 return value;
170}
171
172static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
173 struct dev_context *devc)
174{
175 uint8_t buf[] = {
176 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
177
178 REG_READ_ADDR | NEXT_REG,
179 REG_READ_ADDR | NEXT_REG,
180 REG_READ_ADDR | NEXT_REG,
181 REG_READ_ADDR | NEXT_REG,
182 REG_READ_ADDR | NEXT_REG,
183 REG_READ_ADDR | NEXT_REG,
184 };
185 uint8_t result[6];
186
187 sigma_write(buf, sizeof(buf), devc);
188
189 sigma_read(result, sizeof(result), devc);
190
191 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
192 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
193
194 /* Not really sure why this must be done, but according to spec. */
195 if ((--*stoppos & 0x1ff) == 0x1ff)
196 stoppos -= 64;
197
198 if ((*--triggerpos & 0x1ff) == 0x1ff)
199 triggerpos -= 64;
200
201 return 1;
202}
203
204static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
205 uint8_t *data, struct dev_context *devc)
206{
207 size_t i;
208 uint8_t buf[4096];
209 int idx = 0;
210
211 /* Send the startchunk. Index start with 1. */
212 buf[0] = startchunk >> 8;
213 buf[1] = startchunk & 0xff;
214 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
215
216 /* Read the DRAM. */
217 buf[idx++] = REG_DRAM_BLOCK;
218 buf[idx++] = REG_DRAM_WAIT_ACK;
219
220 for (i = 0; i < numchunks; ++i) {
221 /* Alternate bit to copy from DRAM to cache. */
222 if (i != (numchunks - 1))
223 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
224
225 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
226
227 if (i != (numchunks - 1))
228 buf[idx++] = REG_DRAM_WAIT_ACK;
229 }
230
231 sigma_write(buf, idx, devc);
232
233 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
234}
235
236/* Upload trigger look-up tables to Sigma. */
237static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
238{
239 int i;
240 uint8_t tmp[2];
241 uint16_t bit;
242
243 /* Transpose the table and send to Sigma. */
244 for (i = 0; i < 16; ++i) {
245 bit = 1 << i;
246
247 tmp[0] = tmp[1] = 0;
248
249 if (lut->m2d[0] & bit)
250 tmp[0] |= 0x01;
251 if (lut->m2d[1] & bit)
252 tmp[0] |= 0x02;
253 if (lut->m2d[2] & bit)
254 tmp[0] |= 0x04;
255 if (lut->m2d[3] & bit)
256 tmp[0] |= 0x08;
257
258 if (lut->m3 & bit)
259 tmp[0] |= 0x10;
260 if (lut->m3s & bit)
261 tmp[0] |= 0x20;
262 if (lut->m4 & bit)
263 tmp[0] |= 0x40;
264
265 if (lut->m0d[0] & bit)
266 tmp[1] |= 0x01;
267 if (lut->m0d[1] & bit)
268 tmp[1] |= 0x02;
269 if (lut->m0d[2] & bit)
270 tmp[1] |= 0x04;
271 if (lut->m0d[3] & bit)
272 tmp[1] |= 0x08;
273
274 if (lut->m1d[0] & bit)
275 tmp[1] |= 0x10;
276 if (lut->m1d[1] & bit)
277 tmp[1] |= 0x20;
278 if (lut->m1d[2] & bit)
279 tmp[1] |= 0x40;
280 if (lut->m1d[3] & bit)
281 tmp[1] |= 0x80;
282
283 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
284 devc);
285 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
286 }
287
288 /* Send the parameters */
289 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
290 sizeof(lut->params), devc);
291
292 return SR_OK;
293}
294
295static void clear_helper(void *priv)
296{
297 struct dev_context *devc;
298
299 devc = priv;
300
301 ftdi_deinit(&devc->ftdic);
302}
303
304static int dev_clear(void)
305{
306 return std_dev_clear(di, clear_helper);
307}
308
309static int init(struct sr_context *sr_ctx)
310{
311 return std_init(sr_ctx, di, LOG_PREFIX);
312}
313
314static GSList *scan(GSList *options)
315{
316 struct sr_dev_inst *sdi;
317 struct sr_channel *ch;
318 struct drv_context *drvc;
319 struct dev_context *devc;
320 GSList *devices;
321 struct ftdi_device_list *devlist;
322 char serial_txt[10];
323 uint32_t serial;
324 int ret;
325 unsigned int i;
326
327 (void)options;
328
329 drvc = di->priv;
330
331 devices = NULL;
332
333 if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
334 sr_err("%s: devc malloc failed", __func__);
335 return NULL;
336 }
337
338 ftdi_init(&devc->ftdic);
339
340 /* Look for SIGMAs. */
341
342 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
343 USB_VENDOR, USB_PRODUCT)) <= 0) {
344 if (ret < 0)
345 sr_err("ftdi_usb_find_all(): %d", ret);
346 goto free;
347 }
348
349 /* Make sure it's a version 1 or 2 SIGMA. */
350 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
351 serial_txt, sizeof(serial_txt));
352 sscanf(serial_txt, "%x", &serial);
353
354 if (serial < 0xa6010000 || serial > 0xa602ffff) {
355 sr_err("Only SIGMA and SIGMA2 are supported "
356 "in this version of libsigrok.");
357 goto free;
358 }
359
360 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
361
362 devc->cur_samplerate = samplerates[0];
363 devc->period_ps = 0;
364 devc->limit_msec = 0;
365 devc->cur_firmware = -1;
366 devc->num_channels = 0;
367 devc->samples_per_event = 0;
368 devc->capture_ratio = 50;
369 devc->use_triggers = 0;
370
371 /* Register SIGMA device. */
372 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
373 USB_MODEL_NAME, NULL))) {
374 sr_err("%s: sdi was NULL", __func__);
375 goto free;
376 }
377 sdi->driver = di;
378
379 for (i = 0; i < ARRAY_SIZE(channel_names); i++) {
380 ch = sr_channel_new(i, SR_CHANNEL_LOGIC, TRUE,
381 channel_names[i]);
382 if (!ch)
383 return NULL;
384 sdi->channels = g_slist_append(sdi->channels, ch);
385 }
386
387 devices = g_slist_append(devices, sdi);
388 drvc->instances = g_slist_append(drvc->instances, sdi);
389 sdi->priv = devc;
390
391 /* We will open the device again when we need it. */
392 ftdi_list_free(&devlist);
393
394 return devices;
395
396free:
397 ftdi_deinit(&devc->ftdic);
398 g_free(devc);
399 return NULL;
400}
401
402static GSList *dev_list(void)
403{
404 return ((struct drv_context *)(di->priv))->instances;
405}
406
407/*
408 * Configure the FPGA for bitbang mode.
409 * This sequence is documented in section 2. of the ASIX Sigma programming
410 * manual. This sequence is necessary to configure the FPGA in the Sigma
411 * into Bitbang mode, in which it can be programmed with the firmware.
412 */
413static int sigma_fpga_init_bitbang(struct dev_context *devc)
414{
415 uint8_t suicide[] = {
416 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
417 };
418 uint8_t init_array[] = {
419 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
420 0x01, 0x01,
421 };
422 int i, ret, timeout = 10000;
423 uint8_t data;
424
425 /* Section 2. part 1), do the FPGA suicide. */
426 sigma_write(suicide, sizeof(suicide), devc);
427 sigma_write(suicide, sizeof(suicide), devc);
428 sigma_write(suicide, sizeof(suicide), devc);
429 sigma_write(suicide, sizeof(suicide), devc);
430
431 /* Section 2. part 2), do pulse on D1. */
432 sigma_write(init_array, sizeof(init_array), devc);
433 ftdi_usb_purge_buffers(&devc->ftdic);
434
435 /* Wait until the FPGA asserts D6/INIT_B. */
436 for (i = 0; i < timeout; i++) {
437 ret = sigma_read(&data, 1, devc);
438 if (ret < 0)
439 return ret;
440 /* Test if pin D6 got asserted. */
441 if (data & (1 << 5))
442 return 0;
443 /* The D6 was not asserted yet, wait a bit. */
444 usleep(10000);
445 }
446
447 return SR_ERR_TIMEOUT;
448}
449
450/*
451 * Configure the FPGA for logic-analyzer mode.
452 */
453static int sigma_fpga_init_la(struct dev_context *devc)
454{
455 /* Initialize the logic analyzer mode. */
456 uint8_t logic_mode_start[] = {
457 REG_ADDR_LOW | (READ_ID & 0xf),
458 REG_ADDR_HIGH | (READ_ID >> 8),
459 REG_READ_ADDR, /* Read ID register. */
460
461 REG_ADDR_LOW | (WRITE_TEST & 0xf),
462 REG_DATA_LOW | 0x5,
463 REG_DATA_HIGH_WRITE | 0x5,
464 REG_READ_ADDR, /* Read scratch register. */
465
466 REG_DATA_LOW | 0xa,
467 REG_DATA_HIGH_WRITE | 0xa,
468 REG_READ_ADDR, /* Read scratch register. */
469
470 REG_ADDR_LOW | (WRITE_MODE & 0xf),
471 REG_DATA_LOW | 0x0,
472 REG_DATA_HIGH_WRITE | 0x8,
473 };
474
475 uint8_t result[3];
476 int ret;
477
478 /* Initialize the logic analyzer mode. */
479 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
480
481 /* Expect a 3 byte reply since we issued three READ requests. */
482 ret = sigma_read(result, 3, devc);
483 if (ret != 3)
484 goto err;
485
486 if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa)
487 goto err;
488
489 return SR_OK;
490err:
491 sr_err("Configuration failed. Invalid reply received.");
492 return SR_ERR;
493}
494
495/*
496 * Read the firmware from a file and transform it into a series of bitbang
497 * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d
498 * by the caller of this function.
499 */
500static int sigma_fw_2_bitbang(const char *filename,
501 uint8_t **bb_cmd, gsize *bb_cmd_size)
502{
503 GMappedFile *file;
504 GError *error;
505 gsize i, file_size, bb_size;
506 gchar *firmware;
507 uint8_t *bb_stream, *bbs;
508 uint32_t imm;
509 int bit, v;
510 int ret = SR_OK;
511
512 /*
513 * Map the file and make the mapped buffer writable.
514 * NOTE: Using writable=TRUE does _NOT_ mean that file that is mapped
515 * will be modified. It will not be modified until someone uses
516 * g_file_set_contents() on it.
517 */
518 error = NULL;
519 file = g_mapped_file_new(filename, TRUE, &error);
520 g_assert_no_error(error);
521
522 file_size = g_mapped_file_get_length(file);
523 firmware = g_mapped_file_get_contents(file);
524 g_assert(firmware);
525
526 /* Weird magic transformation below, I have no idea what it does. */
527 imm = 0x3f6df2ab;
528 for (i = 0; i < file_size; i++) {
529 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
530 firmware[i] ^= imm & 0xff;
531 }
532
533 /*
534 * Now that the firmware is "transformed", we will transcribe the
535 * firmware blob into a sequence of toggles of the Dx wires. This
536 * sequence will be fed directly into the Sigma, which must be in
537 * the FPGA bitbang programming mode.
538 */
539
540 /* Each bit of firmware is transcribed as two toggles of Dx wires. */
541 bb_size = file_size * 8 * 2;
542 bb_stream = (uint8_t *)g_try_malloc(bb_size);
543 if (!bb_stream) {
544 sr_err("%s: Failed to allocate bitbang stream", __func__);
545 ret = SR_ERR_MALLOC;
546 goto exit;
547 }
548
549 bbs = bb_stream;
550 for (i = 0; i < file_size; i++) {
551 for (bit = 7; bit >= 0; bit--) {
552 v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00;
553 *bbs++ = v | 0x01;
554 *bbs++ = v;
555 }
556 }
557
558 /* The transformation completed successfully, return the result. */
559 *bb_cmd = bb_stream;
560 *bb_cmd_size = bb_size;
561
562exit:
563 g_mapped_file_unref(file);
564 return ret;
565}
566
567static int upload_firmware(int firmware_idx, struct dev_context *devc)
568{
569 int ret;
570 unsigned char *buf;
571 unsigned char pins;
572 size_t buf_size;
573 const char *firmware = sigma_firmware_files[firmware_idx];
574 struct ftdi_context *ftdic = &devc->ftdic;
575
576 /* Make sure it's an ASIX SIGMA. */
577 ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT,
578 USB_DESCRIPTION, NULL);
579 if (ret < 0) {
580 sr_err("ftdi_usb_open failed: %s",
581 ftdi_get_error_string(ftdic));
582 return 0;
583 }
584
585 ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG);
586 if (ret < 0) {
587 sr_err("ftdi_set_bitmode failed: %s",
588 ftdi_get_error_string(ftdic));
589 return 0;
590 }
591
592 /* Four times the speed of sigmalogan - Works well. */
593 ret = ftdi_set_baudrate(ftdic, 750000);
594 if (ret < 0) {
595 sr_err("ftdi_set_baudrate failed: %s",
596 ftdi_get_error_string(ftdic));
597 return 0;
598 }
599
600 /* Initialize the FPGA for firmware upload. */
601 ret = sigma_fpga_init_bitbang(devc);
602 if (ret)
603 return ret;
604
605 /* Prepare firmware. */
606 ret = sigma_fw_2_bitbang(firmware, &buf, &buf_size);
607 if (ret != SR_OK) {
608 sr_err("An error occured while reading the firmware: %s",
609 firmware);
610 return ret;
611 }
612
613 /* Upload firmare. */
614 sr_info("Uploading firmware file '%s'.", firmware);
615 sigma_write(buf, buf_size, devc);
616
617 g_free(buf);
618
619 ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET);
620 if (ret < 0) {
621 sr_err("ftdi_set_bitmode failed: %s",
622 ftdi_get_error_string(ftdic));
623 return SR_ERR;
624 }
625
626 ftdi_usb_purge_buffers(ftdic);
627
628 /* Discard garbage. */
629 while (sigma_read(&pins, 1, devc) == 1)
630 ;
631
632 /* Initialize the FPGA for logic-analyzer mode. */
633 ret = sigma_fpga_init_la(devc);
634 if (ret != SR_OK)
635 return ret;
636
637 devc->cur_firmware = firmware_idx;
638
639 sr_info("Firmware uploaded.");
640
641 return SR_OK;
642}
643
644static int dev_open(struct sr_dev_inst *sdi)
645{
646 struct dev_context *devc;
647 int ret;
648
649 devc = sdi->priv;
650
651 /* Make sure it's an ASIX SIGMA. */
652 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
653 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
654
655 sr_err("ftdi_usb_open failed: %s",
656 ftdi_get_error_string(&devc->ftdic));
657
658 return 0;
659 }
660
661 sdi->status = SR_ST_ACTIVE;
662
663 return SR_OK;
664}
665
666static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
667{
668 struct dev_context *devc;
669 unsigned int i;
670 int ret;
671
672 devc = sdi->priv;
673 ret = SR_OK;
674
675 for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
676 if (samplerates[i] == samplerate)
677 break;
678 }
679 if (samplerates[i] == 0)
680 return SR_ERR_SAMPLERATE;
681
682 if (samplerate <= SR_MHZ(50)) {
683 ret = upload_firmware(0, devc);
684 devc->num_channels = 16;
685 } else if (samplerate == SR_MHZ(100)) {
686 ret = upload_firmware(1, devc);
687 devc->num_channels = 8;
688 } else if (samplerate == SR_MHZ(200)) {
689 ret = upload_firmware(2, devc);
690 devc->num_channels = 4;
691 }
692
693 if (ret == SR_OK) {
694 devc->cur_samplerate = samplerate;
695 devc->period_ps = 1000000000000ULL / samplerate;
696 devc->samples_per_event = 16 / devc->num_channels;
697 devc->state.state = SIGMA_IDLE;
698 }
699
700 return ret;
701}
702
703/*
704 * In 100 and 200 MHz mode, only a single pin rising/falling can be
705 * set as trigger. In other modes, two rising/falling triggers can be set,
706 * in addition to value/mask trigger for any number of channels.
707 *
708 * The Sigma supports complex triggers using boolean expressions, but this
709 * has not been implemented yet.
710 */
711static int configure_channels(const struct sr_dev_inst *sdi)
712{
713 struct dev_context *devc = sdi->priv;
714 const struct sr_channel *ch;
715 const GSList *l;
716 int trigger_set = 0;
717 int channelbit;
718
719 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
720
721 for (l = sdi->channels; l; l = l->next) {
722 ch = (struct sr_channel *)l->data;
723 channelbit = 1 << (ch->index);
724
725 if (!ch->enabled || !ch->trigger)
726 continue;
727
728 if (devc->cur_samplerate >= SR_MHZ(100)) {
729 /* Fast trigger support. */
730 if (trigger_set) {
731 sr_err("Only a single pin trigger in 100 and "
732 "200MHz mode is supported.");
733 return SR_ERR;
734 }
735 if (ch->trigger[0] == 'f')
736 devc->trigger.fallingmask |= channelbit;
737 else if (ch->trigger[0] == 'r')
738 devc->trigger.risingmask |= channelbit;
739 else {
740 sr_err("Only rising/falling trigger in 100 "
741 "and 200MHz mode is supported.");
742 return SR_ERR;
743 }
744
745 ++trigger_set;
746 } else {
747 /* Simple trigger support (event). */
748 if (ch->trigger[0] == '1') {
749 devc->trigger.simplevalue |= channelbit;
750 devc->trigger.simplemask |= channelbit;
751 }
752 else if (ch->trigger[0] == '0') {
753 devc->trigger.simplevalue &= ~channelbit;
754 devc->trigger.simplemask |= channelbit;
755 }
756 else if (ch->trigger[0] == 'f') {
757 devc->trigger.fallingmask |= channelbit;
758 ++trigger_set;
759 }
760 else if (ch->trigger[0] == 'r') {
761 devc->trigger.risingmask |= channelbit;
762 ++trigger_set;
763 }
764
765 /*
766 * Actually, Sigma supports 2 rising/falling triggers,
767 * but they are ORed and the current trigger syntax
768 * does not permit ORed triggers.
769 */
770 if (trigger_set > 1) {
771 sr_err("Only 1 rising/falling trigger "
772 "is supported.");
773 return SR_ERR;
774 }
775 }
776
777 if (trigger_set)
778 devc->use_triggers = 1;
779 }
780
781 return SR_OK;
782}
783
784static int dev_close(struct sr_dev_inst *sdi)
785{
786 struct dev_context *devc;
787
788 devc = sdi->priv;
789
790 /* TODO */
791 if (sdi->status == SR_ST_ACTIVE)
792 ftdi_usb_close(&devc->ftdic);
793
794 sdi->status = SR_ST_INACTIVE;
795
796 return SR_OK;
797}
798
799static int cleanup(void)
800{
801 return dev_clear();
802}
803
804static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi,
805 const struct sr_channel_group *cg)
806{
807 struct dev_context *devc;
808
809 (void)cg;
810
811 if (!sdi)
812 return SR_ERR;
813 devc = sdi->priv;
814
815 switch (id) {
816 case SR_CONF_SAMPLERATE:
817 *data = g_variant_new_uint64(devc->cur_samplerate);
818 break;
819 case SR_CONF_LIMIT_MSEC:
820 *data = g_variant_new_uint64(devc->limit_msec);
821 break;
822 case SR_CONF_CAPTURE_RATIO:
823 *data = g_variant_new_uint64(devc->capture_ratio);
824 break;
825 default:
826 return SR_ERR_NA;
827 }
828
829 return SR_OK;
830}
831
832static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi,
833 const struct sr_channel_group *cg)
834{
835 struct dev_context *devc;
836 uint64_t tmp;
837 int ret;
838
839 (void)cg;
840
841 if (sdi->status != SR_ST_ACTIVE)
842 return SR_ERR_DEV_CLOSED;
843
844 devc = sdi->priv;
845
846 ret = SR_OK;
847 switch (id) {
848 case SR_CONF_SAMPLERATE:
849 ret = set_samplerate(sdi, g_variant_get_uint64(data));
850 break;
851 case SR_CONF_LIMIT_MSEC:
852 tmp = g_variant_get_uint64(data);
853 if (tmp > 0)
854 devc->limit_msec = g_variant_get_uint64(data);
855 else
856 ret = SR_ERR;
857 break;
858 case SR_CONF_LIMIT_SAMPLES:
859 tmp = g_variant_get_uint64(data);
860 devc->limit_msec = tmp * 1000 / devc->cur_samplerate;
861 break;
862 case SR_CONF_CAPTURE_RATIO:
863 tmp = g_variant_get_uint64(data);
864 if (tmp <= 100)
865 devc->capture_ratio = tmp;
866 else
867 ret = SR_ERR;
868 break;
869 default:
870 ret = SR_ERR_NA;
871 }
872
873 return ret;
874}
875
876static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi,
877 const struct sr_channel_group *cg)
878{
879 GVariant *gvar;
880 GVariantBuilder gvb;
881
882 (void)sdi;
883 (void)cg;
884
885 switch (key) {
886 case SR_CONF_DEVICE_OPTIONS:
887 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
888 hwcaps, ARRAY_SIZE(hwcaps), sizeof(int32_t));
889 break;
890 case SR_CONF_SAMPLERATE:
891 g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
892 gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
893 ARRAY_SIZE(samplerates), sizeof(uint64_t));
894 g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
895 *data = g_variant_builder_end(&gvb);
896 break;
897 case SR_CONF_TRIGGER_TYPE:
898 *data = g_variant_new_string(TRIGGER_TYPE);
899 break;
900 default:
901 return SR_ERR_NA;
902 }
903
904 return SR_OK;
905}
906
907/* Software trigger to determine exact trigger position. */
908static int get_trigger_offset(uint8_t *samples, uint16_t last_sample,
909 struct sigma_trigger *t)
910{
911 int i;
912 uint16_t sample = 0;
913
914 for (i = 0; i < 8; ++i) {
915 if (i > 0)
916 last_sample = sample;
917 sample = samples[2 * i] | (samples[2 * i + 1] << 8);
918
919 /* Simple triggers. */
920 if ((sample & t->simplemask) != t->simplevalue)
921 continue;
922
923 /* Rising edge. */
924 if (((last_sample & t->risingmask) != 0) ||
925 ((sample & t->risingmask) != t->risingmask))
926 continue;
927
928 /* Falling edge. */
929 if ((last_sample & t->fallingmask) != t->fallingmask ||
930 (sample & t->fallingmask) != 0)
931 continue;
932
933 break;
934 }
935
936 /* If we did not match, return original trigger pos. */
937 return i & 0x7;
938}
939
940
941/*
942 * Return the timestamp of "DRAM cluster".
943 */
944static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster)
945{
946 return (cluster->timestamp_hi << 8) | cluster->timestamp_lo;
947}
948
949static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster,
950 unsigned int events_in_cluster,
951 unsigned int triggered,
952 struct sr_dev_inst *sdi)
953{
954 struct dev_context *devc = sdi->priv;
955 struct sigma_state *ss = &devc->state;
956 struct sr_datafeed_packet packet;
957 struct sr_datafeed_logic logic;
958 uint16_t tsdiff, ts;
959 uint8_t samples[2048];
960 unsigned int i;
961
962 ts = sigma_dram_cluster_ts(dram_cluster);
963 tsdiff = ts - ss->lastts;
964 ss->lastts = ts;
965
966 packet.type = SR_DF_LOGIC;
967 packet.payload = &logic;
968 logic.unitsize = 2;
969 logic.data = samples;
970
971 /*
972 * First of all, send Sigrok a copy of the last sample from
973 * previous cluster as many times as needed to make up for
974 * the differential characteristics of data we get from the
975 * Sigma. Sigrok needs one sample of data per period.
976 *
977 * One DRAM cluster contains a timestamp and seven samples,
978 * the units of timestamp are "devc->period_ps" , the first
979 * sample in the cluster happens at the time of the timestamp
980 * and the remaining samples happen at timestamp +1...+6 .
981 */
982 for (ts = 0; ts < tsdiff - (EVENTS_PER_CLUSTER - 1); ts++) {
983 i = ts % 1024;
984 samples[2 * i + 0] = ss->lastsample & 0xff;
985 samples[2 * i + 1] = ss->lastsample >> 8;
986
987 /*
988 * If we have 1024 samples ready or we're at the
989 * end of submitting the padding samples, submit
990 * the packet to Sigrok.
991 */
992 if ((i == 1023) || (ts == (tsdiff - EVENTS_PER_CLUSTER))) {
993 logic.length = (i + 1) * logic.unitsize;
994 sr_session_send(devc->cb_data, &packet);
995 }
996 }
997
998 /*
999 * Parse the samples in current cluster and prepare them
1000 * to be submitted to Sigrok.
1001 */
1002 for (i = 0; i < events_in_cluster; i++) {
1003 samples[2 * i + 1] = dram_cluster->samples[i].sample_lo;
1004 samples[2 * i + 0] = dram_cluster->samples[i].sample_hi;
1005 }
1006
1007 /* Send data up to trigger point (if triggered). */
1008 int trigger_offset = 0;
1009 if (triggered) {
1010 /*
1011 * Trigger is not always accurate to sample because of
1012 * pipeline delay. However, it always triggers before
1013 * the actual event. We therefore look at the next
1014 * samples to pinpoint the exact position of the trigger.
1015 */
1016 trigger_offset = get_trigger_offset(samples,
1017 ss->lastsample, &devc->trigger);
1018
1019 if (trigger_offset > 0) {
1020 packet.type = SR_DF_LOGIC;
1021 logic.length = trigger_offset * logic.unitsize;
1022 sr_session_send(devc->cb_data, &packet);
1023 events_in_cluster -= trigger_offset;
1024 }
1025
1026 /* Only send trigger if explicitly enabled. */
1027 if (devc->use_triggers) {
1028 packet.type = SR_DF_TRIGGER;
1029 sr_session_send(devc->cb_data, &packet);
1030 }
1031 }
1032
1033 if (events_in_cluster > 0) {
1034 packet.type = SR_DF_LOGIC;
1035 logic.length = events_in_cluster * logic.unitsize;
1036 logic.data = samples + (trigger_offset * logic.unitsize);
1037 sr_session_send(devc->cb_data, &packet);
1038 }
1039
1040 ss->lastsample =
1041 samples[2 * (events_in_cluster - 1) + 0] |
1042 (samples[2 * (events_in_cluster - 1) + 1] << 8);
1043
1044}
1045
1046/*
1047 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
1048 * Each event is 20ns apart, and can contain multiple samples.
1049 *
1050 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
1051 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
1052 * For 50 MHz and below, events contain one sample for each channel,
1053 * spread 20 ns apart.
1054 */
1055static int decode_chunk_ts(struct sigma_dram_line *dram_line,
1056 uint16_t events_in_line,
1057 uint32_t trigger_event,
1058 void *cb_data)
1059{
1060 struct sigma_dram_cluster *dram_cluster;
1061 struct sr_dev_inst *sdi = cb_data;
1062 struct dev_context *devc = sdi->priv;
1063 unsigned int clusters_in_line =
1064 (events_in_line + (EVENTS_PER_CLUSTER - 1)) / EVENTS_PER_CLUSTER;
1065 unsigned int events_in_cluster;
1066 unsigned int i;
1067 uint32_t trigger_cluster = ~0, triggered = 0;
1068
1069 /* Check if trigger is in this chunk. */
1070 if (trigger_event < (64 * 7)) {
1071 if (devc->cur_samplerate <= SR_MHZ(50)) {
1072 trigger_event -= MIN(EVENTS_PER_CLUSTER - 1,
1073 trigger_event);
1074 }
1075
1076 /* Find in which cluster the trigger occured. */
1077 trigger_cluster = trigger_event / EVENTS_PER_CLUSTER;
1078 }
1079
1080 /* For each full DRAM cluster. */
1081 for (i = 0; i < clusters_in_line; i++) {
1082 dram_cluster = &dram_line->cluster[i];
1083
1084 /* The last cluster might not be full. */
1085 if ((i == clusters_in_line - 1) &&
1086 (events_in_line % EVENTS_PER_CLUSTER)) {
1087 events_in_cluster = events_in_line % EVENTS_PER_CLUSTER;
1088 } else {
1089 events_in_cluster = EVENTS_PER_CLUSTER;
1090 }
1091
1092 triggered = (i == trigger_cluster);
1093 sigma_decode_dram_cluster(dram_cluster, events_in_cluster,
1094 triggered, sdi);
1095 }
1096
1097 return SR_OK;
1098}
1099
1100static int download_capture(struct sr_dev_inst *sdi)
1101{
1102 struct dev_context *devc = sdi->priv;
1103 const int chunks_per_read = 32;
1104 struct sigma_dram_line *dram_line;
1105 int bufsz;
1106 uint32_t stoppos, triggerpos;
1107 struct sr_datafeed_packet packet;
1108 uint8_t modestatus;
1109
1110 uint32_t i;
1111 uint32_t dl_lines_total, dl_lines_curr, dl_lines_done;
1112 uint32_t dl_events_in_line = 64 * 7;
1113 uint32_t trg_line = ~0, trg_event = ~0;
1114
1115 dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line));
1116 if (!dram_line)
1117 return FALSE;
1118
1119 sr_info("Downloading sample data.");
1120
1121 /* Stop acquisition. */
1122 sigma_set_register(WRITE_MODE, 0x11, devc);
1123
1124 /* Set SDRAM Read Enable. */
1125 sigma_set_register(WRITE_MODE, 0x02, devc);
1126
1127 /* Get the current position. */
1128 sigma_read_pos(&stoppos, &triggerpos, devc);
1129
1130 /* Check if trigger has fired. */
1131 modestatus = sigma_get_register(READ_MODE, devc);
1132 if (modestatus & 0x20) {
1133 trg_line = triggerpos >> 9;
1134 trg_event = triggerpos & 0x1ff;
1135 }
1136
1137 /*
1138 * Determine how many 1024b "DRAM lines" do we need to read from the
1139 * Sigma so we have a complete set of samples. Note that the last
1140 * line can be only partial, containing less than 64 clusters.
1141 */
1142 dl_lines_total = (stoppos >> 9) + 1;
1143
1144 dl_lines_done = 0;
1145
1146 while (dl_lines_total > dl_lines_done) {
1147 /* We can download only up-to 32 DRAM lines in one go! */
1148 dl_lines_curr = MIN(chunks_per_read, dl_lines_total);
1149
1150 bufsz = sigma_read_dram(dl_lines_done, dl_lines_curr,
1151 (uint8_t *)dram_line, devc);
1152 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1153 (void)bufsz;
1154
1155 /* This is the first DRAM line, so find the initial timestamp. */
1156 if (dl_lines_done == 0) {
1157 devc->state.lastts =
1158 sigma_dram_cluster_ts(&dram_line[0].cluster[0]);
1159 devc->state.lastsample = 0;
1160 }
1161
1162 for (i = 0; i < dl_lines_curr; i++) {
1163 uint32_t trigger_event = ~0;
1164 /* The last "DRAM line" can be only partially full. */
1165 if (dl_lines_done + i == dl_lines_total - 1)
1166 dl_events_in_line = stoppos & 0x1ff;
1167
1168 /* Test if the trigger happened on this line. */
1169 if (dl_lines_done + i == trg_line)
1170 trigger_event = trg_event;
1171
1172 decode_chunk_ts(dram_line + i, dl_events_in_line,
1173 trigger_event, sdi);
1174 }
1175
1176 dl_lines_done += dl_lines_curr;
1177 }
1178
1179 /* All done. */
1180 packet.type = SR_DF_END;
1181 sr_session_send(sdi, &packet);
1182
1183 dev_acquisition_stop(sdi, sdi);
1184
1185 g_free(dram_line);
1186
1187 return TRUE;
1188}
1189
1190/*
1191 * Handle the Sigma when in CAPTURE mode. This function checks:
1192 * - Sampling time ended
1193 * - DRAM capacity overflow
1194 * This function triggers download of the samples from Sigma
1195 * in case either of the above conditions is true.
1196 */
1197static int sigma_capture_mode(struct sr_dev_inst *sdi)
1198{
1199 struct dev_context *devc = sdi->priv;
1200
1201 uint64_t running_msec;
1202 struct timeval tv;
1203
1204 uint32_t stoppos, triggerpos;
1205
1206 /* Check if the selected sampling duration passed. */
1207 gettimeofday(&tv, 0);
1208 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1209 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1210 if (running_msec >= devc->limit_msec)
1211 return download_capture(sdi);
1212
1213 /* Get the position in DRAM to which the FPGA is writing now. */
1214 sigma_read_pos(&stoppos, &triggerpos, devc);
1215 /* Test if DRAM is full and if so, download the data. */
1216 if ((stoppos >> 9) == 32767)
1217 return download_capture(sdi);
1218
1219 return TRUE;
1220}
1221
1222static int receive_data(int fd, int revents, void *cb_data)
1223{
1224 struct sr_dev_inst *sdi;
1225 struct dev_context *devc;
1226
1227 (void)fd;
1228 (void)revents;
1229
1230 sdi = cb_data;
1231 devc = sdi->priv;
1232
1233 if (devc->state.state == SIGMA_IDLE)
1234 return TRUE;
1235
1236 if (devc->state.state == SIGMA_CAPTURE)
1237 return sigma_capture_mode(sdi);
1238
1239 return TRUE;
1240}
1241
1242/* Build a LUT entry used by the trigger functions. */
1243static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1244{
1245 int i, j, k, bit;
1246
1247 /* For each quad channel. */
1248 for (i = 0; i < 4; ++i) {
1249 entry[i] = 0xffff;
1250
1251 /* For each bit in LUT. */
1252 for (j = 0; j < 16; ++j)
1253
1254 /* For each channel in quad. */
1255 for (k = 0; k < 4; ++k) {
1256 bit = 1 << (i * 4 + k);
1257
1258 /* Set bit in entry */
1259 if ((mask & bit) &&
1260 ((!(value & bit)) !=
1261 (!(j & (1 << k)))))
1262 entry[i] &= ~(1 << j);
1263 }
1264 }
1265}
1266
1267/* Add a logical function to LUT mask. */
1268static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1269 int index, int neg, uint16_t *mask)
1270{
1271 int i, j;
1272 int x[2][2], tmp, a, b, aset, bset, rset;
1273
1274 memset(x, 0, 4 * sizeof(int));
1275
1276 /* Trigger detect condition. */
1277 switch (oper) {
1278 case OP_LEVEL:
1279 x[0][1] = 1;
1280 x[1][1] = 1;
1281 break;
1282 case OP_NOT:
1283 x[0][0] = 1;
1284 x[1][0] = 1;
1285 break;
1286 case OP_RISE:
1287 x[0][1] = 1;
1288 break;
1289 case OP_FALL:
1290 x[1][0] = 1;
1291 break;
1292 case OP_RISEFALL:
1293 x[0][1] = 1;
1294 x[1][0] = 1;
1295 break;
1296 case OP_NOTRISE:
1297 x[1][1] = 1;
1298 x[0][0] = 1;
1299 x[1][0] = 1;
1300 break;
1301 case OP_NOTFALL:
1302 x[1][1] = 1;
1303 x[0][0] = 1;
1304 x[0][1] = 1;
1305 break;
1306 case OP_NOTRISEFALL:
1307 x[1][1] = 1;
1308 x[0][0] = 1;
1309 break;
1310 }
1311
1312 /* Transpose if neg is set. */
1313 if (neg) {
1314 for (i = 0; i < 2; ++i) {
1315 for (j = 0; j < 2; ++j) {
1316 tmp = x[i][j];
1317 x[i][j] = x[1-i][1-j];
1318 x[1-i][1-j] = tmp;
1319 }
1320 }
1321 }
1322
1323 /* Update mask with function. */
1324 for (i = 0; i < 16; ++i) {
1325 a = (i >> (2 * index + 0)) & 1;
1326 b = (i >> (2 * index + 1)) & 1;
1327
1328 aset = (*mask >> i) & 1;
1329 bset = x[b][a];
1330
1331 if (func == FUNC_AND || func == FUNC_NAND)
1332 rset = aset & bset;
1333 else if (func == FUNC_OR || func == FUNC_NOR)
1334 rset = aset | bset;
1335 else if (func == FUNC_XOR || func == FUNC_NXOR)
1336 rset = aset ^ bset;
1337
1338 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1339 rset = !rset;
1340
1341 *mask &= ~(1 << i);
1342
1343 if (rset)
1344 *mask |= 1 << i;
1345 }
1346}
1347
1348/*
1349 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1350 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1351 * set at any time, but a full mask and value can be set (0/1).
1352 */
1353static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1354{
1355 int i,j;
1356 uint16_t masks[2] = { 0, 0 };
1357
1358 memset(lut, 0, sizeof(struct triggerlut));
1359
1360 /* Contant for simple triggers. */
1361 lut->m4 = 0xa000;
1362
1363 /* Value/mask trigger support. */
1364 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1365 lut->m2d);
1366
1367 /* Rise/fall trigger support. */
1368 for (i = 0, j = 0; i < 16; ++i) {
1369 if (devc->trigger.risingmask & (1 << i) ||
1370 devc->trigger.fallingmask & (1 << i))
1371 masks[j++] = 1 << i;
1372 }
1373
1374 build_lut_entry(masks[0], masks[0], lut->m0d);
1375 build_lut_entry(masks[1], masks[1], lut->m1d);
1376
1377 /* Add glue logic */
1378 if (masks[0] || masks[1]) {
1379 /* Transition trigger. */
1380 if (masks[0] & devc->trigger.risingmask)
1381 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1382 if (masks[0] & devc->trigger.fallingmask)
1383 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1384 if (masks[1] & devc->trigger.risingmask)
1385 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1386 if (masks[1] & devc->trigger.fallingmask)
1387 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1388 } else {
1389 /* Only value/mask trigger. */
1390 lut->m3 = 0xffff;
1391 }
1392
1393 /* Triggertype: event. */
1394 lut->params.selres = 3;
1395
1396 return SR_OK;
1397}
1398
1399static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
1400{
1401 struct dev_context *devc;
1402 struct clockselect_50 clockselect;
1403 int frac, triggerpin, ret;
1404 uint8_t triggerselect = 0;
1405 struct triggerinout triggerinout_conf;
1406 struct triggerlut lut;
1407
1408 if (sdi->status != SR_ST_ACTIVE)
1409 return SR_ERR_DEV_CLOSED;
1410
1411 devc = sdi->priv;
1412
1413 if (configure_channels(sdi) != SR_OK) {
1414 sr_err("Failed to configure channels.");
1415 return SR_ERR;
1416 }
1417
1418 /* If the samplerate has not been set, default to 200 kHz. */
1419 if (devc->cur_firmware == -1) {
1420 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1421 return ret;
1422 }
1423
1424 /* Enter trigger programming mode. */
1425 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1426
1427 /* 100 and 200 MHz mode. */
1428 if (devc->cur_samplerate >= SR_MHZ(100)) {
1429 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1430
1431 /* Find which pin to trigger on from mask. */
1432 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1433 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1434 (1 << triggerpin))
1435 break;
1436
1437 /* Set trigger pin and light LED on trigger. */
1438 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1439
1440 /* Default rising edge. */
1441 if (devc->trigger.fallingmask)
1442 triggerselect |= 1 << 3;
1443
1444 /* All other modes. */
1445 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1446 build_basic_trigger(&lut, devc);
1447
1448 sigma_write_trigger_lut(&lut, devc);
1449
1450 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1451 }
1452
1453 /* Setup trigger in and out pins to default values. */
1454 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1455 triggerinout_conf.trgout_bytrigger = 1;
1456 triggerinout_conf.trgout_enable = 1;
1457
1458 sigma_write_register(WRITE_TRIGGER_OPTION,
1459 (uint8_t *) &triggerinout_conf,
1460 sizeof(struct triggerinout), devc);
1461
1462 /* Go back to normal mode. */
1463 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1464
1465 /* Set clock select register. */
1466 if (devc->cur_samplerate == SR_MHZ(200))
1467 /* Enable 4 channels. */
1468 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1469 else if (devc->cur_samplerate == SR_MHZ(100))
1470 /* Enable 8 channels. */
1471 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1472 else {
1473 /*
1474 * 50 MHz mode (or fraction thereof). Any fraction down to
1475 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1476 */
1477 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1478
1479 clockselect.async = 0;
1480 clockselect.fraction = frac;
1481 clockselect.disabled_channels = 0;
1482
1483 sigma_write_register(WRITE_CLOCK_SELECT,
1484 (uint8_t *) &clockselect,
1485 sizeof(clockselect), devc);
1486 }
1487
1488 /* Setup maximum post trigger time. */
1489 sigma_set_register(WRITE_POST_TRIGGER,
1490 (devc->capture_ratio * 255) / 100, devc);
1491
1492 /* Start acqusition. */
1493 gettimeofday(&devc->start_tv, 0);
1494 sigma_set_register(WRITE_MODE, 0x0d, devc);
1495
1496 devc->cb_data = cb_data;
1497
1498 /* Send header packet to the session bus. */
1499 std_session_send_df_header(cb_data, LOG_PREFIX);
1500
1501 /* Add capture source. */
1502 sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
1503
1504 devc->state.state = SIGMA_CAPTURE;
1505
1506 return SR_OK;
1507}
1508
1509static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1510{
1511 struct dev_context *devc;
1512
1513 (void)cb_data;
1514
1515 devc = sdi->priv;
1516 devc->state.state = SIGMA_IDLE;
1517
1518 sr_source_remove(0);
1519
1520 return SR_OK;
1521}
1522
1523SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1524 .name = "asix-sigma",
1525 .longname = "ASIX SIGMA/SIGMA2",
1526 .api_version = 1,
1527 .init = init,
1528 .cleanup = cleanup,
1529 .scan = scan,
1530 .dev_list = dev_list,
1531 .dev_clear = dev_clear,
1532 .config_get = config_get,
1533 .config_set = config_set,
1534 .config_list = config_list,
1535 .dev_open = dev_open,
1536 .dev_close = dev_close,
1537 .dev_acquisition_start = dev_acquisition_start,
1538 .dev_acquisition_stop = dev_acquisition_stop,
1539 .priv = NULL,
1540};
Hardware access and backend lib