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1/*
2 * This file is part of the sigrok project.
3 *
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22/*
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
24 */
25
26#include <glib.h>
27#include <glib/gstdio.h>
28#include <ftdi.h>
29#include <string.h>
30#include "libsigrok.h"
31#include "libsigrok-internal.h"
32#include "asix-sigma.h"
33
34#define USB_VENDOR 0xa600
35#define USB_PRODUCT 0xa000
36#define USB_DESCRIPTION "ASIX SIGMA"
37#define USB_VENDOR_NAME "ASIX"
38#define USB_MODEL_NAME "SIGMA"
39#define USB_MODEL_VERSION ""
40#define TRIGGER_TYPES "rf10"
41#define NUM_PROBES 16
42
43SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
44static struct sr_dev_driver *adi = &asix_sigma_driver_info;
45
46static const uint64_t supported_samplerates[] = {
47 SR_KHZ(200),
48 SR_KHZ(250),
49 SR_KHZ(500),
50 SR_MHZ(1),
51 SR_MHZ(5),
52 SR_MHZ(10),
53 SR_MHZ(25),
54 SR_MHZ(50),
55 SR_MHZ(100),
56 SR_MHZ(200),
57 0,
58};
59
60/*
61 * Probe numbers seem to go from 1-16, according to this image:
62 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
63 * (the cable has two additional GND pins, and a TI and TO pin)
64 */
65static const char *probe_names[NUM_PROBES + 1] = {
66 "1",
67 "2",
68 "3",
69 "4",
70 "5",
71 "6",
72 "7",
73 "8",
74 "9",
75 "10",
76 "11",
77 "12",
78 "13",
79 "14",
80 "15",
81 "16",
82 NULL,
83};
84
85static const struct sr_samplerates samplerates = {
86 0,
87 0,
88 0,
89 supported_samplerates,
90};
91
92static const int hwcaps[] = {
93 SR_HWCAP_LOGIC_ANALYZER,
94 SR_HWCAP_SAMPLERATE,
95 SR_HWCAP_CAPTURE_RATIO,
96 SR_HWCAP_PROBECONFIG,
97
98 SR_HWCAP_LIMIT_MSEC,
99 0,
100};
101
102/* Force the FPGA to reboot. */
103static uint8_t suicide[] = {
104 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
105};
106
107/* Prepare to upload firmware (FPGA specific). */
108static uint8_t init[] = {
109 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
110};
111
112/* Initialize the logic analyzer mode. */
113static uint8_t logic_mode_start[] = {
114 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
115 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
116};
117
118static const char *firmware_files[] = {
119 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
120 "asix-sigma-100.fw", /* 100 MHz */
121 "asix-sigma-200.fw", /* 200 MHz */
122 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
123 "asix-sigma-phasor.fw", /* Frequency counter */
124};
125
126static int hw_dev_acquisition_stop(int dev_index, void *cb_data);
127
128static int sigma_read(void *buf, size_t size, struct context *ctx)
129{
130 int ret;
131
132 ret = ftdi_read_data(&ctx->ftdic, (unsigned char *)buf, size);
133 if (ret < 0) {
134 sr_err("sigma: ftdi_read_data failed: %s",
135 ftdi_get_error_string(&ctx->ftdic));
136 }
137
138 return ret;
139}
140
141static int sigma_write(void *buf, size_t size, struct context *ctx)
142{
143 int ret;
144
145 ret = ftdi_write_data(&ctx->ftdic, (unsigned char *)buf, size);
146 if (ret < 0) {
147 sr_err("sigma: ftdi_write_data failed: %s",
148 ftdi_get_error_string(&ctx->ftdic));
149 } else if ((size_t) ret != size) {
150 sr_err("sigma: ftdi_write_data did not complete write.");
151 }
152
153 return ret;
154}
155
156static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
157 struct context *ctx)
158{
159 size_t i;
160 uint8_t buf[len + 2];
161 int idx = 0;
162
163 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
164 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
165
166 for (i = 0; i < len; ++i) {
167 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
168 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
169 }
170
171 return sigma_write(buf, idx, ctx);
172}
173
174static int sigma_set_register(uint8_t reg, uint8_t value, struct context *ctx)
175{
176 return sigma_write_register(reg, &value, 1, ctx);
177}
178
179static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
180 struct context *ctx)
181{
182 uint8_t buf[3];
183
184 buf[0] = REG_ADDR_LOW | (reg & 0xf);
185 buf[1] = REG_ADDR_HIGH | (reg >> 4);
186 buf[2] = REG_READ_ADDR;
187
188 sigma_write(buf, sizeof(buf), ctx);
189
190 return sigma_read(data, len, ctx);
191}
192
193static uint8_t sigma_get_register(uint8_t reg, struct context *ctx)
194{
195 uint8_t value;
196
197 if (1 != sigma_read_register(reg, &value, 1, ctx)) {
198 sr_err("sigma: sigma_get_register: 1 byte expected");
199 return 0;
200 }
201
202 return value;
203}
204
205static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
206 struct context *ctx)
207{
208 uint8_t buf[] = {
209 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
210
211 REG_READ_ADDR | NEXT_REG,
212 REG_READ_ADDR | NEXT_REG,
213 REG_READ_ADDR | NEXT_REG,
214 REG_READ_ADDR | NEXT_REG,
215 REG_READ_ADDR | NEXT_REG,
216 REG_READ_ADDR | NEXT_REG,
217 };
218 uint8_t result[6];
219
220 sigma_write(buf, sizeof(buf), ctx);
221
222 sigma_read(result, sizeof(result), ctx);
223
224 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
225 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
226
227 /* Not really sure why this must be done, but according to spec. */
228 if ((--*stoppos & 0x1ff) == 0x1ff)
229 stoppos -= 64;
230
231 if ((*--triggerpos & 0x1ff) == 0x1ff)
232 triggerpos -= 64;
233
234 return 1;
235}
236
237static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
238 uint8_t *data, struct context *ctx)
239{
240 size_t i;
241 uint8_t buf[4096];
242 int idx = 0;
243
244 /* Send the startchunk. Index start with 1. */
245 buf[0] = startchunk >> 8;
246 buf[1] = startchunk & 0xff;
247 sigma_write_register(WRITE_MEMROW, buf, 2, ctx);
248
249 /* Read the DRAM. */
250 buf[idx++] = REG_DRAM_BLOCK;
251 buf[idx++] = REG_DRAM_WAIT_ACK;
252
253 for (i = 0; i < numchunks; ++i) {
254 /* Alternate bit to copy from DRAM to cache. */
255 if (i != (numchunks - 1))
256 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
257
258 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
259
260 if (i != (numchunks - 1))
261 buf[idx++] = REG_DRAM_WAIT_ACK;
262 }
263
264 sigma_write(buf, idx, ctx);
265
266 return sigma_read(data, numchunks * CHUNK_SIZE, ctx);
267}
268
269/* Upload trigger look-up tables to Sigma. */
270static int sigma_write_trigger_lut(struct triggerlut *lut, struct context *ctx)
271{
272 int i;
273 uint8_t tmp[2];
274 uint16_t bit;
275
276 /* Transpose the table and send to Sigma. */
277 for (i = 0; i < 16; ++i) {
278 bit = 1 << i;
279
280 tmp[0] = tmp[1] = 0;
281
282 if (lut->m2d[0] & bit)
283 tmp[0] |= 0x01;
284 if (lut->m2d[1] & bit)
285 tmp[0] |= 0x02;
286 if (lut->m2d[2] & bit)
287 tmp[0] |= 0x04;
288 if (lut->m2d[3] & bit)
289 tmp[0] |= 0x08;
290
291 if (lut->m3 & bit)
292 tmp[0] |= 0x10;
293 if (lut->m3s & bit)
294 tmp[0] |= 0x20;
295 if (lut->m4 & bit)
296 tmp[0] |= 0x40;
297
298 if (lut->m0d[0] & bit)
299 tmp[1] |= 0x01;
300 if (lut->m0d[1] & bit)
301 tmp[1] |= 0x02;
302 if (lut->m0d[2] & bit)
303 tmp[1] |= 0x04;
304 if (lut->m0d[3] & bit)
305 tmp[1] |= 0x08;
306
307 if (lut->m1d[0] & bit)
308 tmp[1] |= 0x10;
309 if (lut->m1d[1] & bit)
310 tmp[1] |= 0x20;
311 if (lut->m1d[2] & bit)
312 tmp[1] |= 0x40;
313 if (lut->m1d[3] & bit)
314 tmp[1] |= 0x80;
315
316 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
317 ctx);
318 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, ctx);
319 }
320
321 /* Send the parameters */
322 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
323 sizeof(lut->params), ctx);
324
325 return SR_OK;
326}
327
328/* Generate the bitbang stream for programming the FPGA. */
329static int bin2bitbang(const char *filename,
330 unsigned char **buf, size_t *buf_size)
331{
332 FILE *f;
333 unsigned long file_size;
334 unsigned long offset = 0;
335 unsigned char *p;
336 uint8_t *firmware;
337 unsigned long fwsize = 0;
338 const int buffer_size = 65536;
339 size_t i;
340 int c, bit, v;
341 uint32_t imm = 0x3f6df2ab;
342
343 f = g_fopen(filename, "rb");
344 if (!f) {
345 sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename);
346 return SR_ERR;
347 }
348
349 if (-1 == fseek(f, 0, SEEK_END)) {
350 sr_err("sigma: fseek on %s failed", filename);
351 fclose(f);
352 return SR_ERR;
353 }
354
355 file_size = ftell(f);
356
357 fseek(f, 0, SEEK_SET);
358
359 if (!(firmware = g_try_malloc(buffer_size))) {
360 sr_err("sigma: %s: firmware malloc failed", __func__);
361 fclose(f);
362 return SR_ERR_MALLOC;
363 }
364
365 while ((c = getc(f)) != EOF) {
366 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
367 firmware[fwsize++] = c ^ imm;
368 }
369 fclose(f);
370
371 if(fwsize != file_size) {
372 sr_err("sigma: %s: Error reading firmware", filename);
373 fclose(f);
374 g_free(firmware);
375 return SR_ERR;
376 }
377
378 *buf_size = fwsize * 2 * 8;
379
380 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
381 if (!p) {
382 sr_err("sigma: %s: buf/p malloc failed", __func__);
383 g_free(firmware);
384 return SR_ERR_MALLOC;
385 }
386
387 for (i = 0; i < fwsize; ++i) {
388 for (bit = 7; bit >= 0; --bit) {
389 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
390 p[offset++] = v | 0x01;
391 p[offset++] = v;
392 }
393 }
394
395 g_free(firmware);
396
397 if (offset != *buf_size) {
398 g_free(*buf);
399 sr_err("sigma: Error reading firmware %s "
400 "offset=%ld, file_size=%ld, buf_size=%zd.",
401 filename, offset, file_size, *buf_size);
402
403 return SR_ERR;
404 }
405
406 return SR_OK;
407}
408
409static void clear_instances(void)
410{
411 GSList *l;
412 struct sr_dev_inst *sdi;
413 struct context *ctx;
414
415 /* Properly close all devices. */
416 for (l = adi->instances; l; l = l->next) {
417 if (!(sdi = l->data)) {
418 /* Log error, but continue cleaning up the rest. */
419 sr_err("sigma: %s: sdi was NULL, continuing", __func__);
420 continue;
421 }
422 if (sdi->priv) {
423 ctx = sdi->priv;
424 ftdi_free(&ctx->ftdic);
425 g_free(ctx);
426 }
427 sr_dev_inst_free(sdi);
428 }
429 g_slist_free(adi->instances);
430 adi->instances = NULL;
431
432}
433
434static int hw_init(void)
435{
436
437 /* Nothing to do. */
438
439 return SR_OK;
440}
441
442static GSList *hw_scan(GSList *options)
443{
444 struct sr_dev_inst *sdi;
445 struct context *ctx;
446 GSList *devices;
447 struct ftdi_device_list *devlist;
448 char serial_txt[10];
449 uint32_t serial;
450 int ret;
451
452 (void)options;
453 devices = NULL;
454 clear_instances();
455
456 if (!(ctx = g_try_malloc(sizeof(struct context)))) {
457 sr_err("sigma: %s: ctx malloc failed", __func__);
458 return NULL;
459 }
460
461 ftdi_init(&ctx->ftdic);
462
463 /* Look for SIGMAs. */
464
465 if ((ret = ftdi_usb_find_all(&ctx->ftdic, &devlist,
466 USB_VENDOR, USB_PRODUCT)) <= 0) {
467 if (ret < 0)
468 sr_err("ftdi_usb_find_all(): %d", ret);
469 goto free;
470 }
471
472 /* Make sure it's a version 1 or 2 SIGMA. */
473 ftdi_usb_get_strings(&ctx->ftdic, devlist->dev, NULL, 0, NULL, 0,
474 serial_txt, sizeof(serial_txt));
475 sscanf(serial_txt, "%x", &serial);
476
477 if (serial < 0xa6010000 || serial > 0xa602ffff) {
478 sr_err("sigma: Only SIGMA and SIGMA2 are supported "
479 "in this version of sigrok.");
480 goto free;
481 }
482
483 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
484
485 ctx->cur_samplerate = 0;
486 ctx->period_ps = 0;
487 ctx->limit_msec = 0;
488 ctx->cur_firmware = -1;
489 ctx->num_probes = 0;
490 ctx->samples_per_event = 0;
491 ctx->capture_ratio = 50;
492 ctx->use_triggers = 0;
493
494 /* Register SIGMA device. */
495 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
496 USB_MODEL_NAME, USB_MODEL_VERSION))) {
497 sr_err("sigma: %s: sdi was NULL", __func__);
498 goto free;
499 }
500 sdi->driver = adi;
501 devices = g_slist_append(devices, sdi);
502 adi->instances = g_slist_append(adi->instances, sdi);
503 sdi->priv = ctx;
504
505 /* We will open the device again when we need it. */
506 ftdi_list_free(&devlist);
507
508 return devices;
509
510free:
511 ftdi_deinit(&ctx->ftdic);
512 g_free(ctx);
513 return NULL;
514}
515
516static int upload_firmware(int firmware_idx, struct context *ctx)
517{
518 int ret;
519 unsigned char *buf;
520 unsigned char pins;
521 size_t buf_size;
522 unsigned char result[32];
523 char firmware_path[128];
524
525 /* Make sure it's an ASIX SIGMA. */
526 if ((ret = ftdi_usb_open_desc(&ctx->ftdic,
527 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
528 sr_err("sigma: ftdi_usb_open failed: %s",
529 ftdi_get_error_string(&ctx->ftdic));
530 return 0;
531 }
532
533 if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
534 sr_err("sigma: ftdi_set_bitmode failed: %s",
535 ftdi_get_error_string(&ctx->ftdic));
536 return 0;
537 }
538
539 /* Four times the speed of sigmalogan - Works well. */
540 if ((ret = ftdi_set_baudrate(&ctx->ftdic, 750000)) < 0) {
541 sr_err("sigma: ftdi_set_baudrate failed: %s",
542 ftdi_get_error_string(&ctx->ftdic));
543 return 0;
544 }
545
546 /* Force the FPGA to reboot. */
547 sigma_write(suicide, sizeof(suicide), ctx);
548 sigma_write(suicide, sizeof(suicide), ctx);
549 sigma_write(suicide, sizeof(suicide), ctx);
550 sigma_write(suicide, sizeof(suicide), ctx);
551
552 /* Prepare to upload firmware (FPGA specific). */
553 sigma_write(init, sizeof(init), ctx);
554
555 ftdi_usb_purge_buffers(&ctx->ftdic);
556
557 /* Wait until the FPGA asserts INIT_B. */
558 while (1) {
559 ret = sigma_read(result, 1, ctx);
560 if (result[0] & 0x20)
561 break;
562 }
563
564 /* Prepare firmware. */
565 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
566 firmware_files[firmware_idx]);
567
568 if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
569 sr_err("sigma: An error occured while reading the firmware: %s",
570 firmware_path);
571 return ret;
572 }
573
574 /* Upload firmare. */
575 sr_info("sigma: Uploading firmware %s", firmware_files[firmware_idx]);
576 sigma_write(buf, buf_size, ctx);
577
578 g_free(buf);
579
580 if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0x00, BITMODE_RESET)) < 0) {
581 sr_err("sigma: ftdi_set_bitmode failed: %s",
582 ftdi_get_error_string(&ctx->ftdic));
583 return SR_ERR;
584 }
585
586 ftdi_usb_purge_buffers(&ctx->ftdic);
587
588 /* Discard garbage. */
589 while (1 == sigma_read(&pins, 1, ctx))
590 ;
591
592 /* Initialize the logic analyzer mode. */
593 sigma_write(logic_mode_start, sizeof(logic_mode_start), ctx);
594
595 /* Expect a 3 byte reply. */
596 ret = sigma_read(result, 3, ctx);
597 if (ret != 3 ||
598 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
599 sr_err("sigma: Configuration failed. Invalid reply received.");
600 return SR_ERR;
601 }
602
603 ctx->cur_firmware = firmware_idx;
604
605 sr_info("sigma: Firmware uploaded");
606
607 return SR_OK;
608}
609
610static int hw_dev_open(int dev_index)
611{
612 struct sr_dev_inst *sdi;
613 struct context *ctx;
614 int ret;
615
616 if (!(sdi = sr_dev_inst_get(adi->instances, dev_index)))
617 return SR_ERR;
618
619 ctx = sdi->priv;
620
621 /* Make sure it's an ASIX SIGMA. */
622 if ((ret = ftdi_usb_open_desc(&ctx->ftdic,
623 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
624
625 sr_err("sigma: ftdi_usb_open failed: %s",
626 ftdi_get_error_string(&ctx->ftdic));
627
628 return 0;
629 }
630
631 sdi->status = SR_ST_ACTIVE;
632
633 return SR_OK;
634}
635
636static int set_samplerate(struct sr_dev_inst *sdi, uint64_t samplerate)
637{
638 int i, ret;
639 struct context *ctx = sdi->priv;
640
641 for (i = 0; supported_samplerates[i]; i++) {
642 if (supported_samplerates[i] == samplerate)
643 break;
644 }
645 if (supported_samplerates[i] == 0)
646 return SR_ERR_SAMPLERATE;
647
648 if (samplerate <= SR_MHZ(50)) {
649 ret = upload_firmware(0, ctx);
650 ctx->num_probes = 16;
651 }
652 if (samplerate == SR_MHZ(100)) {
653 ret = upload_firmware(1, ctx);
654 ctx->num_probes = 8;
655 }
656 else if (samplerate == SR_MHZ(200)) {
657 ret = upload_firmware(2, ctx);
658 ctx->num_probes = 4;
659 }
660
661 ctx->cur_samplerate = samplerate;
662 ctx->period_ps = 1000000000000 / samplerate;
663 ctx->samples_per_event = 16 / ctx->num_probes;
664 ctx->state.state = SIGMA_IDLE;
665
666 return ret;
667}
668
669/*
670 * In 100 and 200 MHz mode, only a single pin rising/falling can be
671 * set as trigger. In other modes, two rising/falling triggers can be set,
672 * in addition to value/mask trigger for any number of probes.
673 *
674 * The Sigma supports complex triggers using boolean expressions, but this
675 * has not been implemented yet.
676 */
677static int configure_probes(struct sr_dev_inst *sdi, const GSList *probes)
678{
679 struct context *ctx = sdi->priv;
680 const struct sr_probe *probe;
681 const GSList *l;
682 int trigger_set = 0;
683 int probebit;
684
685 memset(&ctx->trigger, 0, sizeof(struct sigma_trigger));
686
687 for (l = probes; l; l = l->next) {
688 probe = (struct sr_probe *)l->data;
689 probebit = 1 << (probe->index - 1);
690
691 if (!probe->enabled || !probe->trigger)
692 continue;
693
694 if (ctx->cur_samplerate >= SR_MHZ(100)) {
695 /* Fast trigger support. */
696 if (trigger_set) {
697 sr_err("sigma: ASIX SIGMA only supports a single "
698 "pin trigger in 100 and 200MHz mode.");
699 return SR_ERR;
700 }
701 if (probe->trigger[0] == 'f')
702 ctx->trigger.fallingmask |= probebit;
703 else if (probe->trigger[0] == 'r')
704 ctx->trigger.risingmask |= probebit;
705 else {
706 sr_err("sigma: ASIX SIGMA only supports "
707 "rising/falling trigger in 100 "
708 "and 200MHz mode.");
709 return SR_ERR;
710 }
711
712 ++trigger_set;
713 } else {
714 /* Simple trigger support (event). */
715 if (probe->trigger[0] == '1') {
716 ctx->trigger.simplevalue |= probebit;
717 ctx->trigger.simplemask |= probebit;
718 }
719 else if (probe->trigger[0] == '0') {
720 ctx->trigger.simplevalue &= ~probebit;
721 ctx->trigger.simplemask |= probebit;
722 }
723 else if (probe->trigger[0] == 'f') {
724 ctx->trigger.fallingmask |= probebit;
725 ++trigger_set;
726 }
727 else if (probe->trigger[0] == 'r') {
728 ctx->trigger.risingmask |= probebit;
729 ++trigger_set;
730 }
731
732 /*
733 * Actually, Sigma supports 2 rising/falling triggers,
734 * but they are ORed and the current trigger syntax
735 * does not permit ORed triggers.
736 */
737 if (trigger_set > 1) {
738 sr_err("sigma: ASIX SIGMA only supports 1 "
739 "rising/falling triggers.");
740 return SR_ERR;
741 }
742 }
743
744 if (trigger_set)
745 ctx->use_triggers = 1;
746 }
747
748 return SR_OK;
749}
750
751static int hw_dev_close(int dev_index)
752{
753 struct sr_dev_inst *sdi;
754 struct context *ctx;
755
756 if (!(sdi = sr_dev_inst_get(adi->instances, dev_index))) {
757 sr_err("sigma: %s: sdi was NULL", __func__);
758 return SR_ERR_BUG;
759 }
760
761 if (!(ctx = sdi->priv)) {
762 sr_err("sigma: %s: sdi->priv was NULL", __func__);
763 return SR_ERR_BUG;
764 }
765
766 /* TODO */
767 if (sdi->status == SR_ST_ACTIVE)
768 ftdi_usb_close(&ctx->ftdic);
769
770 sdi->status = SR_ST_INACTIVE;
771
772 return SR_OK;
773}
774
775static int hw_cleanup(void)
776{
777
778 clear_instances();
779
780 return SR_OK;
781}
782
783static int hw_info_get(int info_id, const void **data,
784 const struct sr_dev_inst *sdi)
785{
786 struct context *ctx;
787
788 switch (info_id) {
789 case SR_DI_INST:
790 *data = sdi;
791 break;
792 case SR_DI_HWCAPS:
793 *data = hwcaps;
794 break;
795 case SR_DI_NUM_PROBES:
796 *data = GINT_TO_POINTER(NUM_PROBES);
797 break;
798 case SR_DI_PROBE_NAMES:
799 *data = probe_names;
800 break;
801 case SR_DI_SAMPLERATES:
802 *data = &samplerates;
803 break;
804 case SR_DI_TRIGGER_TYPES:
805 *data = (char *)TRIGGER_TYPES;
806 break;
807 case SR_DI_CUR_SAMPLERATE:
808 if (sdi) {
809 ctx = sdi->priv;
810 *data = &ctx->cur_samplerate;
811 } else
812 return SR_ERR;
813 break;
814 default:
815 return SR_ERR_ARG;
816 }
817
818 return SR_OK;
819}
820
821static int hw_dev_status_get(int dev_index)
822{
823 struct sr_dev_inst *sdi;
824
825 sdi = sr_dev_inst_get(adi->instances, dev_index);
826 if (sdi)
827 return sdi->status;
828 else
829 return SR_ST_NOT_FOUND;
830}
831
832static int hw_dev_config_set(int dev_index, int hwcap, const void *value)
833{
834 struct sr_dev_inst *sdi;
835 struct context *ctx;
836 int ret;
837
838 if (!(sdi = sr_dev_inst_get(adi->instances, dev_index)))
839 return SR_ERR;
840
841 ctx = sdi->priv;
842
843 if (hwcap == SR_HWCAP_SAMPLERATE) {
844 ret = set_samplerate(sdi, *(const uint64_t *)value);
845 } else if (hwcap == SR_HWCAP_PROBECONFIG) {
846 ret = configure_probes(sdi, value);
847 } else if (hwcap == SR_HWCAP_LIMIT_MSEC) {
848 ctx->limit_msec = *(const uint64_t *)value;
849 if (ctx->limit_msec > 0)
850 ret = SR_OK;
851 else
852 ret = SR_ERR;
853 } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) {
854 ctx->capture_ratio = *(const uint64_t *)value;
855 if (ctx->capture_ratio < 0 || ctx->capture_ratio > 100)
856 ret = SR_ERR;
857 else
858 ret = SR_OK;
859 } else {
860 ret = SR_ERR;
861 }
862
863 return ret;
864}
865
866/* Software trigger to determine exact trigger position. */
867static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
868 struct sigma_trigger *t)
869{
870 int i;
871
872 for (i = 0; i < 8; ++i) {
873 if (i > 0)
874 last_sample = samples[i-1];
875
876 /* Simple triggers. */
877 if ((samples[i] & t->simplemask) != t->simplevalue)
878 continue;
879
880 /* Rising edge. */
881 if ((last_sample & t->risingmask) != 0 || (samples[i] &
882 t->risingmask) != t->risingmask)
883 continue;
884
885 /* Falling edge. */
886 if ((last_sample & t->fallingmask) != t->fallingmask ||
887 (samples[i] & t->fallingmask) != 0)
888 continue;
889
890 break;
891 }
892
893 /* If we did not match, return original trigger pos. */
894 return i & 0x7;
895}
896
897/*
898 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
899 * Each event is 20ns apart, and can contain multiple samples.
900 *
901 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
902 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
903 * For 50 MHz and below, events contain one sample for each channel,
904 * spread 20 ns apart.
905 */
906static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
907 uint16_t *lastsample, int triggerpos,
908 uint16_t limit_chunk, void *cb_data)
909{
910 struct sr_dev_inst *sdi = cb_data;
911 struct context *ctx = sdi->priv;
912 uint16_t tsdiff, ts;
913 uint16_t samples[65536 * ctx->samples_per_event];
914 struct sr_datafeed_packet packet;
915 struct sr_datafeed_logic logic;
916 int i, j, k, l, numpad, tosend;
917 size_t n = 0, sent = 0;
918 int clustersize = EVENTS_PER_CLUSTER * ctx->samples_per_event;
919 uint16_t *event;
920 uint16_t cur_sample;
921 int triggerts = -1;
922
923 /* Check if trigger is in this chunk. */
924 if (triggerpos != -1) {
925 if (ctx->cur_samplerate <= SR_MHZ(50))
926 triggerpos -= EVENTS_PER_CLUSTER - 1;
927
928 if (triggerpos < 0)
929 triggerpos = 0;
930
931 /* Find in which cluster the trigger occured. */
932 triggerts = triggerpos / 7;
933 }
934
935 /* For each ts. */
936 for (i = 0; i < 64; ++i) {
937 ts = *(uint16_t *) &buf[i * 16];
938 tsdiff = ts - *lastts;
939 *lastts = ts;
940
941 /* Decode partial chunk. */
942 if (limit_chunk && ts > limit_chunk)
943 return SR_OK;
944
945 /* Pad last sample up to current point. */
946 numpad = tsdiff * ctx->samples_per_event - clustersize;
947 if (numpad > 0) {
948 for (j = 0; j < numpad; ++j)
949 samples[j] = *lastsample;
950
951 n = numpad;
952 }
953
954 /* Send samples between previous and this timestamp to sigrok. */
955 sent = 0;
956 while (sent < n) {
957 tosend = MIN(2048, n - sent);
958
959 packet.type = SR_DF_LOGIC;
960 packet.payload = &logic;
961 logic.length = tosend * sizeof(uint16_t);
962 logic.unitsize = 2;
963 logic.data = samples + sent;
964 sr_session_send(ctx->session_dev_id, &packet);
965
966 sent += tosend;
967 }
968 n = 0;
969
970 event = (uint16_t *) &buf[i * 16 + 2];
971 cur_sample = 0;
972
973 /* For each event in cluster. */
974 for (j = 0; j < 7; ++j) {
975
976 /* For each sample in event. */
977 for (k = 0; k < ctx->samples_per_event; ++k) {
978 cur_sample = 0;
979
980 /* For each probe. */
981 for (l = 0; l < ctx->num_probes; ++l)
982 cur_sample |= (!!(event[j] & (1 << (l *
983 ctx->samples_per_event + k)))) << l;
984
985 samples[n++] = cur_sample;
986 }
987 }
988
989 /* Send data up to trigger point (if triggered). */
990 sent = 0;
991 if (i == triggerts) {
992 /*
993 * Trigger is not always accurate to sample because of
994 * pipeline delay. However, it always triggers before
995 * the actual event. We therefore look at the next
996 * samples to pinpoint the exact position of the trigger.
997 */
998 tosend = get_trigger_offset(samples, *lastsample,
999 &ctx->trigger);
1000
1001 if (tosend > 0) {
1002 packet.type = SR_DF_LOGIC;
1003 packet.payload = &logic;
1004 logic.length = tosend * sizeof(uint16_t);
1005 logic.unitsize = 2;
1006 logic.data = samples;
1007 sr_session_send(ctx->session_dev_id, &packet);
1008
1009 sent += tosend;
1010 }
1011
1012 /* Only send trigger if explicitly enabled. */
1013 if (ctx->use_triggers) {
1014 packet.type = SR_DF_TRIGGER;
1015 sr_session_send(ctx->session_dev_id, &packet);
1016 }
1017 }
1018
1019 /* Send rest of the chunk to sigrok. */
1020 tosend = n - sent;
1021
1022 if (tosend > 0) {
1023 packet.type = SR_DF_LOGIC;
1024 packet.payload = &logic;
1025 logic.length = tosend * sizeof(uint16_t);
1026 logic.unitsize = 2;
1027 logic.data = samples + sent;
1028 sr_session_send(ctx->session_dev_id, &packet);
1029 }
1030
1031 *lastsample = samples[n - 1];
1032 }
1033
1034 return SR_OK;
1035}
1036
1037static int receive_data(int fd, int revents, void *cb_data)
1038{
1039 struct sr_dev_inst *sdi = cb_data;
1040 struct context *ctx = sdi->priv;
1041 struct sr_datafeed_packet packet;
1042 const int chunks_per_read = 32;
1043 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1044 int bufsz, numchunks, i, newchunks;
1045 uint64_t running_msec;
1046 struct timeval tv;
1047
1048 /* Avoid compiler warnings. */
1049 (void)fd;
1050 (void)revents;
1051
1052 /* Get the current position. */
1053 sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx);
1054
1055 numchunks = (ctx->state.stoppos + 511) / 512;
1056
1057 if (ctx->state.state == SIGMA_IDLE)
1058 return TRUE;
1059
1060 if (ctx->state.state == SIGMA_CAPTURE) {
1061 /* Check if the timer has expired, or memory is full. */
1062 gettimeofday(&tv, 0);
1063 running_msec = (tv.tv_sec - ctx->start_tv.tv_sec) * 1000 +
1064 (tv.tv_usec - ctx->start_tv.tv_usec) / 1000;
1065
1066 if (running_msec < ctx->limit_msec && numchunks < 32767)
1067 return TRUE; /* While capturing... */
1068 else
1069 hw_dev_acquisition_stop(sdi->index, sdi);
1070
1071 } else if (ctx->state.state == SIGMA_DOWNLOAD) {
1072 if (ctx->state.chunks_downloaded >= numchunks) {
1073 /* End of samples. */
1074 packet.type = SR_DF_END;
1075 sr_session_send(ctx->session_dev_id, &packet);
1076
1077 ctx->state.state = SIGMA_IDLE;
1078
1079 return TRUE;
1080 }
1081
1082 newchunks = MIN(chunks_per_read,
1083 numchunks - ctx->state.chunks_downloaded);
1084
1085 sr_info("sigma: Downloading sample data: %.0f %%",
1086 100.0 * ctx->state.chunks_downloaded / numchunks);
1087
1088 bufsz = sigma_read_dram(ctx->state.chunks_downloaded,
1089 newchunks, buf, ctx);
1090 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1091 (void)bufsz;
1092
1093 /* Find first ts. */
1094 if (ctx->state.chunks_downloaded == 0) {
1095 ctx->state.lastts = *(uint16_t *) buf - 1;
1096 ctx->state.lastsample = 0;
1097 }
1098
1099 /* Decode chunks and send them to sigrok. */
1100 for (i = 0; i < newchunks; ++i) {
1101 int limit_chunk = 0;
1102
1103 /* The last chunk may potentially be only in part. */
1104 if (ctx->state.chunks_downloaded == numchunks - 1) {
1105 /* Find the last valid timestamp */
1106 limit_chunk = ctx->state.stoppos % 512 + ctx->state.lastts;
1107 }
1108
1109 if (ctx->state.chunks_downloaded + i == ctx->state.triggerchunk)
1110 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1111 &ctx->state.lastts,
1112 &ctx->state.lastsample,
1113 ctx->state.triggerpos & 0x1ff,
1114 limit_chunk, sdi);
1115 else
1116 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1117 &ctx->state.lastts,
1118 &ctx->state.lastsample,
1119 -1, limit_chunk, sdi);
1120
1121 ++ctx->state.chunks_downloaded;
1122 }
1123 }
1124
1125 return TRUE;
1126}
1127
1128/* Build a LUT entry used by the trigger functions. */
1129static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1130{
1131 int i, j, k, bit;
1132
1133 /* For each quad probe. */
1134 for (i = 0; i < 4; ++i) {
1135 entry[i] = 0xffff;
1136
1137 /* For each bit in LUT. */
1138 for (j = 0; j < 16; ++j)
1139
1140 /* For each probe in quad. */
1141 for (k = 0; k < 4; ++k) {
1142 bit = 1 << (i * 4 + k);
1143
1144 /* Set bit in entry */
1145 if ((mask & bit) &&
1146 ((!(value & bit)) !=
1147 (!(j & (1 << k)))))
1148 entry[i] &= ~(1 << j);
1149 }
1150 }
1151}
1152
1153/* Add a logical function to LUT mask. */
1154static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1155 int index, int neg, uint16_t *mask)
1156{
1157 int i, j;
1158 int x[2][2], tmp, a, b, aset, bset, rset;
1159
1160 memset(x, 0, 4 * sizeof(int));
1161
1162 /* Trigger detect condition. */
1163 switch (oper) {
1164 case OP_LEVEL:
1165 x[0][1] = 1;
1166 x[1][1] = 1;
1167 break;
1168 case OP_NOT:
1169 x[0][0] = 1;
1170 x[1][0] = 1;
1171 break;
1172 case OP_RISE:
1173 x[0][1] = 1;
1174 break;
1175 case OP_FALL:
1176 x[1][0] = 1;
1177 break;
1178 case OP_RISEFALL:
1179 x[0][1] = 1;
1180 x[1][0] = 1;
1181 break;
1182 case OP_NOTRISE:
1183 x[1][1] = 1;
1184 x[0][0] = 1;
1185 x[1][0] = 1;
1186 break;
1187 case OP_NOTFALL:
1188 x[1][1] = 1;
1189 x[0][0] = 1;
1190 x[0][1] = 1;
1191 break;
1192 case OP_NOTRISEFALL:
1193 x[1][1] = 1;
1194 x[0][0] = 1;
1195 break;
1196 }
1197
1198 /* Transpose if neg is set. */
1199 if (neg) {
1200 for (i = 0; i < 2; ++i) {
1201 for (j = 0; j < 2; ++j) {
1202 tmp = x[i][j];
1203 x[i][j] = x[1-i][1-j];
1204 x[1-i][1-j] = tmp;
1205 }
1206 }
1207 }
1208
1209 /* Update mask with function. */
1210 for (i = 0; i < 16; ++i) {
1211 a = (i >> (2 * index + 0)) & 1;
1212 b = (i >> (2 * index + 1)) & 1;
1213
1214 aset = (*mask >> i) & 1;
1215 bset = x[b][a];
1216
1217 if (func == FUNC_AND || func == FUNC_NAND)
1218 rset = aset & bset;
1219 else if (func == FUNC_OR || func == FUNC_NOR)
1220 rset = aset | bset;
1221 else if (func == FUNC_XOR || func == FUNC_NXOR)
1222 rset = aset ^ bset;
1223
1224 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1225 rset = !rset;
1226
1227 *mask &= ~(1 << i);
1228
1229 if (rset)
1230 *mask |= 1 << i;
1231 }
1232}
1233
1234/*
1235 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1236 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1237 * set at any time, but a full mask and value can be set (0/1).
1238 */
1239static int build_basic_trigger(struct triggerlut *lut, struct context *ctx)
1240{
1241 int i,j;
1242 uint16_t masks[2] = { 0, 0 };
1243
1244 memset(lut, 0, sizeof(struct triggerlut));
1245
1246 /* Contant for simple triggers. */
1247 lut->m4 = 0xa000;
1248
1249 /* Value/mask trigger support. */
1250 build_lut_entry(ctx->trigger.simplevalue, ctx->trigger.simplemask,
1251 lut->m2d);
1252
1253 /* Rise/fall trigger support. */
1254 for (i = 0, j = 0; i < 16; ++i) {
1255 if (ctx->trigger.risingmask & (1 << i) ||
1256 ctx->trigger.fallingmask & (1 << i))
1257 masks[j++] = 1 << i;
1258 }
1259
1260 build_lut_entry(masks[0], masks[0], lut->m0d);
1261 build_lut_entry(masks[1], masks[1], lut->m1d);
1262
1263 /* Add glue logic */
1264 if (masks[0] || masks[1]) {
1265 /* Transition trigger. */
1266 if (masks[0] & ctx->trigger.risingmask)
1267 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1268 if (masks[0] & ctx->trigger.fallingmask)
1269 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1270 if (masks[1] & ctx->trigger.risingmask)
1271 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1272 if (masks[1] & ctx->trigger.fallingmask)
1273 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1274 } else {
1275 /* Only value/mask trigger. */
1276 lut->m3 = 0xffff;
1277 }
1278
1279 /* Triggertype: event. */
1280 lut->params.selres = 3;
1281
1282 return SR_OK;
1283}
1284
1285static int hw_dev_acquisition_start(int dev_index, void *cb_data)
1286{
1287 struct sr_dev_inst *sdi;
1288 struct context *ctx;
1289 struct sr_datafeed_packet *packet;
1290 struct sr_datafeed_header *header;
1291 struct sr_datafeed_meta_logic meta;
1292 struct clockselect_50 clockselect;
1293 int frac, triggerpin, ret;
1294 uint8_t triggerselect;
1295 struct triggerinout triggerinout_conf;
1296 struct triggerlut lut;
1297
1298 if (!(sdi = sr_dev_inst_get(adi->instances, dev_index)))
1299 return SR_ERR;
1300
1301 ctx = sdi->priv;
1302
1303 /* If the samplerate has not been set, default to 200 kHz. */
1304 if (ctx->cur_firmware == -1) {
1305 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1306 return ret;
1307 }
1308
1309 /* Enter trigger programming mode. */
1310 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, ctx);
1311
1312 /* 100 and 200 MHz mode. */
1313 if (ctx->cur_samplerate >= SR_MHZ(100)) {
1314 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, ctx);
1315
1316 /* Find which pin to trigger on from mask. */
1317 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1318 if ((ctx->trigger.risingmask | ctx->trigger.fallingmask) &
1319 (1 << triggerpin))
1320 break;
1321
1322 /* Set trigger pin and light LED on trigger. */
1323 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1324
1325 /* Default rising edge. */
1326 if (ctx->trigger.fallingmask)
1327 triggerselect |= 1 << 3;
1328
1329 /* All other modes. */
1330 } else if (ctx->cur_samplerate <= SR_MHZ(50)) {
1331 build_basic_trigger(&lut, ctx);
1332
1333 sigma_write_trigger_lut(&lut, ctx);
1334
1335 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1336 }
1337
1338 /* Setup trigger in and out pins to default values. */
1339 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1340 triggerinout_conf.trgout_bytrigger = 1;
1341 triggerinout_conf.trgout_enable = 1;
1342
1343 sigma_write_register(WRITE_TRIGGER_OPTION,
1344 (uint8_t *) &triggerinout_conf,
1345 sizeof(struct triggerinout), ctx);
1346
1347 /* Go back to normal mode. */
1348 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, ctx);
1349
1350 /* Set clock select register. */
1351 if (ctx->cur_samplerate == SR_MHZ(200))
1352 /* Enable 4 probes. */
1353 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, ctx);
1354 else if (ctx->cur_samplerate == SR_MHZ(100))
1355 /* Enable 8 probes. */
1356 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, ctx);
1357 else {
1358 /*
1359 * 50 MHz mode (or fraction thereof). Any fraction down to
1360 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1361 */
1362 frac = SR_MHZ(50) / ctx->cur_samplerate - 1;
1363
1364 clockselect.async = 0;
1365 clockselect.fraction = frac;
1366 clockselect.disabled_probes = 0;
1367
1368 sigma_write_register(WRITE_CLOCK_SELECT,
1369 (uint8_t *) &clockselect,
1370 sizeof(clockselect), ctx);
1371 }
1372
1373 /* Setup maximum post trigger time. */
1374 sigma_set_register(WRITE_POST_TRIGGER,
1375 (ctx->capture_ratio * 255) / 100, ctx);
1376
1377 /* Start acqusition. */
1378 gettimeofday(&ctx->start_tv, 0);
1379 sigma_set_register(WRITE_MODE, 0x0d, ctx);
1380
1381 ctx->session_dev_id = cb_data;
1382
1383 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1384 sr_err("sigma: %s: packet malloc failed.", __func__);
1385 return SR_ERR_MALLOC;
1386 }
1387
1388 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1389 sr_err("sigma: %s: header malloc failed.", __func__);
1390 return SR_ERR_MALLOC;
1391 }
1392
1393 /* Send header packet to the session bus. */
1394 packet->type = SR_DF_HEADER;
1395 packet->payload = header;
1396 header->feed_version = 1;
1397 gettimeofday(&header->starttime, NULL);
1398 sr_session_send(ctx->session_dev_id, packet);
1399
1400 /* Send metadata about the SR_DF_LOGIC packets to come. */
1401 packet->type = SR_DF_META_LOGIC;
1402 packet->payload = &meta;
1403 meta.samplerate = ctx->cur_samplerate;
1404 meta.num_probes = ctx->num_probes;
1405 sr_session_send(ctx->session_dev_id, packet);
1406
1407 /* Add capture source. */
1408 sr_source_add(0, G_IO_IN, 10, receive_data, sdi);
1409
1410 g_free(header);
1411 g_free(packet);
1412
1413 ctx->state.state = SIGMA_CAPTURE;
1414
1415 return SR_OK;
1416}
1417
1418static int hw_dev_acquisition_stop(int dev_index, void *cb_data)
1419{
1420 struct sr_dev_inst *sdi;
1421 struct context *ctx;
1422 uint8_t modestatus;
1423
1424 /* Avoid compiler warnings. */
1425 (void)cb_data;
1426
1427 if (!(sdi = sr_dev_inst_get(adi->instances, dev_index))) {
1428 sr_err("sigma: %s: sdi was NULL", __func__);
1429 return SR_ERR_BUG;
1430 }
1431
1432 if (!(ctx = sdi->priv)) {
1433 sr_err("sigma: %s: sdi->priv was NULL", __func__);
1434 return SR_ERR_BUG;
1435 }
1436
1437 /* Stop acquisition. */
1438 sigma_set_register(WRITE_MODE, 0x11, ctx);
1439
1440 /* Set SDRAM Read Enable. */
1441 sigma_set_register(WRITE_MODE, 0x02, ctx);
1442
1443 /* Get the current position. */
1444 sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx);
1445
1446 /* Check if trigger has fired. */
1447 modestatus = sigma_get_register(READ_MODE, ctx);
1448 if (modestatus & 0x20)
1449 ctx->state.triggerchunk = ctx->state.triggerpos / 512;
1450 else
1451 ctx->state.triggerchunk = -1;
1452
1453 ctx->state.chunks_downloaded = 0;
1454
1455 ctx->state.state = SIGMA_DOWNLOAD;
1456
1457 return SR_OK;
1458}
1459
1460SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1461 .name = "asix-sigma",
1462 .longname = "ASIX SIGMA/SIGMA2",
1463 .api_version = 1,
1464 .init = hw_init,
1465 .cleanup = hw_cleanup,
1466 .scan = hw_scan,
1467 .dev_open = hw_dev_open,
1468 .dev_close = hw_dev_close,
1469 .info_get = hw_info_get,
1470 .dev_status_get = hw_dev_status_get,
1471 .dev_config_set = hw_dev_config_set,
1472 .dev_acquisition_start = hw_dev_acquisition_start,
1473 .dev_acquisition_stop = hw_dev_acquisition_stop,
1474 .instances = NULL,
1475};
Hardware access and backend lib