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1/*
2 * This file is part of the sigrok project.
3 *
4 * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22/*
23 * ASIX Sigma Logic Analyzer Driver
24 */
25
26#include "config.h"
27#include <glib.h>
28#include <glib/gstdio.h>
29#include <ftdi.h>
30#include <string.h>
31#include <zlib.h>
32#include <sigrok.h>
33#include <sigrok-internal.h>
34#include "asix-sigma.h"
35
36#define USB_VENDOR 0xa600
37#define USB_PRODUCT 0xa000
38#define USB_DESCRIPTION "ASIX SIGMA"
39#define USB_VENDOR_NAME "ASIX"
40#define USB_MODEL_NAME "SIGMA"
41#define USB_MODEL_VERSION ""
42#define TRIGGER_TYPES "rf10"
43
44static GSList *device_instances = NULL;
45
46static uint64_t supported_samplerates[] = {
47 SR_KHZ(200),
48 SR_KHZ(250),
49 SR_KHZ(500),
50 SR_MHZ(1),
51 SR_MHZ(5),
52 SR_MHZ(10),
53 SR_MHZ(25),
54 SR_MHZ(50),
55 SR_MHZ(100),
56 SR_MHZ(200),
57 0,
58};
59
60static struct sr_samplerates samplerates = {
61 SR_KHZ(200),
62 SR_MHZ(200),
63 SR_HZ(0),
64 supported_samplerates,
65};
66
67static int capabilities[] = {
68 SR_HWCAP_LOGIC_ANALYZER,
69 SR_HWCAP_SAMPLERATE,
70 SR_HWCAP_CAPTURE_RATIO,
71 SR_HWCAP_PROBECONFIG,
72
73 SR_HWCAP_LIMIT_MSEC,
74 0,
75};
76
77/* Force the FPGA to reboot. */
78static uint8_t suicide[] = {
79 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
80};
81
82/* Prepare to upload firmware (FPGA specific). */
83static uint8_t init[] = {
84 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
85};
86
87/* Initialize the logic analyzer mode. */
88static uint8_t logic_mode_start[] = {
89 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
90 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
91};
92
93static const char *firmware_files[] = {
94 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
95 "asix-sigma-100.fw", /* 100 MHz */
96 "asix-sigma-200.fw", /* 200 MHz */
97 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
98 "asix-sigma-phasor.fw", /* Frequency counter */
99};
100
101static void hw_stop_acquisition(int device_index, gpointer session_device_id);
102
103static int sigma_read(void *buf, size_t size, struct sigma *sigma)
104{
105 int ret;
106
107 ret = ftdi_read_data(&sigma->ftdic, (unsigned char *)buf, size);
108 if (ret < 0) {
109 sr_warn("ftdi_read_data failed: %s",
110 ftdi_get_error_string(&sigma->ftdic));
111 }
112
113 return ret;
114}
115
116static int sigma_write(void *buf, size_t size, struct sigma *sigma)
117{
118 int ret;
119
120 ret = ftdi_write_data(&sigma->ftdic, (unsigned char *)buf, size);
121 if (ret < 0) {
122 sr_warn("ftdi_write_data failed: %s",
123 ftdi_get_error_string(&sigma->ftdic));
124 } else if ((size_t) ret != size) {
125 sr_warn("ftdi_write_data did not complete write\n");
126 }
127
128 return ret;
129}
130
131static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
132 struct sigma *sigma)
133{
134 size_t i;
135 uint8_t buf[len + 2];
136 int idx = 0;
137
138 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
139 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
140
141 for (i = 0; i < len; ++i) {
142 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
143 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
144 }
145
146 return sigma_write(buf, idx, sigma);
147}
148
149static int sigma_set_register(uint8_t reg, uint8_t value, struct sigma *sigma)
150{
151 return sigma_write_register(reg, &value, 1, sigma);
152}
153
154static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
155 struct sigma *sigma)
156{
157 uint8_t buf[3];
158
159 buf[0] = REG_ADDR_LOW | (reg & 0xf);
160 buf[1] = REG_ADDR_HIGH | (reg >> 4);
161 buf[2] = REG_READ_ADDR;
162
163 sigma_write(buf, sizeof(buf), sigma);
164
165 return sigma_read(data, len, sigma);
166}
167
168static uint8_t sigma_get_register(uint8_t reg, struct sigma *sigma)
169{
170 uint8_t value;
171
172 if (1 != sigma_read_register(reg, &value, 1, sigma)) {
173 sr_warn("sigma_get_register: 1 byte expected");
174 return 0;
175 }
176
177 return value;
178}
179
180static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
181 struct sigma *sigma)
182{
183 uint8_t buf[] = {
184 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
185
186 REG_READ_ADDR | NEXT_REG,
187 REG_READ_ADDR | NEXT_REG,
188 REG_READ_ADDR | NEXT_REG,
189 REG_READ_ADDR | NEXT_REG,
190 REG_READ_ADDR | NEXT_REG,
191 REG_READ_ADDR | NEXT_REG,
192 };
193 uint8_t result[6];
194
195 sigma_write(buf, sizeof(buf), sigma);
196
197 sigma_read(result, sizeof(result), sigma);
198
199 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
200 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
201
202 /* Not really sure why this must be done, but according to spec. */
203 if ((--*stoppos & 0x1ff) == 0x1ff)
204 stoppos -= 64;
205
206 if ((*--triggerpos & 0x1ff) == 0x1ff)
207 triggerpos -= 64;
208
209 return 1;
210}
211
212static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
213 uint8_t *data, struct sigma *sigma)
214{
215 size_t i;
216 uint8_t buf[4096];
217 int idx = 0;
218
219 /* Send the startchunk. Index start with 1. */
220 buf[0] = startchunk >> 8;
221 buf[1] = startchunk & 0xff;
222 sigma_write_register(WRITE_MEMROW, buf, 2, sigma);
223
224 /* Read the DRAM. */
225 buf[idx++] = REG_DRAM_BLOCK;
226 buf[idx++] = REG_DRAM_WAIT_ACK;
227
228 for (i = 0; i < numchunks; ++i) {
229 /* Alternate bit to copy from DRAM to cache. */
230 if (i != (numchunks - 1))
231 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
232
233 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
234
235 if (i != (numchunks - 1))
236 buf[idx++] = REG_DRAM_WAIT_ACK;
237 }
238
239 sigma_write(buf, idx, sigma);
240
241 return sigma_read(data, numchunks * CHUNK_SIZE, sigma);
242}
243
244/* Upload trigger look-up tables to Sigma. */
245static int sigma_write_trigger_lut(struct triggerlut *lut, struct sigma *sigma)
246{
247 int i;
248 uint8_t tmp[2];
249 uint16_t bit;
250
251 /* Transpose the table and send to Sigma. */
252 for (i = 0; i < 16; ++i) {
253 bit = 1 << i;
254
255 tmp[0] = tmp[1] = 0;
256
257 if (lut->m2d[0] & bit)
258 tmp[0] |= 0x01;
259 if (lut->m2d[1] & bit)
260 tmp[0] |= 0x02;
261 if (lut->m2d[2] & bit)
262 tmp[0] |= 0x04;
263 if (lut->m2d[3] & bit)
264 tmp[0] |= 0x08;
265
266 if (lut->m3 & bit)
267 tmp[0] |= 0x10;
268 if (lut->m3s & bit)
269 tmp[0] |= 0x20;
270 if (lut->m4 & bit)
271 tmp[0] |= 0x40;
272
273 if (lut->m0d[0] & bit)
274 tmp[1] |= 0x01;
275 if (lut->m0d[1] & bit)
276 tmp[1] |= 0x02;
277 if (lut->m0d[2] & bit)
278 tmp[1] |= 0x04;
279 if (lut->m0d[3] & bit)
280 tmp[1] |= 0x08;
281
282 if (lut->m1d[0] & bit)
283 tmp[1] |= 0x10;
284 if (lut->m1d[1] & bit)
285 tmp[1] |= 0x20;
286 if (lut->m1d[2] & bit)
287 tmp[1] |= 0x40;
288 if (lut->m1d[3] & bit)
289 tmp[1] |= 0x80;
290
291 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
292 sigma);
293 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, sigma);
294 }
295
296 /* Send the parameters */
297 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
298 sizeof(lut->params), sigma);
299
300 return SR_OK;
301}
302
303/* Generate the bitbang stream for programming the FPGA. */
304static int bin2bitbang(const char *filename,
305 unsigned char **buf, size_t *buf_size)
306{
307 FILE *f;
308 long file_size;
309 unsigned long offset = 0;
310 unsigned char *p;
311 uint8_t *compressed_buf, *firmware;
312 uLongf csize, fwsize;
313 const int buffer_size = 65536;
314 size_t i;
315 int c, ret, bit, v;
316 uint32_t imm = 0x3f6df2ab;
317
318 f = g_fopen(filename, "rb");
319 if (!f) {
320 sr_warn("g_fopen(\"%s\", \"rb\")", filename);
321 return SR_ERR;
322 }
323
324 if (-1 == fseek(f, 0, SEEK_END)) {
325 sr_warn("fseek on %s failed", filename);
326 fclose(f);
327 return SR_ERR;
328 }
329
330 file_size = ftell(f);
331
332 fseek(f, 0, SEEK_SET);
333
334 if (!(compressed_buf = g_try_malloc(file_size))) {
335 sr_err("asix: %s: compressed_buf malloc failed", __func__);
336 return SR_ERR_MALLOC;
337 }
338
339 if (!(firmware = g_try_malloc(buffer_size))) {
340 sr_err("asix: %s: firmware malloc failed", __func__);
341 return SR_ERR_MALLOC;
342 }
343
344 csize = 0;
345 while ((c = getc(f)) != EOF) {
346 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
347 compressed_buf[csize++] = c ^ imm;
348 }
349 fclose(f);
350
351 fwsize = buffer_size;
352 ret = uncompress(firmware, &fwsize, compressed_buf, csize);
353 if (ret < 0) {
354 g_free(compressed_buf);
355 g_free(firmware);
356 sr_warn("Could not unpack Sigma firmware. (Error %d)\n", ret);
357 return SR_ERR;
358 }
359
360 g_free(compressed_buf);
361
362 *buf_size = fwsize * 2 * 8;
363
364 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
365 if (!p) {
366 sr_err("asix: %s: buf/p malloc failed", __func__);
367 return SR_ERR_MALLOC;
368 }
369
370 for (i = 0; i < fwsize; ++i) {
371 for (bit = 7; bit >= 0; --bit) {
372 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
373 p[offset++] = v | 0x01;
374 p[offset++] = v;
375 }
376 }
377
378 g_free(firmware);
379
380 if (offset != *buf_size) {
381 g_free(*buf);
382 sr_warn("Error reading firmware %s "
383 "offset=%ld, file_size=%ld, buf_size=%zd\n",
384 filename, offset, file_size, *buf_size);
385
386 return SR_ERR;
387 }
388
389 return SR_OK;
390}
391
392static int hw_init(const char *deviceinfo)
393{
394 struct sr_device_instance *sdi;
395 struct sigma *sigma;
396
397 /* Avoid compiler warnings. */
398 deviceinfo = deviceinfo;
399
400 if (!(sigma = g_try_malloc(sizeof(struct sigma)))) {
401 sr_err("asix: %s: sigma malloc failed", __func__);
402 return 0; /* FIXME: Should be SR_ERR_MALLOC. */
403 }
404
405 ftdi_init(&sigma->ftdic);
406
407 /* Look for SIGMAs. */
408 if (ftdi_usb_open_desc(&sigma->ftdic, USB_VENDOR, USB_PRODUCT,
409 USB_DESCRIPTION, NULL) < 0)
410 goto free;
411
412 sigma->cur_samplerate = 0;
413 sigma->limit_msec = 0;
414 sigma->cur_firmware = -1;
415 sigma->num_probes = 0;
416 sigma->samples_per_event = 0;
417 sigma->capture_ratio = 50;
418 sigma->use_triggers = 0;
419
420 /* Register SIGMA device. */
421 sdi = sr_device_instance_new(0, SR_ST_INITIALIZING,
422 USB_VENDOR_NAME, USB_MODEL_NAME, USB_MODEL_VERSION);
423 if (!sdi)
424 goto free;
425
426 sdi->priv = sigma;
427
428 device_instances = g_slist_append(device_instances, sdi);
429
430 /* We will open the device again when we need it. */
431 ftdi_usb_close(&sigma->ftdic);
432
433 return 1;
434free:
435 free(sigma);
436 return 0;
437}
438
439static int upload_firmware(int firmware_idx, struct sigma *sigma)
440{
441 int ret;
442 unsigned char *buf;
443 unsigned char pins;
444 size_t buf_size;
445 unsigned char result[32];
446 char firmware_path[128];
447
448 /* Make sure it's an ASIX SIGMA. */
449 if ((ret = ftdi_usb_open_desc(&sigma->ftdic,
450 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
451 sr_warn("ftdi_usb_open failed: %s",
452 ftdi_get_error_string(&sigma->ftdic));
453 return 0;
454 }
455
456 if ((ret = ftdi_set_bitmode(&sigma->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
457 sr_warn("ftdi_set_bitmode failed: %s",
458 ftdi_get_error_string(&sigma->ftdic));
459 return 0;
460 }
461
462 /* Four times the speed of sigmalogan - Works well. */
463 if ((ret = ftdi_set_baudrate(&sigma->ftdic, 750000)) < 0) {
464 sr_warn("ftdi_set_baudrate failed: %s",
465 ftdi_get_error_string(&sigma->ftdic));
466 return 0;
467 }
468
469 /* Force the FPGA to reboot. */
470 sigma_write(suicide, sizeof(suicide), sigma);
471 sigma_write(suicide, sizeof(suicide), sigma);
472 sigma_write(suicide, sizeof(suicide), sigma);
473 sigma_write(suicide, sizeof(suicide), sigma);
474
475 /* Prepare to upload firmware (FPGA specific). */
476 sigma_write(init, sizeof(init), sigma);
477
478 ftdi_usb_purge_buffers(&sigma->ftdic);
479
480 /* Wait until the FPGA asserts INIT_B. */
481 while (1) {
482 ret = sigma_read(result, 1, sigma);
483 if (result[0] & 0x20)
484 break;
485 }
486
487 /* Prepare firmware. */
488 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
489 firmware_files[firmware_idx]);
490
491 if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
492 sr_warn("An error occured while reading the firmware: %s",
493 firmware_path);
494 return ret;
495 }
496
497 /* Upload firmare. */
498 sigma_write(buf, buf_size, sigma);
499
500 g_free(buf);
501
502 if ((ret = ftdi_set_bitmode(&sigma->ftdic, 0x00, BITMODE_RESET)) < 0) {
503 sr_warn("ftdi_set_bitmode failed: %s",
504 ftdi_get_error_string(&sigma->ftdic));
505 return SR_ERR;
506 }
507
508 ftdi_usb_purge_buffers(&sigma->ftdic);
509
510 /* Discard garbage. */
511 while (1 == sigma_read(&pins, 1, sigma))
512 ;
513
514 /* Initialize the logic analyzer mode. */
515 sigma_write(logic_mode_start, sizeof(logic_mode_start), sigma);
516
517 /* Expect a 3 byte reply. */
518 ret = sigma_read(result, 3, sigma);
519 if (ret != 3 ||
520 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
521 sr_warn("Configuration failed. Invalid reply received.");
522 return SR_ERR;
523 }
524
525 sigma->cur_firmware = firmware_idx;
526
527 return SR_OK;
528}
529
530static int hw_opendev(int device_index)
531{
532 struct sr_device_instance *sdi;
533 struct sigma *sigma;
534 int ret;
535
536 if (!(sdi = sr_get_device_instance(device_instances, device_index)))
537 return SR_ERR;
538
539 sigma = sdi->priv;
540
541 /* Make sure it's an ASIX SIGMA. */
542 if ((ret = ftdi_usb_open_desc(&sigma->ftdic,
543 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
544
545 sr_warn("ftdi_usb_open failed: %s",
546 ftdi_get_error_string(&sigma->ftdic));
547
548 return 0;
549 }
550
551 sdi->status = SR_ST_ACTIVE;
552
553 return SR_OK;
554}
555
556static int set_samplerate(struct sr_device_instance *sdi,
557 uint64_t samplerate)
558{
559 int i, ret;
560 struct sigma *sigma = sdi->priv;
561
562 for (i = 0; supported_samplerates[i]; i++) {
563 if (supported_samplerates[i] == samplerate)
564 break;
565 }
566 if (supported_samplerates[i] == 0)
567 return SR_ERR_SAMPLERATE;
568
569 if (samplerate <= SR_MHZ(50)) {
570 ret = upload_firmware(0, sigma);
571 sigma->num_probes = 16;
572 }
573 if (samplerate == SR_MHZ(100)) {
574 ret = upload_firmware(1, sigma);
575 sigma->num_probes = 8;
576 }
577 else if (samplerate == SR_MHZ(200)) {
578 ret = upload_firmware(2, sigma);
579 sigma->num_probes = 4;
580 }
581
582 sigma->cur_samplerate = samplerate;
583 sigma->samples_per_event = 16 / sigma->num_probes;
584 sigma->state.state = SIGMA_IDLE;
585
586 sr_info("Firmware uploaded");
587
588 return ret;
589}
590
591/*
592 * In 100 and 200 MHz mode, only a single pin rising/falling can be
593 * set as trigger. In other modes, two rising/falling triggers can be set,
594 * in addition to value/mask trigger for any number of probes.
595 *
596 * The Sigma supports complex triggers using boolean expressions, but this
597 * has not been implemented yet.
598 */
599static int configure_probes(struct sr_device_instance *sdi, GSList *probes)
600{
601 struct sigma *sigma = sdi->priv;
602 struct sr_probe *probe;
603 GSList *l;
604 int trigger_set = 0;
605 int probebit;
606
607 memset(&sigma->trigger, 0, sizeof(struct sigma_trigger));
608
609 for (l = probes; l; l = l->next) {
610 probe = (struct sr_probe *)l->data;
611 probebit = 1 << (probe->index - 1);
612
613 if (!probe->enabled || !probe->trigger)
614 continue;
615
616 if (sigma->cur_samplerate >= SR_MHZ(100)) {
617 /* Fast trigger support. */
618 if (trigger_set) {
619 sr_warn("Asix Sigma only supports a single "
620 "pin trigger in 100 and 200MHz mode.");
621 return SR_ERR;
622 }
623 if (probe->trigger[0] == 'f')
624 sigma->trigger.fallingmask |= probebit;
625 else if (probe->trigger[0] == 'r')
626 sigma->trigger.risingmask |= probebit;
627 else {
628 sr_warn("Asix Sigma only supports "
629 "rising/falling trigger in 100 "
630 "and 200MHz mode.");
631 return SR_ERR;
632 }
633
634 ++trigger_set;
635 } else {
636 /* Simple trigger support (event). */
637 if (probe->trigger[0] == '1') {
638 sigma->trigger.simplevalue |= probebit;
639 sigma->trigger.simplemask |= probebit;
640 }
641 else if (probe->trigger[0] == '0') {
642 sigma->trigger.simplevalue &= ~probebit;
643 sigma->trigger.simplemask |= probebit;
644 }
645 else if (probe->trigger[0] == 'f') {
646 sigma->trigger.fallingmask |= probebit;
647 ++trigger_set;
648 }
649 else if (probe->trigger[0] == 'r') {
650 sigma->trigger.risingmask |= probebit;
651 ++trigger_set;
652 }
653
654 /*
655 * Actually, Sigma supports 2 rising/falling triggers,
656 * but they are ORed and the current trigger syntax
657 * does not permit ORed triggers.
658 */
659 if (trigger_set > 1) {
660 sr_warn("Asix Sigma only supports 1 rising/"
661 "falling triggers.");
662 return SR_ERR;
663 }
664 }
665
666 if (trigger_set)
667 sigma->use_triggers = 1;
668 }
669
670 return SR_OK;
671}
672
673static void hw_closedev(int device_index)
674{
675 struct sr_device_instance *sdi;
676 struct sigma *sigma;
677
678 if ((sdi = sr_get_device_instance(device_instances, device_index)))
679 {
680 sigma = sdi->priv;
681 if (sdi->status == SR_ST_ACTIVE)
682 ftdi_usb_close(&sigma->ftdic);
683
684 sdi->status = SR_ST_INACTIVE;
685 }
686}
687
688static void hw_cleanup(void)
689{
690 GSList *l;
691 struct sr_device_instance *sdi;
692
693 /* Properly close all devices. */
694 for (l = device_instances; l; l = l->next) {
695 sdi = l->data;
696 if (sdi->priv != NULL)
697 free(sdi->priv);
698 sr_device_instance_free(sdi);
699 }
700 g_slist_free(device_instances);
701 device_instances = NULL;
702}
703
704static void *hw_get_device_info(int device_index, int device_info_id)
705{
706 struct sr_device_instance *sdi;
707 struct sigma *sigma;
708 void *info = NULL;
709
710 if (!(sdi = sr_get_device_instance(device_instances, device_index))) {
711 fprintf(stderr, "It's NULL.\n");
712 return NULL;
713 }
714
715 sigma = sdi->priv;
716
717 switch (device_info_id) {
718 case SR_DI_INSTANCE:
719 info = sdi;
720 break;
721 case SR_DI_NUM_PROBES:
722 info = GINT_TO_POINTER(16);
723 break;
724 case SR_DI_SAMPLERATES:
725 info = &samplerates;
726 break;
727 case SR_DI_TRIGGER_TYPES:
728 info = (char *)TRIGGER_TYPES;
729 break;
730 case SR_DI_CUR_SAMPLERATE:
731 info = &sigma->cur_samplerate;
732 break;
733 }
734
735 return info;
736}
737
738static int hw_get_status(int device_index)
739{
740 struct sr_device_instance *sdi;
741
742 sdi = sr_get_device_instance(device_instances, device_index);
743 if (sdi)
744 return sdi->status;
745 else
746 return SR_ST_NOT_FOUND;
747}
748
749static int *hw_get_capabilities(void)
750{
751 return capabilities;
752}
753
754static int hw_set_configuration(int device_index, int capability, void *value)
755{
756 struct sr_device_instance *sdi;
757 struct sigma *sigma;
758 int ret;
759
760 if (!(sdi = sr_get_device_instance(device_instances, device_index)))
761 return SR_ERR;
762
763 sigma = sdi->priv;
764
765 if (capability == SR_HWCAP_SAMPLERATE) {
766 ret = set_samplerate(sdi, *(uint64_t*) value);
767 } else if (capability == SR_HWCAP_PROBECONFIG) {
768 ret = configure_probes(sdi, value);
769 } else if (capability == SR_HWCAP_LIMIT_MSEC) {
770 sigma->limit_msec = *(uint64_t*) value;
771 if (sigma->limit_msec > 0)
772 ret = SR_OK;
773 else
774 ret = SR_ERR;
775 } else if (capability == SR_HWCAP_CAPTURE_RATIO) {
776 sigma->capture_ratio = *(uint64_t*) value;
777 if (sigma->capture_ratio < 0 || sigma->capture_ratio > 100)
778 ret = SR_ERR;
779 else
780 ret = SR_OK;
781 } else {
782 ret = SR_ERR;
783 }
784
785 return ret;
786}
787
788/* Software trigger to determine exact trigger position. */
789static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
790 struct sigma_trigger *t)
791{
792 int i;
793
794 for (i = 0; i < 8; ++i) {
795 if (i > 0)
796 last_sample = samples[i-1];
797
798 /* Simple triggers. */
799 if ((samples[i] & t->simplemask) != t->simplevalue)
800 continue;
801
802 /* Rising edge. */
803 if ((last_sample & t->risingmask) != 0 || (samples[i] &
804 t->risingmask) != t->risingmask)
805 continue;
806
807 /* Falling edge. */
808 if ((last_sample & t->fallingmask) != t->fallingmask ||
809 (samples[i] & t->fallingmask) != 0)
810 continue;
811
812 break;
813 }
814
815 /* If we did not match, return original trigger pos. */
816 return i & 0x7;
817}
818
819/*
820 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
821 * Each event is 20ns apart, and can contain multiple samples.
822 *
823 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
824 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
825 * For 50 MHz and below, events contain one sample for each channel,
826 * spread 20 ns apart.
827 */
828static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
829 uint16_t *lastsample, int triggerpos,
830 uint16_t limit_chunk, void *user_data)
831{
832 struct sr_device_instance *sdi = user_data;
833 struct sigma *sigma = sdi->priv;
834 uint16_t tsdiff, ts;
835 uint16_t samples[65536 * sigma->samples_per_event];
836 struct sr_datafeed_packet packet;
837 int i, j, k, l, numpad, tosend;
838 size_t n = 0, sent = 0;
839 int clustersize = EVENTS_PER_CLUSTER * sigma->samples_per_event;
840 uint16_t *event;
841 uint16_t cur_sample;
842 int triggerts = -1;
843
844 /* Check if trigger is in this chunk. */
845 if (triggerpos != -1) {
846 if (sigma->cur_samplerate <= SR_MHZ(50))
847 triggerpos -= EVENTS_PER_CLUSTER - 1;
848
849 if (triggerpos < 0)
850 triggerpos = 0;
851
852 /* Find in which cluster the trigger occured. */
853 triggerts = triggerpos / 7;
854 }
855
856 /* For each ts. */
857 for (i = 0; i < 64; ++i) {
858 ts = *(uint16_t *) &buf[i * 16];
859 tsdiff = ts - *lastts;
860 *lastts = ts;
861
862 /* Decode partial chunk. */
863 if (limit_chunk && ts > limit_chunk)
864 return SR_OK;
865
866 /* Pad last sample up to current point. */
867 numpad = tsdiff * sigma->samples_per_event - clustersize;
868 if (numpad > 0) {
869 for (j = 0; j < numpad; ++j)
870 samples[j] = *lastsample;
871
872 n = numpad;
873 }
874
875 /* Send samples between previous and this timestamp to sigrok. */
876 sent = 0;
877 while (sent < n) {
878 tosend = MIN(2048, n - sent);
879
880 packet.type = SR_DF_LOGIC;
881 packet.length = tosend * sizeof(uint16_t);
882 packet.unitsize = 2;
883 packet.payload = samples + sent;
884 sr_session_bus(sigma->session_id, &packet);
885
886 sent += tosend;
887 }
888 n = 0;
889
890 event = (uint16_t *) &buf[i * 16 + 2];
891 cur_sample = 0;
892
893 /* For each event in cluster. */
894 for (j = 0; j < 7; ++j) {
895
896 /* For each sample in event. */
897 for (k = 0; k < sigma->samples_per_event; ++k) {
898 cur_sample = 0;
899
900 /* For each probe. */
901 for (l = 0; l < sigma->num_probes; ++l)
902 cur_sample |= (!!(event[j] & (1 << (l *
903 sigma->samples_per_event
904 + k))))
905 << l;
906
907 samples[n++] = cur_sample;
908 }
909 }
910
911 /* Send data up to trigger point (if triggered). */
912 sent = 0;
913 if (i == triggerts) {
914 /*
915 * Trigger is not always accurate to sample because of
916 * pipeline delay. However, it always triggers before
917 * the actual event. We therefore look at the next
918 * samples to pinpoint the exact position of the trigger.
919 */
920 tosend = get_trigger_offset(samples, *lastsample,
921 &sigma->trigger);
922
923 if (tosend > 0) {
924 packet.type = SR_DF_LOGIC;
925 packet.length = tosend * sizeof(uint16_t);
926 packet.unitsize = 2;
927 packet.payload = samples;
928 sr_session_bus(sigma->session_id, &packet);
929
930 sent += tosend;
931 }
932
933 /* Only send trigger if explicitly enabled. */
934 if (sigma->use_triggers) {
935 packet.type = SR_DF_TRIGGER;
936 packet.length = 0;
937 packet.payload = 0;
938 sr_session_bus(sigma->session_id, &packet);
939 }
940 }
941
942 /* Send rest of the chunk to sigrok. */
943 tosend = n - sent;
944
945 if (tosend > 0) {
946 packet.type = SR_DF_LOGIC;
947 packet.length = tosend * sizeof(uint16_t);
948 packet.unitsize = 2;
949 packet.payload = samples + sent;
950 sr_session_bus(sigma->session_id, &packet);
951 }
952
953 *lastsample = samples[n - 1];
954 }
955
956 return SR_OK;
957}
958
959static int receive_data(int fd, int revents, void *user_data)
960{
961 struct sr_device_instance *sdi = user_data;
962 struct sigma *sigma = sdi->priv;
963 struct sr_datafeed_packet packet;
964 const int chunks_per_read = 32;
965 unsigned char buf[chunks_per_read * CHUNK_SIZE];
966 int bufsz, numchunks, i, newchunks;
967 uint64_t running_msec;
968 struct timeval tv;
969
970 fd = fd;
971 revents = revents;
972
973 numchunks = (sigma->state.stoppos + 511) / 512;
974
975 if (sigma->state.state == SIGMA_IDLE)
976 return FALSE;
977
978 if (sigma->state.state == SIGMA_CAPTURE) {
979
980 /* Check if the timer has expired, or memory is full. */
981 gettimeofday(&tv, 0);
982 running_msec = (tv.tv_sec - sigma->start_tv.tv_sec) * 1000 +
983 (tv.tv_usec - sigma->start_tv.tv_usec) / 1000;
984
985 if (running_msec < sigma->limit_msec && numchunks < 32767)
986 return FALSE;
987
988 hw_stop_acquisition(sdi->index, user_data);
989
990 return FALSE;
991
992 } else if (sigma->state.state == SIGMA_DOWNLOAD) {
993 if (sigma->state.chunks_downloaded >= numchunks) {
994 /* End of samples. */
995 packet.type = SR_DF_END;
996 packet.length = 0;
997 sr_session_bus(sigma->session_id, &packet);
998
999 sigma->state.state = SIGMA_IDLE;
1000
1001 return TRUE;
1002 }
1003
1004 newchunks = MIN(chunks_per_read,
1005 numchunks - sigma->state.chunks_downloaded);
1006
1007 sr_info("Downloading sample data: %.0f %%",
1008 100.0 * sigma->state.chunks_downloaded / numchunks);
1009
1010 bufsz = sigma_read_dram(sigma->state.chunks_downloaded,
1011 newchunks, buf, sigma);
1012
1013 /* Find first ts. */
1014 if (sigma->state.chunks_downloaded == 0) {
1015 sigma->state.lastts = *(uint16_t *) buf - 1;
1016 sigma->state.lastsample = 0;
1017 }
1018
1019 /* Decode chunks and send them to sigrok. */
1020 for (i = 0; i < newchunks; ++i) {
1021 int limit_chunk = 0;
1022
1023 /* The last chunk may potentially be only in part. */
1024 if (sigma->state.chunks_downloaded == numchunks - 1)
1025 {
1026 /* Find the last valid timestamp */
1027 limit_chunk = sigma->state.stoppos % 512 + sigma->state.lastts;
1028 }
1029
1030 if (sigma->state.chunks_downloaded + i == sigma->state.triggerchunk)
1031 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1032 &sigma->state.lastts,
1033 &sigma->state.lastsample,
1034 sigma->state.triggerpos & 0x1ff,
1035 limit_chunk, user_data);
1036 else
1037 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1038 &sigma->state.lastts,
1039 &sigma->state.lastsample,
1040 -1, limit_chunk, user_data);
1041
1042 ++sigma->state.chunks_downloaded;
1043 }
1044 }
1045
1046 return TRUE;
1047}
1048
1049/* Build a LUT entry used by the trigger functions. */
1050static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1051{
1052 int i, j, k, bit;
1053
1054 /* For each quad probe. */
1055 for (i = 0; i < 4; ++i) {
1056 entry[i] = 0xffff;
1057
1058 /* For each bit in LUT. */
1059 for (j = 0; j < 16; ++j)
1060
1061 /* For each probe in quad. */
1062 for (k = 0; k < 4; ++k) {
1063 bit = 1 << (i * 4 + k);
1064
1065 /* Set bit in entry */
1066 if ((mask & bit) &&
1067 ((!(value & bit)) !=
1068 (!(j & (1 << k)))))
1069 entry[i] &= ~(1 << j);
1070 }
1071 }
1072}
1073
1074/* Add a logical function to LUT mask. */
1075static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1076 int index, int neg, uint16_t *mask)
1077{
1078 int i, j;
1079 int x[2][2], tmp, a, b, aset, bset, rset;
1080
1081 memset(x, 0, 4 * sizeof(int));
1082
1083 /* Trigger detect condition. */
1084 switch (oper) {
1085 case OP_LEVEL:
1086 x[0][1] = 1;
1087 x[1][1] = 1;
1088 break;
1089 case OP_NOT:
1090 x[0][0] = 1;
1091 x[1][0] = 1;
1092 break;
1093 case OP_RISE:
1094 x[0][1] = 1;
1095 break;
1096 case OP_FALL:
1097 x[1][0] = 1;
1098 break;
1099 case OP_RISEFALL:
1100 x[0][1] = 1;
1101 x[1][0] = 1;
1102 break;
1103 case OP_NOTRISE:
1104 x[1][1] = 1;
1105 x[0][0] = 1;
1106 x[1][0] = 1;
1107 break;
1108 case OP_NOTFALL:
1109 x[1][1] = 1;
1110 x[0][0] = 1;
1111 x[0][1] = 1;
1112 break;
1113 case OP_NOTRISEFALL:
1114 x[1][1] = 1;
1115 x[0][0] = 1;
1116 break;
1117 }
1118
1119 /* Transpose if neg is set. */
1120 if (neg) {
1121 for (i = 0; i < 2; ++i)
1122 for (j = 0; j < 2; ++j) {
1123 tmp = x[i][j];
1124 x[i][j] = x[1-i][1-j];
1125 x[1-i][1-j] = tmp;
1126 }
1127 }
1128
1129 /* Update mask with function. */
1130 for (i = 0; i < 16; ++i) {
1131 a = (i >> (2 * index + 0)) & 1;
1132 b = (i >> (2 * index + 1)) & 1;
1133
1134 aset = (*mask >> i) & 1;
1135 bset = x[b][a];
1136
1137 if (func == FUNC_AND || func == FUNC_NAND)
1138 rset = aset & bset;
1139 else if (func == FUNC_OR || func == FUNC_NOR)
1140 rset = aset | bset;
1141 else if (func == FUNC_XOR || func == FUNC_NXOR)
1142 rset = aset ^ bset;
1143
1144 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1145 rset = !rset;
1146
1147 *mask &= ~(1 << i);
1148
1149 if (rset)
1150 *mask |= 1 << i;
1151 }
1152}
1153
1154/*
1155 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1156 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1157 * set at any time, but a full mask and value can be set (0/1).
1158 */
1159static int build_basic_trigger(struct triggerlut *lut, struct sigma *sigma)
1160{
1161 int i,j;
1162 uint16_t masks[2] = { 0, 0 };
1163
1164 memset(lut, 0, sizeof(struct triggerlut));
1165
1166 /* Contant for simple triggers. */
1167 lut->m4 = 0xa000;
1168
1169 /* Value/mask trigger support. */
1170 build_lut_entry(sigma->trigger.simplevalue, sigma->trigger.simplemask,
1171 lut->m2d);
1172
1173 /* Rise/fall trigger support. */
1174 for (i = 0, j = 0; i < 16; ++i) {
1175 if (sigma->trigger.risingmask & (1 << i) ||
1176 sigma->trigger.fallingmask & (1 << i))
1177 masks[j++] = 1 << i;
1178 }
1179
1180 build_lut_entry(masks[0], masks[0], lut->m0d);
1181 build_lut_entry(masks[1], masks[1], lut->m1d);
1182
1183 /* Add glue logic */
1184 if (masks[0] || masks[1]) {
1185 /* Transition trigger. */
1186 if (masks[0] & sigma->trigger.risingmask)
1187 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1188 if (masks[0] & sigma->trigger.fallingmask)
1189 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1190 if (masks[1] & sigma->trigger.risingmask)
1191 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1192 if (masks[1] & sigma->trigger.fallingmask)
1193 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1194 } else {
1195 /* Only value/mask trigger. */
1196 lut->m3 = 0xffff;
1197 }
1198
1199 /* Triggertype: event. */
1200 lut->params.selres = 3;
1201
1202 return SR_OK;
1203}
1204
1205static int hw_start_acquisition(int device_index, gpointer session_device_id)
1206{
1207 struct sr_device_instance *sdi;
1208 struct sigma *sigma;
1209 struct sr_datafeed_packet packet;
1210 struct sr_datafeed_header header;
1211 struct clockselect_50 clockselect;
1212 int frac, triggerpin, ret;
1213 uint8_t triggerselect;
1214 struct triggerinout triggerinout_conf;
1215 struct triggerlut lut;
1216
1217 session_device_id = session_device_id;
1218
1219 if (!(sdi = sr_get_device_instance(device_instances, device_index)))
1220 return SR_ERR;
1221
1222 sigma = sdi->priv;
1223
1224 /* If the samplerate has not been set, default to 200 KHz. */
1225 if (sigma->cur_firmware == -1) {
1226 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1227 return ret;
1228 }
1229
1230 /* Enter trigger programming mode. */
1231 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, sigma);
1232
1233 /* 100 and 200 MHz mode. */
1234 if (sigma->cur_samplerate >= SR_MHZ(100)) {
1235 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, sigma);
1236
1237 /* Find which pin to trigger on from mask. */
1238 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1239 if ((sigma->trigger.risingmask | sigma->trigger.fallingmask) &
1240 (1 << triggerpin))
1241 break;
1242
1243 /* Set trigger pin and light LED on trigger. */
1244 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1245
1246 /* Default rising edge. */
1247 if (sigma->trigger.fallingmask)
1248 triggerselect |= 1 << 3;
1249
1250 /* All other modes. */
1251 } else if (sigma->cur_samplerate <= SR_MHZ(50)) {
1252 build_basic_trigger(&lut, sigma);
1253
1254 sigma_write_trigger_lut(&lut, sigma);
1255
1256 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1257 }
1258
1259 /* Setup trigger in and out pins to default values. */
1260 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1261 triggerinout_conf.trgout_bytrigger = 1;
1262 triggerinout_conf.trgout_enable = 1;
1263
1264 sigma_write_register(WRITE_TRIGGER_OPTION,
1265 (uint8_t *) &triggerinout_conf,
1266 sizeof(struct triggerinout), sigma);
1267
1268 /* Go back to normal mode. */
1269 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, sigma);
1270
1271 /* Set clock select register. */
1272 if (sigma->cur_samplerate == SR_MHZ(200))
1273 /* Enable 4 probes. */
1274 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, sigma);
1275 else if (sigma->cur_samplerate == SR_MHZ(100))
1276 /* Enable 8 probes. */
1277 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, sigma);
1278 else {
1279 /*
1280 * 50 MHz mode (or fraction thereof). Any fraction down to
1281 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1282 */
1283 frac = SR_MHZ(50) / sigma->cur_samplerate - 1;
1284
1285 clockselect.async = 0;
1286 clockselect.fraction = frac;
1287 clockselect.disabled_probes = 0;
1288
1289 sigma_write_register(WRITE_CLOCK_SELECT,
1290 (uint8_t *) &clockselect,
1291 sizeof(clockselect), sigma);
1292 }
1293
1294 /* Setup maximum post trigger time. */
1295 sigma_set_register(WRITE_POST_TRIGGER,
1296 (sigma->capture_ratio * 255) / 100, sigma);
1297
1298 /* Start acqusition. */
1299 gettimeofday(&sigma->start_tv, 0);
1300 sigma_set_register(WRITE_MODE, 0x0d, sigma);
1301
1302 sigma->session_id = session_device_id;
1303
1304 /* Send header packet to the session bus. */
1305 packet.type = SR_DF_HEADER;
1306 packet.length = sizeof(struct sr_datafeed_header);
1307 packet.payload = &header;
1308 header.feed_version = 1;
1309 gettimeofday(&header.starttime, NULL);
1310 header.samplerate = sigma->cur_samplerate;
1311 header.protocol_id = SR_PROTO_RAW;
1312 header.num_logic_probes = sigma->num_probes;
1313 header.num_analog_probes = 0;
1314 sr_session_bus(session_device_id, &packet);
1315
1316 /* Add capture source. */
1317 sr_source_add(0, G_IO_IN, 10, receive_data, sdi);
1318
1319 sigma->state.state = SIGMA_CAPTURE;
1320
1321 return SR_OK;
1322}
1323
1324static void hw_stop_acquisition(int device_index, gpointer session_device_id)
1325{
1326 struct sr_device_instance *sdi;
1327 struct sigma *sigma;
1328 uint8_t modestatus;
1329
1330 if (!(sdi = sr_get_device_instance(device_instances, device_index)))
1331 return;
1332
1333 sigma = sdi->priv;
1334
1335 session_device_id = session_device_id;
1336
1337 /* Stop acquisition. */
1338 sigma_set_register(WRITE_MODE, 0x11, sigma);
1339
1340 /* Set SDRAM Read Enable. */
1341 sigma_set_register(WRITE_MODE, 0x02, sigma);
1342
1343 /* Get the current position. */
1344 sigma_read_pos(&sigma->state.stoppos, &sigma->state.triggerpos, sigma);
1345
1346 /* Check if trigger has fired. */
1347 modestatus = sigma_get_register(READ_MODE, sigma);
1348 if (modestatus & 0x20) {
1349 sigma->state.triggerchunk = sigma->state.triggerpos / 512;
1350
1351 } else
1352 sigma->state.triggerchunk = -1;
1353
1354 sigma->state.chunks_downloaded = 0;
1355
1356 sigma->state.state = SIGMA_DOWNLOAD;
1357}
1358
1359struct sr_device_plugin asix_sigma_plugin_info = {
1360 "asix-sigma",
1361 "ASIX SIGMA",
1362 1,
1363 hw_init,
1364 hw_cleanup,
1365 hw_opendev,
1366 hw_closedev,
1367 hw_get_device_info,
1368 hw_get_status,
1369 hw_get_capabilities,
1370 hw_set_configuration,
1371 hw_start_acquisition,
1372 hw_stop_acquisition,
1373};
Hardware access and backend lib