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chronovu-la8: use driver struct-based device instance list
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1/*
2 * This file is part of the sigrok project.
3 *
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22/*
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
24 */
25
26#include <glib.h>
27#include <glib/gstdio.h>
28#include <ftdi.h>
29#include <string.h>
30#include "libsigrok.h"
31#include "libsigrok-internal.h"
32#include "asix-sigma.h"
33
34#define USB_VENDOR 0xa600
35#define USB_PRODUCT 0xa000
36#define USB_DESCRIPTION "ASIX SIGMA"
37#define USB_VENDOR_NAME "ASIX"
38#define USB_MODEL_NAME "SIGMA"
39#define USB_MODEL_VERSION ""
40#define TRIGGER_TYPES "rf10"
41#define NUM_PROBES 16
42
43static GSList *dev_insts = NULL;
44
45static const uint64_t supported_samplerates[] = {
46 SR_KHZ(200),
47 SR_KHZ(250),
48 SR_KHZ(500),
49 SR_MHZ(1),
50 SR_MHZ(5),
51 SR_MHZ(10),
52 SR_MHZ(25),
53 SR_MHZ(50),
54 SR_MHZ(100),
55 SR_MHZ(200),
56 0,
57};
58
59/*
60 * Probe numbers seem to go from 1-16, according to this image:
61 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
62 * (the cable has two additional GND pins, and a TI and TO pin)
63 */
64static const char *probe_names[NUM_PROBES + 1] = {
65 "1",
66 "2",
67 "3",
68 "4",
69 "5",
70 "6",
71 "7",
72 "8",
73 "9",
74 "10",
75 "11",
76 "12",
77 "13",
78 "14",
79 "15",
80 "16",
81 NULL,
82};
83
84static const struct sr_samplerates samplerates = {
85 0,
86 0,
87 0,
88 supported_samplerates,
89};
90
91static const int hwcaps[] = {
92 SR_HWCAP_LOGIC_ANALYZER,
93 SR_HWCAP_SAMPLERATE,
94 SR_HWCAP_CAPTURE_RATIO,
95 SR_HWCAP_PROBECONFIG,
96
97 SR_HWCAP_LIMIT_MSEC,
98 0,
99};
100
101/* Force the FPGA to reboot. */
102static uint8_t suicide[] = {
103 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
104};
105
106/* Prepare to upload firmware (FPGA specific). */
107static uint8_t init[] = {
108 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
109};
110
111/* Initialize the logic analyzer mode. */
112static uint8_t logic_mode_start[] = {
113 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
114 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
115};
116
117static const char *firmware_files[] = {
118 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
119 "asix-sigma-100.fw", /* 100 MHz */
120 "asix-sigma-200.fw", /* 200 MHz */
121 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
122 "asix-sigma-phasor.fw", /* Frequency counter */
123};
124
125static int hw_dev_acquisition_stop(int dev_index, void *cb_data);
126
127static int sigma_read(void *buf, size_t size, struct context *ctx)
128{
129 int ret;
130
131 ret = ftdi_read_data(&ctx->ftdic, (unsigned char *)buf, size);
132 if (ret < 0) {
133 sr_err("sigma: ftdi_read_data failed: %s",
134 ftdi_get_error_string(&ctx->ftdic));
135 }
136
137 return ret;
138}
139
140static int sigma_write(void *buf, size_t size, struct context *ctx)
141{
142 int ret;
143
144 ret = ftdi_write_data(&ctx->ftdic, (unsigned char *)buf, size);
145 if (ret < 0) {
146 sr_err("sigma: ftdi_write_data failed: %s",
147 ftdi_get_error_string(&ctx->ftdic));
148 } else if ((size_t) ret != size) {
149 sr_err("sigma: ftdi_write_data did not complete write.");
150 }
151
152 return ret;
153}
154
155static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
156 struct context *ctx)
157{
158 size_t i;
159 uint8_t buf[len + 2];
160 int idx = 0;
161
162 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
163 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
164
165 for (i = 0; i < len; ++i) {
166 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
167 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
168 }
169
170 return sigma_write(buf, idx, ctx);
171}
172
173static int sigma_set_register(uint8_t reg, uint8_t value, struct context *ctx)
174{
175 return sigma_write_register(reg, &value, 1, ctx);
176}
177
178static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
179 struct context *ctx)
180{
181 uint8_t buf[3];
182
183 buf[0] = REG_ADDR_LOW | (reg & 0xf);
184 buf[1] = REG_ADDR_HIGH | (reg >> 4);
185 buf[2] = REG_READ_ADDR;
186
187 sigma_write(buf, sizeof(buf), ctx);
188
189 return sigma_read(data, len, ctx);
190}
191
192static uint8_t sigma_get_register(uint8_t reg, struct context *ctx)
193{
194 uint8_t value;
195
196 if (1 != sigma_read_register(reg, &value, 1, ctx)) {
197 sr_err("sigma: sigma_get_register: 1 byte expected");
198 return 0;
199 }
200
201 return value;
202}
203
204static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
205 struct context *ctx)
206{
207 uint8_t buf[] = {
208 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
209
210 REG_READ_ADDR | NEXT_REG,
211 REG_READ_ADDR | NEXT_REG,
212 REG_READ_ADDR | NEXT_REG,
213 REG_READ_ADDR | NEXT_REG,
214 REG_READ_ADDR | NEXT_REG,
215 REG_READ_ADDR | NEXT_REG,
216 };
217 uint8_t result[6];
218
219 sigma_write(buf, sizeof(buf), ctx);
220
221 sigma_read(result, sizeof(result), ctx);
222
223 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
224 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
225
226 /* Not really sure why this must be done, but according to spec. */
227 if ((--*stoppos & 0x1ff) == 0x1ff)
228 stoppos -= 64;
229
230 if ((*--triggerpos & 0x1ff) == 0x1ff)
231 triggerpos -= 64;
232
233 return 1;
234}
235
236static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
237 uint8_t *data, struct context *ctx)
238{
239 size_t i;
240 uint8_t buf[4096];
241 int idx = 0;
242
243 /* Send the startchunk. Index start with 1. */
244 buf[0] = startchunk >> 8;
245 buf[1] = startchunk & 0xff;
246 sigma_write_register(WRITE_MEMROW, buf, 2, ctx);
247
248 /* Read the DRAM. */
249 buf[idx++] = REG_DRAM_BLOCK;
250 buf[idx++] = REG_DRAM_WAIT_ACK;
251
252 for (i = 0; i < numchunks; ++i) {
253 /* Alternate bit to copy from DRAM to cache. */
254 if (i != (numchunks - 1))
255 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
256
257 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
258
259 if (i != (numchunks - 1))
260 buf[idx++] = REG_DRAM_WAIT_ACK;
261 }
262
263 sigma_write(buf, idx, ctx);
264
265 return sigma_read(data, numchunks * CHUNK_SIZE, ctx);
266}
267
268/* Upload trigger look-up tables to Sigma. */
269static int sigma_write_trigger_lut(struct triggerlut *lut, struct context *ctx)
270{
271 int i;
272 uint8_t tmp[2];
273 uint16_t bit;
274
275 /* Transpose the table and send to Sigma. */
276 for (i = 0; i < 16; ++i) {
277 bit = 1 << i;
278
279 tmp[0] = tmp[1] = 0;
280
281 if (lut->m2d[0] & bit)
282 tmp[0] |= 0x01;
283 if (lut->m2d[1] & bit)
284 tmp[0] |= 0x02;
285 if (lut->m2d[2] & bit)
286 tmp[0] |= 0x04;
287 if (lut->m2d[3] & bit)
288 tmp[0] |= 0x08;
289
290 if (lut->m3 & bit)
291 tmp[0] |= 0x10;
292 if (lut->m3s & bit)
293 tmp[0] |= 0x20;
294 if (lut->m4 & bit)
295 tmp[0] |= 0x40;
296
297 if (lut->m0d[0] & bit)
298 tmp[1] |= 0x01;
299 if (lut->m0d[1] & bit)
300 tmp[1] |= 0x02;
301 if (lut->m0d[2] & bit)
302 tmp[1] |= 0x04;
303 if (lut->m0d[3] & bit)
304 tmp[1] |= 0x08;
305
306 if (lut->m1d[0] & bit)
307 tmp[1] |= 0x10;
308 if (lut->m1d[1] & bit)
309 tmp[1] |= 0x20;
310 if (lut->m1d[2] & bit)
311 tmp[1] |= 0x40;
312 if (lut->m1d[3] & bit)
313 tmp[1] |= 0x80;
314
315 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
316 ctx);
317 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, ctx);
318 }
319
320 /* Send the parameters */
321 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
322 sizeof(lut->params), ctx);
323
324 return SR_OK;
325}
326
327/* Generate the bitbang stream for programming the FPGA. */
328static int bin2bitbang(const char *filename,
329 unsigned char **buf, size_t *buf_size)
330{
331 FILE *f;
332 unsigned long file_size;
333 unsigned long offset = 0;
334 unsigned char *p;
335 uint8_t *firmware;
336 unsigned long fwsize = 0;
337 const int buffer_size = 65536;
338 size_t i;
339 int c, bit, v;
340 uint32_t imm = 0x3f6df2ab;
341
342 f = g_fopen(filename, "rb");
343 if (!f) {
344 sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename);
345 return SR_ERR;
346 }
347
348 if (-1 == fseek(f, 0, SEEK_END)) {
349 sr_err("sigma: fseek on %s failed", filename);
350 fclose(f);
351 return SR_ERR;
352 }
353
354 file_size = ftell(f);
355
356 fseek(f, 0, SEEK_SET);
357
358 if (!(firmware = g_try_malloc(buffer_size))) {
359 sr_err("sigma: %s: firmware malloc failed", __func__);
360 fclose(f);
361 return SR_ERR_MALLOC;
362 }
363
364 while ((c = getc(f)) != EOF) {
365 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
366 firmware[fwsize++] = c ^ imm;
367 }
368 fclose(f);
369
370 if(fwsize != file_size) {
371 sr_err("sigma: %s: Error reading firmware", filename);
372 fclose(f);
373 g_free(firmware);
374 return SR_ERR;
375 }
376
377 *buf_size = fwsize * 2 * 8;
378
379 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
380 if (!p) {
381 sr_err("sigma: %s: buf/p malloc failed", __func__);
382 g_free(firmware);
383 return SR_ERR_MALLOC;
384 }
385
386 for (i = 0; i < fwsize; ++i) {
387 for (bit = 7; bit >= 0; --bit) {
388 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
389 p[offset++] = v | 0x01;
390 p[offset++] = v;
391 }
392 }
393
394 g_free(firmware);
395
396 if (offset != *buf_size) {
397 g_free(*buf);
398 sr_err("sigma: Error reading firmware %s "
399 "offset=%ld, file_size=%ld, buf_size=%zd.",
400 filename, offset, file_size, *buf_size);
401
402 return SR_ERR;
403 }
404
405 return SR_OK;
406}
407
408static int hw_init(void)
409{
410
411 /* Nothing to do. */
412
413 return SR_OK;
414}
415
416static int hw_scan(void)
417{
418 struct sr_dev_inst *sdi;
419 struct context *ctx;
420 struct ftdi_device_list *devlist;
421 char serial_txt[10];
422 uint32_t serial;
423
424 if (!(ctx = g_try_malloc(sizeof(struct context)))) {
425 sr_err("sigma: %s: ctx malloc failed", __func__);
426 return SR_ERR_MALLOC;
427 }
428
429 ftdi_init(&ctx->ftdic);
430
431 /* Look for SIGMAs. */
432
433 if (ftdi_usb_find_all(&ctx->ftdic, &devlist,
434 USB_VENDOR, USB_PRODUCT) <= 0)
435 goto free;
436
437 /* Make sure it's a version 1 or 2 SIGMA. */
438 ftdi_usb_get_strings(&ctx->ftdic, devlist->dev, NULL, 0, NULL, 0,
439 serial_txt, sizeof(serial_txt));
440 sscanf(serial_txt, "%x", &serial);
441
442 if (serial < 0xa6010000 || serial > 0xa602ffff) {
443 sr_err("sigma: Only SIGMA and SIGMA2 are supported "
444 "in this version of sigrok.");
445 goto free;
446 }
447
448 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
449
450 ctx->cur_samplerate = 0;
451 ctx->period_ps = 0;
452 ctx->limit_msec = 0;
453 ctx->cur_firmware = -1;
454 ctx->num_probes = 0;
455 ctx->samples_per_event = 0;
456 ctx->capture_ratio = 50;
457 ctx->use_triggers = 0;
458
459 /* Register SIGMA device. */
460 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
461 USB_MODEL_NAME, USB_MODEL_VERSION))) {
462 sr_err("sigma: %s: sdi was NULL", __func__);
463 goto free;
464 }
465
466 sdi->priv = ctx;
467
468 dev_insts = g_slist_append(dev_insts, sdi);
469
470 /* We will open the device again when we need it. */
471 ftdi_list_free(&devlist);
472
473 return 1;
474
475free:
476 g_free(ctx);
477 return 0;
478}
479
480static int upload_firmware(int firmware_idx, struct context *ctx)
481{
482 int ret;
483 unsigned char *buf;
484 unsigned char pins;
485 size_t buf_size;
486 unsigned char result[32];
487 char firmware_path[128];
488
489 /* Make sure it's an ASIX SIGMA. */
490 if ((ret = ftdi_usb_open_desc(&ctx->ftdic,
491 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
492 sr_err("sigma: ftdi_usb_open failed: %s",
493 ftdi_get_error_string(&ctx->ftdic));
494 return 0;
495 }
496
497 if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
498 sr_err("sigma: ftdi_set_bitmode failed: %s",
499 ftdi_get_error_string(&ctx->ftdic));
500 return 0;
501 }
502
503 /* Four times the speed of sigmalogan - Works well. */
504 if ((ret = ftdi_set_baudrate(&ctx->ftdic, 750000)) < 0) {
505 sr_err("sigma: ftdi_set_baudrate failed: %s",
506 ftdi_get_error_string(&ctx->ftdic));
507 return 0;
508 }
509
510 /* Force the FPGA to reboot. */
511 sigma_write(suicide, sizeof(suicide), ctx);
512 sigma_write(suicide, sizeof(suicide), ctx);
513 sigma_write(suicide, sizeof(suicide), ctx);
514 sigma_write(suicide, sizeof(suicide), ctx);
515
516 /* Prepare to upload firmware (FPGA specific). */
517 sigma_write(init, sizeof(init), ctx);
518
519 ftdi_usb_purge_buffers(&ctx->ftdic);
520
521 /* Wait until the FPGA asserts INIT_B. */
522 while (1) {
523 ret = sigma_read(result, 1, ctx);
524 if (result[0] & 0x20)
525 break;
526 }
527
528 /* Prepare firmware. */
529 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
530 firmware_files[firmware_idx]);
531
532 if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
533 sr_err("sigma: An error occured while reading the firmware: %s",
534 firmware_path);
535 return ret;
536 }
537
538 /* Upload firmare. */
539 sr_info("sigma: Uploading firmware %s", firmware_files[firmware_idx]);
540 sigma_write(buf, buf_size, ctx);
541
542 g_free(buf);
543
544 if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0x00, BITMODE_RESET)) < 0) {
545 sr_err("sigma: ftdi_set_bitmode failed: %s",
546 ftdi_get_error_string(&ctx->ftdic));
547 return SR_ERR;
548 }
549
550 ftdi_usb_purge_buffers(&ctx->ftdic);
551
552 /* Discard garbage. */
553 while (1 == sigma_read(&pins, 1, ctx))
554 ;
555
556 /* Initialize the logic analyzer mode. */
557 sigma_write(logic_mode_start, sizeof(logic_mode_start), ctx);
558
559 /* Expect a 3 byte reply. */
560 ret = sigma_read(result, 3, ctx);
561 if (ret != 3 ||
562 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
563 sr_err("sigma: Configuration failed. Invalid reply received.");
564 return SR_ERR;
565 }
566
567 ctx->cur_firmware = firmware_idx;
568
569 sr_info("sigma: Firmware uploaded");
570
571 return SR_OK;
572}
573
574static int hw_dev_open(int dev_index)
575{
576 struct sr_dev_inst *sdi;
577 struct context *ctx;
578 int ret;
579
580 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
581 return SR_ERR;
582
583 ctx = sdi->priv;
584
585 /* Make sure it's an ASIX SIGMA. */
586 if ((ret = ftdi_usb_open_desc(&ctx->ftdic,
587 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
588
589 sr_err("sigma: ftdi_usb_open failed: %s",
590 ftdi_get_error_string(&ctx->ftdic));
591
592 return 0;
593 }
594
595 sdi->status = SR_ST_ACTIVE;
596
597 return SR_OK;
598}
599
600static int set_samplerate(struct sr_dev_inst *sdi, uint64_t samplerate)
601{
602 int i, ret;
603 struct context *ctx = sdi->priv;
604
605 for (i = 0; supported_samplerates[i]; i++) {
606 if (supported_samplerates[i] == samplerate)
607 break;
608 }
609 if (supported_samplerates[i] == 0)
610 return SR_ERR_SAMPLERATE;
611
612 if (samplerate <= SR_MHZ(50)) {
613 ret = upload_firmware(0, ctx);
614 ctx->num_probes = 16;
615 }
616 if (samplerate == SR_MHZ(100)) {
617 ret = upload_firmware(1, ctx);
618 ctx->num_probes = 8;
619 }
620 else if (samplerate == SR_MHZ(200)) {
621 ret = upload_firmware(2, ctx);
622 ctx->num_probes = 4;
623 }
624
625 ctx->cur_samplerate = samplerate;
626 ctx->period_ps = 1000000000000 / samplerate;
627 ctx->samples_per_event = 16 / ctx->num_probes;
628 ctx->state.state = SIGMA_IDLE;
629
630 return ret;
631}
632
633/*
634 * In 100 and 200 MHz mode, only a single pin rising/falling can be
635 * set as trigger. In other modes, two rising/falling triggers can be set,
636 * in addition to value/mask trigger for any number of probes.
637 *
638 * The Sigma supports complex triggers using boolean expressions, but this
639 * has not been implemented yet.
640 */
641static int configure_probes(struct sr_dev_inst *sdi, const GSList *probes)
642{
643 struct context *ctx = sdi->priv;
644 const struct sr_probe *probe;
645 const GSList *l;
646 int trigger_set = 0;
647 int probebit;
648
649 memset(&ctx->trigger, 0, sizeof(struct sigma_trigger));
650
651 for (l = probes; l; l = l->next) {
652 probe = (struct sr_probe *)l->data;
653 probebit = 1 << (probe->index - 1);
654
655 if (!probe->enabled || !probe->trigger)
656 continue;
657
658 if (ctx->cur_samplerate >= SR_MHZ(100)) {
659 /* Fast trigger support. */
660 if (trigger_set) {
661 sr_err("sigma: ASIX SIGMA only supports a single "
662 "pin trigger in 100 and 200MHz mode.");
663 return SR_ERR;
664 }
665 if (probe->trigger[0] == 'f')
666 ctx->trigger.fallingmask |= probebit;
667 else if (probe->trigger[0] == 'r')
668 ctx->trigger.risingmask |= probebit;
669 else {
670 sr_err("sigma: ASIX SIGMA only supports "
671 "rising/falling trigger in 100 "
672 "and 200MHz mode.");
673 return SR_ERR;
674 }
675
676 ++trigger_set;
677 } else {
678 /* Simple trigger support (event). */
679 if (probe->trigger[0] == '1') {
680 ctx->trigger.simplevalue |= probebit;
681 ctx->trigger.simplemask |= probebit;
682 }
683 else if (probe->trigger[0] == '0') {
684 ctx->trigger.simplevalue &= ~probebit;
685 ctx->trigger.simplemask |= probebit;
686 }
687 else if (probe->trigger[0] == 'f') {
688 ctx->trigger.fallingmask |= probebit;
689 ++trigger_set;
690 }
691 else if (probe->trigger[0] == 'r') {
692 ctx->trigger.risingmask |= probebit;
693 ++trigger_set;
694 }
695
696 /*
697 * Actually, Sigma supports 2 rising/falling triggers,
698 * but they are ORed and the current trigger syntax
699 * does not permit ORed triggers.
700 */
701 if (trigger_set > 1) {
702 sr_err("sigma: ASIX SIGMA only supports 1 "
703 "rising/falling triggers.");
704 return SR_ERR;
705 }
706 }
707
708 if (trigger_set)
709 ctx->use_triggers = 1;
710 }
711
712 return SR_OK;
713}
714
715static int hw_dev_close(int dev_index)
716{
717 struct sr_dev_inst *sdi;
718 struct context *ctx;
719
720 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) {
721 sr_err("sigma: %s: sdi was NULL", __func__);
722 return SR_ERR_BUG;
723 }
724
725 if (!(ctx = sdi->priv)) {
726 sr_err("sigma: %s: sdi->priv was NULL", __func__);
727 return SR_ERR_BUG;
728 }
729
730 /* TODO */
731 if (sdi->status == SR_ST_ACTIVE)
732 ftdi_usb_close(&ctx->ftdic);
733
734 sdi->status = SR_ST_INACTIVE;
735
736 return SR_OK;
737}
738
739static int hw_cleanup(void)
740{
741 GSList *l;
742 struct sr_dev_inst *sdi;
743 int ret = SR_OK;
744
745 /* Properly close all devices. */
746 for (l = dev_insts; l; l = l->next) {
747 if (!(sdi = l->data)) {
748 /* Log error, but continue cleaning up the rest. */
749 sr_err("sigma: %s: sdi was NULL, continuing", __func__);
750 ret = SR_ERR_BUG;
751 continue;
752 }
753 sr_dev_inst_free(sdi);
754 }
755 g_slist_free(dev_insts);
756 dev_insts = NULL;
757
758 return ret;
759}
760
761static const void *hw_dev_info_get(int dev_index, int dev_info_id)
762{
763 struct sr_dev_inst *sdi;
764 struct context *ctx;
765 const void *info = NULL;
766
767 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) {
768 sr_err("sigma: %s: sdi was NULL", __func__);
769 return NULL;
770 }
771
772 ctx = sdi->priv;
773
774 switch (dev_info_id) {
775 case SR_DI_INST:
776 info = sdi;
777 break;
778 case SR_DI_NUM_PROBES:
779 info = GINT_TO_POINTER(NUM_PROBES);
780 break;
781 case SR_DI_PROBE_NAMES:
782 info = probe_names;
783 break;
784 case SR_DI_SAMPLERATES:
785 info = &samplerates;
786 break;
787 case SR_DI_TRIGGER_TYPES:
788 info = (char *)TRIGGER_TYPES;
789 break;
790 case SR_DI_CUR_SAMPLERATE:
791 info = &ctx->cur_samplerate;
792 break;
793 }
794
795 return info;
796}
797
798static int hw_dev_status_get(int dev_index)
799{
800 struct sr_dev_inst *sdi;
801
802 sdi = sr_dev_inst_get(dev_insts, dev_index);
803 if (sdi)
804 return sdi->status;
805 else
806 return SR_ST_NOT_FOUND;
807}
808
809static const int *hw_hwcap_get_all(void)
810{
811 return hwcaps;
812}
813
814static int hw_dev_config_set(int dev_index, int hwcap, const void *value)
815{
816 struct sr_dev_inst *sdi;
817 struct context *ctx;
818 int ret;
819
820 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
821 return SR_ERR;
822
823 ctx = sdi->priv;
824
825 if (hwcap == SR_HWCAP_SAMPLERATE) {
826 ret = set_samplerate(sdi, *(const uint64_t *)value);
827 } else if (hwcap == SR_HWCAP_PROBECONFIG) {
828 ret = configure_probes(sdi, value);
829 } else if (hwcap == SR_HWCAP_LIMIT_MSEC) {
830 ctx->limit_msec = *(const uint64_t *)value;
831 if (ctx->limit_msec > 0)
832 ret = SR_OK;
833 else
834 ret = SR_ERR;
835 } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) {
836 ctx->capture_ratio = *(const uint64_t *)value;
837 if (ctx->capture_ratio < 0 || ctx->capture_ratio > 100)
838 ret = SR_ERR;
839 else
840 ret = SR_OK;
841 } else {
842 ret = SR_ERR;
843 }
844
845 return ret;
846}
847
848/* Software trigger to determine exact trigger position. */
849static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
850 struct sigma_trigger *t)
851{
852 int i;
853
854 for (i = 0; i < 8; ++i) {
855 if (i > 0)
856 last_sample = samples[i-1];
857
858 /* Simple triggers. */
859 if ((samples[i] & t->simplemask) != t->simplevalue)
860 continue;
861
862 /* Rising edge. */
863 if ((last_sample & t->risingmask) != 0 || (samples[i] &
864 t->risingmask) != t->risingmask)
865 continue;
866
867 /* Falling edge. */
868 if ((last_sample & t->fallingmask) != t->fallingmask ||
869 (samples[i] & t->fallingmask) != 0)
870 continue;
871
872 break;
873 }
874
875 /* If we did not match, return original trigger pos. */
876 return i & 0x7;
877}
878
879/*
880 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
881 * Each event is 20ns apart, and can contain multiple samples.
882 *
883 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
884 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
885 * For 50 MHz and below, events contain one sample for each channel,
886 * spread 20 ns apart.
887 */
888static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
889 uint16_t *lastsample, int triggerpos,
890 uint16_t limit_chunk, void *cb_data)
891{
892 struct sr_dev_inst *sdi = cb_data;
893 struct context *ctx = sdi->priv;
894 uint16_t tsdiff, ts;
895 uint16_t samples[65536 * ctx->samples_per_event];
896 struct sr_datafeed_packet packet;
897 struct sr_datafeed_logic logic;
898 int i, j, k, l, numpad, tosend;
899 size_t n = 0, sent = 0;
900 int clustersize = EVENTS_PER_CLUSTER * ctx->samples_per_event;
901 uint16_t *event;
902 uint16_t cur_sample;
903 int triggerts = -1;
904
905 /* Check if trigger is in this chunk. */
906 if (triggerpos != -1) {
907 if (ctx->cur_samplerate <= SR_MHZ(50))
908 triggerpos -= EVENTS_PER_CLUSTER - 1;
909
910 if (triggerpos < 0)
911 triggerpos = 0;
912
913 /* Find in which cluster the trigger occured. */
914 triggerts = triggerpos / 7;
915 }
916
917 /* For each ts. */
918 for (i = 0; i < 64; ++i) {
919 ts = *(uint16_t *) &buf[i * 16];
920 tsdiff = ts - *lastts;
921 *lastts = ts;
922
923 /* Decode partial chunk. */
924 if (limit_chunk && ts > limit_chunk)
925 return SR_OK;
926
927 /* Pad last sample up to current point. */
928 numpad = tsdiff * ctx->samples_per_event - clustersize;
929 if (numpad > 0) {
930 for (j = 0; j < numpad; ++j)
931 samples[j] = *lastsample;
932
933 n = numpad;
934 }
935
936 /* Send samples between previous and this timestamp to sigrok. */
937 sent = 0;
938 while (sent < n) {
939 tosend = MIN(2048, n - sent);
940
941 packet.type = SR_DF_LOGIC;
942 packet.payload = &logic;
943 logic.length = tosend * sizeof(uint16_t);
944 logic.unitsize = 2;
945 logic.data = samples + sent;
946 sr_session_send(ctx->session_dev_id, &packet);
947
948 sent += tosend;
949 }
950 n = 0;
951
952 event = (uint16_t *) &buf[i * 16 + 2];
953 cur_sample = 0;
954
955 /* For each event in cluster. */
956 for (j = 0; j < 7; ++j) {
957
958 /* For each sample in event. */
959 for (k = 0; k < ctx->samples_per_event; ++k) {
960 cur_sample = 0;
961
962 /* For each probe. */
963 for (l = 0; l < ctx->num_probes; ++l)
964 cur_sample |= (!!(event[j] & (1 << (l *
965 ctx->samples_per_event + k)))) << l;
966
967 samples[n++] = cur_sample;
968 }
969 }
970
971 /* Send data up to trigger point (if triggered). */
972 sent = 0;
973 if (i == triggerts) {
974 /*
975 * Trigger is not always accurate to sample because of
976 * pipeline delay. However, it always triggers before
977 * the actual event. We therefore look at the next
978 * samples to pinpoint the exact position of the trigger.
979 */
980 tosend = get_trigger_offset(samples, *lastsample,
981 &ctx->trigger);
982
983 if (tosend > 0) {
984 packet.type = SR_DF_LOGIC;
985 packet.payload = &logic;
986 logic.length = tosend * sizeof(uint16_t);
987 logic.unitsize = 2;
988 logic.data = samples;
989 sr_session_send(ctx->session_dev_id, &packet);
990
991 sent += tosend;
992 }
993
994 /* Only send trigger if explicitly enabled. */
995 if (ctx->use_triggers) {
996 packet.type = SR_DF_TRIGGER;
997 sr_session_send(ctx->session_dev_id, &packet);
998 }
999 }
1000
1001 /* Send rest of the chunk to sigrok. */
1002 tosend = n - sent;
1003
1004 if (tosend > 0) {
1005 packet.type = SR_DF_LOGIC;
1006 packet.payload = &logic;
1007 logic.length = tosend * sizeof(uint16_t);
1008 logic.unitsize = 2;
1009 logic.data = samples + sent;
1010 sr_session_send(ctx->session_dev_id, &packet);
1011 }
1012
1013 *lastsample = samples[n - 1];
1014 }
1015
1016 return SR_OK;
1017}
1018
1019static int receive_data(int fd, int revents, void *cb_data)
1020{
1021 struct sr_dev_inst *sdi = cb_data;
1022 struct context *ctx = sdi->priv;
1023 struct sr_datafeed_packet packet;
1024 const int chunks_per_read = 32;
1025 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1026 int bufsz, numchunks, i, newchunks;
1027 uint64_t running_msec;
1028 struct timeval tv;
1029
1030 /* Avoid compiler warnings. */
1031 (void)fd;
1032 (void)revents;
1033
1034 /* Get the current position. */
1035 sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx);
1036
1037 numchunks = (ctx->state.stoppos + 511) / 512;
1038
1039 if (ctx->state.state == SIGMA_IDLE)
1040 return TRUE;
1041
1042 if (ctx->state.state == SIGMA_CAPTURE) {
1043 /* Check if the timer has expired, or memory is full. */
1044 gettimeofday(&tv, 0);
1045 running_msec = (tv.tv_sec - ctx->start_tv.tv_sec) * 1000 +
1046 (tv.tv_usec - ctx->start_tv.tv_usec) / 1000;
1047
1048 if (running_msec < ctx->limit_msec && numchunks < 32767)
1049 return TRUE; /* While capturing... */
1050 else
1051 hw_dev_acquisition_stop(sdi->index, sdi);
1052
1053 } else if (ctx->state.state == SIGMA_DOWNLOAD) {
1054 if (ctx->state.chunks_downloaded >= numchunks) {
1055 /* End of samples. */
1056 packet.type = SR_DF_END;
1057 sr_session_send(ctx->session_dev_id, &packet);
1058
1059 ctx->state.state = SIGMA_IDLE;
1060
1061 return TRUE;
1062 }
1063
1064 newchunks = MIN(chunks_per_read,
1065 numchunks - ctx->state.chunks_downloaded);
1066
1067 sr_info("sigma: Downloading sample data: %.0f %%",
1068 100.0 * ctx->state.chunks_downloaded / numchunks);
1069
1070 bufsz = sigma_read_dram(ctx->state.chunks_downloaded,
1071 newchunks, buf, ctx);
1072 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1073 (void)bufsz;
1074
1075 /* Find first ts. */
1076 if (ctx->state.chunks_downloaded == 0) {
1077 ctx->state.lastts = *(uint16_t *) buf - 1;
1078 ctx->state.lastsample = 0;
1079 }
1080
1081 /* Decode chunks and send them to sigrok. */
1082 for (i = 0; i < newchunks; ++i) {
1083 int limit_chunk = 0;
1084
1085 /* The last chunk may potentially be only in part. */
1086 if (ctx->state.chunks_downloaded == numchunks - 1) {
1087 /* Find the last valid timestamp */
1088 limit_chunk = ctx->state.stoppos % 512 + ctx->state.lastts;
1089 }
1090
1091 if (ctx->state.chunks_downloaded + i == ctx->state.triggerchunk)
1092 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1093 &ctx->state.lastts,
1094 &ctx->state.lastsample,
1095 ctx->state.triggerpos & 0x1ff,
1096 limit_chunk, sdi);
1097 else
1098 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1099 &ctx->state.lastts,
1100 &ctx->state.lastsample,
1101 -1, limit_chunk, sdi);
1102
1103 ++ctx->state.chunks_downloaded;
1104 }
1105 }
1106
1107 return TRUE;
1108}
1109
1110/* Build a LUT entry used by the trigger functions. */
1111static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1112{
1113 int i, j, k, bit;
1114
1115 /* For each quad probe. */
1116 for (i = 0; i < 4; ++i) {
1117 entry[i] = 0xffff;
1118
1119 /* For each bit in LUT. */
1120 for (j = 0; j < 16; ++j)
1121
1122 /* For each probe in quad. */
1123 for (k = 0; k < 4; ++k) {
1124 bit = 1 << (i * 4 + k);
1125
1126 /* Set bit in entry */
1127 if ((mask & bit) &&
1128 ((!(value & bit)) !=
1129 (!(j & (1 << k)))))
1130 entry[i] &= ~(1 << j);
1131 }
1132 }
1133}
1134
1135/* Add a logical function to LUT mask. */
1136static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1137 int index, int neg, uint16_t *mask)
1138{
1139 int i, j;
1140 int x[2][2], tmp, a, b, aset, bset, rset;
1141
1142 memset(x, 0, 4 * sizeof(int));
1143
1144 /* Trigger detect condition. */
1145 switch (oper) {
1146 case OP_LEVEL:
1147 x[0][1] = 1;
1148 x[1][1] = 1;
1149 break;
1150 case OP_NOT:
1151 x[0][0] = 1;
1152 x[1][0] = 1;
1153 break;
1154 case OP_RISE:
1155 x[0][1] = 1;
1156 break;
1157 case OP_FALL:
1158 x[1][0] = 1;
1159 break;
1160 case OP_RISEFALL:
1161 x[0][1] = 1;
1162 x[1][0] = 1;
1163 break;
1164 case OP_NOTRISE:
1165 x[1][1] = 1;
1166 x[0][0] = 1;
1167 x[1][0] = 1;
1168 break;
1169 case OP_NOTFALL:
1170 x[1][1] = 1;
1171 x[0][0] = 1;
1172 x[0][1] = 1;
1173 break;
1174 case OP_NOTRISEFALL:
1175 x[1][1] = 1;
1176 x[0][0] = 1;
1177 break;
1178 }
1179
1180 /* Transpose if neg is set. */
1181 if (neg) {
1182 for (i = 0; i < 2; ++i) {
1183 for (j = 0; j < 2; ++j) {
1184 tmp = x[i][j];
1185 x[i][j] = x[1-i][1-j];
1186 x[1-i][1-j] = tmp;
1187 }
1188 }
1189 }
1190
1191 /* Update mask with function. */
1192 for (i = 0; i < 16; ++i) {
1193 a = (i >> (2 * index + 0)) & 1;
1194 b = (i >> (2 * index + 1)) & 1;
1195
1196 aset = (*mask >> i) & 1;
1197 bset = x[b][a];
1198
1199 if (func == FUNC_AND || func == FUNC_NAND)
1200 rset = aset & bset;
1201 else if (func == FUNC_OR || func == FUNC_NOR)
1202 rset = aset | bset;
1203 else if (func == FUNC_XOR || func == FUNC_NXOR)
1204 rset = aset ^ bset;
1205
1206 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1207 rset = !rset;
1208
1209 *mask &= ~(1 << i);
1210
1211 if (rset)
1212 *mask |= 1 << i;
1213 }
1214}
1215
1216/*
1217 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1218 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1219 * set at any time, but a full mask and value can be set (0/1).
1220 */
1221static int build_basic_trigger(struct triggerlut *lut, struct context *ctx)
1222{
1223 int i,j;
1224 uint16_t masks[2] = { 0, 0 };
1225
1226 memset(lut, 0, sizeof(struct triggerlut));
1227
1228 /* Contant for simple triggers. */
1229 lut->m4 = 0xa000;
1230
1231 /* Value/mask trigger support. */
1232 build_lut_entry(ctx->trigger.simplevalue, ctx->trigger.simplemask,
1233 lut->m2d);
1234
1235 /* Rise/fall trigger support. */
1236 for (i = 0, j = 0; i < 16; ++i) {
1237 if (ctx->trigger.risingmask & (1 << i) ||
1238 ctx->trigger.fallingmask & (1 << i))
1239 masks[j++] = 1 << i;
1240 }
1241
1242 build_lut_entry(masks[0], masks[0], lut->m0d);
1243 build_lut_entry(masks[1], masks[1], lut->m1d);
1244
1245 /* Add glue logic */
1246 if (masks[0] || masks[1]) {
1247 /* Transition trigger. */
1248 if (masks[0] & ctx->trigger.risingmask)
1249 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1250 if (masks[0] & ctx->trigger.fallingmask)
1251 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1252 if (masks[1] & ctx->trigger.risingmask)
1253 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1254 if (masks[1] & ctx->trigger.fallingmask)
1255 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1256 } else {
1257 /* Only value/mask trigger. */
1258 lut->m3 = 0xffff;
1259 }
1260
1261 /* Triggertype: event. */
1262 lut->params.selres = 3;
1263
1264 return SR_OK;
1265}
1266
1267static int hw_dev_acquisition_start(int dev_index, void *cb_data)
1268{
1269 struct sr_dev_inst *sdi;
1270 struct context *ctx;
1271 struct sr_datafeed_packet *packet;
1272 struct sr_datafeed_header *header;
1273 struct sr_datafeed_meta_logic meta;
1274 struct clockselect_50 clockselect;
1275 int frac, triggerpin, ret;
1276 uint8_t triggerselect;
1277 struct triggerinout triggerinout_conf;
1278 struct triggerlut lut;
1279
1280 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index)))
1281 return SR_ERR;
1282
1283 ctx = sdi->priv;
1284
1285 /* If the samplerate has not been set, default to 200 kHz. */
1286 if (ctx->cur_firmware == -1) {
1287 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1288 return ret;
1289 }
1290
1291 /* Enter trigger programming mode. */
1292 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, ctx);
1293
1294 /* 100 and 200 MHz mode. */
1295 if (ctx->cur_samplerate >= SR_MHZ(100)) {
1296 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, ctx);
1297
1298 /* Find which pin to trigger on from mask. */
1299 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1300 if ((ctx->trigger.risingmask | ctx->trigger.fallingmask) &
1301 (1 << triggerpin))
1302 break;
1303
1304 /* Set trigger pin and light LED on trigger. */
1305 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1306
1307 /* Default rising edge. */
1308 if (ctx->trigger.fallingmask)
1309 triggerselect |= 1 << 3;
1310
1311 /* All other modes. */
1312 } else if (ctx->cur_samplerate <= SR_MHZ(50)) {
1313 build_basic_trigger(&lut, ctx);
1314
1315 sigma_write_trigger_lut(&lut, ctx);
1316
1317 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1318 }
1319
1320 /* Setup trigger in and out pins to default values. */
1321 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1322 triggerinout_conf.trgout_bytrigger = 1;
1323 triggerinout_conf.trgout_enable = 1;
1324
1325 sigma_write_register(WRITE_TRIGGER_OPTION,
1326 (uint8_t *) &triggerinout_conf,
1327 sizeof(struct triggerinout), ctx);
1328
1329 /* Go back to normal mode. */
1330 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, ctx);
1331
1332 /* Set clock select register. */
1333 if (ctx->cur_samplerate == SR_MHZ(200))
1334 /* Enable 4 probes. */
1335 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, ctx);
1336 else if (ctx->cur_samplerate == SR_MHZ(100))
1337 /* Enable 8 probes. */
1338 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, ctx);
1339 else {
1340 /*
1341 * 50 MHz mode (or fraction thereof). Any fraction down to
1342 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1343 */
1344 frac = SR_MHZ(50) / ctx->cur_samplerate - 1;
1345
1346 clockselect.async = 0;
1347 clockselect.fraction = frac;
1348 clockselect.disabled_probes = 0;
1349
1350 sigma_write_register(WRITE_CLOCK_SELECT,
1351 (uint8_t *) &clockselect,
1352 sizeof(clockselect), ctx);
1353 }
1354
1355 /* Setup maximum post trigger time. */
1356 sigma_set_register(WRITE_POST_TRIGGER,
1357 (ctx->capture_ratio * 255) / 100, ctx);
1358
1359 /* Start acqusition. */
1360 gettimeofday(&ctx->start_tv, 0);
1361 sigma_set_register(WRITE_MODE, 0x0d, ctx);
1362
1363 ctx->session_dev_id = cb_data;
1364
1365 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1366 sr_err("sigma: %s: packet malloc failed.", __func__);
1367 return SR_ERR_MALLOC;
1368 }
1369
1370 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1371 sr_err("sigma: %s: header malloc failed.", __func__);
1372 return SR_ERR_MALLOC;
1373 }
1374
1375 /* Send header packet to the session bus. */
1376 packet->type = SR_DF_HEADER;
1377 packet->payload = header;
1378 header->feed_version = 1;
1379 gettimeofday(&header->starttime, NULL);
1380 sr_session_send(ctx->session_dev_id, packet);
1381
1382 /* Send metadata about the SR_DF_LOGIC packets to come. */
1383 packet->type = SR_DF_META_LOGIC;
1384 packet->payload = &meta;
1385 meta.samplerate = ctx->cur_samplerate;
1386 meta.num_probes = ctx->num_probes;
1387 sr_session_send(ctx->session_dev_id, packet);
1388
1389 /* Add capture source. */
1390 sr_source_add(0, G_IO_IN, 10, receive_data, sdi);
1391
1392 g_free(header);
1393 g_free(packet);
1394
1395 ctx->state.state = SIGMA_CAPTURE;
1396
1397 return SR_OK;
1398}
1399
1400static int hw_dev_acquisition_stop(int dev_index, void *cb_data)
1401{
1402 struct sr_dev_inst *sdi;
1403 struct context *ctx;
1404 uint8_t modestatus;
1405
1406 /* Avoid compiler warnings. */
1407 (void)cb_data;
1408
1409 if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) {
1410 sr_err("sigma: %s: sdi was NULL", __func__);
1411 return SR_ERR_BUG;
1412 }
1413
1414 if (!(ctx = sdi->priv)) {
1415 sr_err("sigma: %s: sdi->priv was NULL", __func__);
1416 return SR_ERR_BUG;
1417 }
1418
1419 /* Stop acquisition. */
1420 sigma_set_register(WRITE_MODE, 0x11, ctx);
1421
1422 /* Set SDRAM Read Enable. */
1423 sigma_set_register(WRITE_MODE, 0x02, ctx);
1424
1425 /* Get the current position. */
1426 sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx);
1427
1428 /* Check if trigger has fired. */
1429 modestatus = sigma_get_register(READ_MODE, ctx);
1430 if (modestatus & 0x20)
1431 ctx->state.triggerchunk = ctx->state.triggerpos / 512;
1432 else
1433 ctx->state.triggerchunk = -1;
1434
1435 ctx->state.chunks_downloaded = 0;
1436
1437 ctx->state.state = SIGMA_DOWNLOAD;
1438
1439 return SR_OK;
1440}
1441
1442SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1443 .name = "asix-sigma",
1444 .longname = "ASIX SIGMA/SIGMA2",
1445 .api_version = 1,
1446 .init = hw_init,
1447 .cleanup = hw_cleanup,
1448 .scan = hw_scan,
1449 .dev_open = hw_dev_open,
1450 .dev_close = hw_dev_close,
1451 .dev_info_get = hw_dev_info_get,
1452 .dev_status_get = hw_dev_status_get,
1453 .hwcap_get_all = hw_hwcap_get_all,
1454 .dev_config_set = hw_dev_config_set,
1455 .dev_acquisition_start = hw_dev_acquisition_start,
1456 .dev_acquisition_stop = hw_dev_acquisition_stop,
1457};
Hardware access and backend lib