]>
Commit | Line | Data |
---|---|---|
1 | /* | |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, | |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
7 | * | |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | /* | |
23 | * ASIX SIGMA/SIGMA2 logic analyzer driver | |
24 | */ | |
25 | ||
26 | #include <glib.h> | |
27 | #include <glib/gstdio.h> | |
28 | #include <ftdi.h> | |
29 | #include <string.h> | |
30 | #include "libsigrok.h" | |
31 | #include "libsigrok-internal.h" | |
32 | #include "asix-sigma.h" | |
33 | ||
34 | #define USB_VENDOR 0xa600 | |
35 | #define USB_PRODUCT 0xa000 | |
36 | #define USB_DESCRIPTION "ASIX SIGMA" | |
37 | #define USB_VENDOR_NAME "ASIX" | |
38 | #define USB_MODEL_NAME "SIGMA" | |
39 | #define TRIGGER_TYPE "rf10" | |
40 | #define NUM_CHANNELS 16 | |
41 | ||
42 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info; | |
43 | static struct sr_dev_driver *di = &asix_sigma_driver_info; | |
44 | static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data); | |
45 | ||
46 | static const uint64_t samplerates[] = { | |
47 | SR_KHZ(200), | |
48 | SR_KHZ(250), | |
49 | SR_KHZ(500), | |
50 | SR_MHZ(1), | |
51 | SR_MHZ(5), | |
52 | SR_MHZ(10), | |
53 | SR_MHZ(25), | |
54 | SR_MHZ(50), | |
55 | SR_MHZ(100), | |
56 | SR_MHZ(200), | |
57 | }; | |
58 | ||
59 | /* | |
60 | * Channel numbers seem to go from 1-16, according to this image: | |
61 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg | |
62 | * (the cable has two additional GND pins, and a TI and TO pin) | |
63 | */ | |
64 | static const char *channel_names[NUM_CHANNELS + 1] = { | |
65 | "1", "2", "3", "4", "5", "6", "7", "8", | |
66 | "9", "10", "11", "12", "13", "14", "15", "16", | |
67 | NULL, | |
68 | }; | |
69 | ||
70 | static const int32_t hwcaps[] = { | |
71 | SR_CONF_LOGIC_ANALYZER, | |
72 | SR_CONF_SAMPLERATE, | |
73 | SR_CONF_TRIGGER_TYPE, | |
74 | SR_CONF_CAPTURE_RATIO, | |
75 | SR_CONF_LIMIT_MSEC, | |
76 | SR_CONF_LIMIT_SAMPLES, | |
77 | }; | |
78 | ||
79 | /* Force the FPGA to reboot. */ | |
80 | static uint8_t suicide[] = { | |
81 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
82 | }; | |
83 | ||
84 | /* Prepare to upload firmware (FPGA specific). */ | |
85 | static uint8_t init_array[] = { | |
86 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, | |
87 | }; | |
88 | ||
89 | /* Initialize the logic analyzer mode. */ | |
90 | static uint8_t logic_mode_start[] = { | |
91 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
92 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
93 | }; | |
94 | ||
95 | static const char *firmware_files[] = { | |
96 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ | |
97 | "asix-sigma-100.fw", /* 100 MHz */ | |
98 | "asix-sigma-200.fw", /* 200 MHz */ | |
99 | "asix-sigma-50sync.fw", /* Synchronous clock from pin */ | |
100 | "asix-sigma-phasor.fw", /* Frequency counter */ | |
101 | }; | |
102 | ||
103 | static int sigma_read(void *buf, size_t size, struct dev_context *devc) | |
104 | { | |
105 | int ret; | |
106 | ||
107 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); | |
108 | if (ret < 0) { | |
109 | sr_err("ftdi_read_data failed: %s", | |
110 | ftdi_get_error_string(&devc->ftdic)); | |
111 | } | |
112 | ||
113 | return ret; | |
114 | } | |
115 | ||
116 | static int sigma_write(void *buf, size_t size, struct dev_context *devc) | |
117 | { | |
118 | int ret; | |
119 | ||
120 | ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); | |
121 | if (ret < 0) { | |
122 | sr_err("ftdi_write_data failed: %s", | |
123 | ftdi_get_error_string(&devc->ftdic)); | |
124 | } else if ((size_t) ret != size) { | |
125 | sr_err("ftdi_write_data did not complete write."); | |
126 | } | |
127 | ||
128 | return ret; | |
129 | } | |
130 | ||
131 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, | |
132 | struct dev_context *devc) | |
133 | { | |
134 | size_t i; | |
135 | uint8_t buf[len + 2]; | |
136 | int idx = 0; | |
137 | ||
138 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
139 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
140 | ||
141 | for (i = 0; i < len; ++i) { | |
142 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); | |
143 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
144 | } | |
145 | ||
146 | return sigma_write(buf, idx, devc); | |
147 | } | |
148 | ||
149 | static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc) | |
150 | { | |
151 | return sigma_write_register(reg, &value, 1, devc); | |
152 | } | |
153 | ||
154 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, | |
155 | struct dev_context *devc) | |
156 | { | |
157 | uint8_t buf[3]; | |
158 | ||
159 | buf[0] = REG_ADDR_LOW | (reg & 0xf); | |
160 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
161 | buf[2] = REG_READ_ADDR; | |
162 | ||
163 | sigma_write(buf, sizeof(buf), devc); | |
164 | ||
165 | return sigma_read(data, len, devc); | |
166 | } | |
167 | ||
168 | static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc) | |
169 | { | |
170 | uint8_t value; | |
171 | ||
172 | if (1 != sigma_read_register(reg, &value, 1, devc)) { | |
173 | sr_err("sigma_get_register: 1 byte expected"); | |
174 | return 0; | |
175 | } | |
176 | ||
177 | return value; | |
178 | } | |
179 | ||
180 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, | |
181 | struct dev_context *devc) | |
182 | { | |
183 | uint8_t buf[] = { | |
184 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
185 | ||
186 | REG_READ_ADDR | NEXT_REG, | |
187 | REG_READ_ADDR | NEXT_REG, | |
188 | REG_READ_ADDR | NEXT_REG, | |
189 | REG_READ_ADDR | NEXT_REG, | |
190 | REG_READ_ADDR | NEXT_REG, | |
191 | REG_READ_ADDR | NEXT_REG, | |
192 | }; | |
193 | uint8_t result[6]; | |
194 | ||
195 | sigma_write(buf, sizeof(buf), devc); | |
196 | ||
197 | sigma_read(result, sizeof(result), devc); | |
198 | ||
199 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
200 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
201 | ||
202 | /* Not really sure why this must be done, but according to spec. */ | |
203 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
204 | stoppos -= 64; | |
205 | ||
206 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
207 | triggerpos -= 64; | |
208 | ||
209 | return 1; | |
210 | } | |
211 | ||
212 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, | |
213 | uint8_t *data, struct dev_context *devc) | |
214 | { | |
215 | size_t i; | |
216 | uint8_t buf[4096]; | |
217 | int idx = 0; | |
218 | ||
219 | /* Send the startchunk. Index start with 1. */ | |
220 | buf[0] = startchunk >> 8; | |
221 | buf[1] = startchunk & 0xff; | |
222 | sigma_write_register(WRITE_MEMROW, buf, 2, devc); | |
223 | ||
224 | /* Read the DRAM. */ | |
225 | buf[idx++] = REG_DRAM_BLOCK; | |
226 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
227 | ||
228 | for (i = 0; i < numchunks; ++i) { | |
229 | /* Alternate bit to copy from DRAM to cache. */ | |
230 | if (i != (numchunks - 1)) | |
231 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
232 | ||
233 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
234 | ||
235 | if (i != (numchunks - 1)) | |
236 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
237 | } | |
238 | ||
239 | sigma_write(buf, idx, devc); | |
240 | ||
241 | return sigma_read(data, numchunks * CHUNK_SIZE, devc); | |
242 | } | |
243 | ||
244 | /* Upload trigger look-up tables to Sigma. */ | |
245 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc) | |
246 | { | |
247 | int i; | |
248 | uint8_t tmp[2]; | |
249 | uint16_t bit; | |
250 | ||
251 | /* Transpose the table and send to Sigma. */ | |
252 | for (i = 0; i < 16; ++i) { | |
253 | bit = 1 << i; | |
254 | ||
255 | tmp[0] = tmp[1] = 0; | |
256 | ||
257 | if (lut->m2d[0] & bit) | |
258 | tmp[0] |= 0x01; | |
259 | if (lut->m2d[1] & bit) | |
260 | tmp[0] |= 0x02; | |
261 | if (lut->m2d[2] & bit) | |
262 | tmp[0] |= 0x04; | |
263 | if (lut->m2d[3] & bit) | |
264 | tmp[0] |= 0x08; | |
265 | ||
266 | if (lut->m3 & bit) | |
267 | tmp[0] |= 0x10; | |
268 | if (lut->m3s & bit) | |
269 | tmp[0] |= 0x20; | |
270 | if (lut->m4 & bit) | |
271 | tmp[0] |= 0x40; | |
272 | ||
273 | if (lut->m0d[0] & bit) | |
274 | tmp[1] |= 0x01; | |
275 | if (lut->m0d[1] & bit) | |
276 | tmp[1] |= 0x02; | |
277 | if (lut->m0d[2] & bit) | |
278 | tmp[1] |= 0x04; | |
279 | if (lut->m0d[3] & bit) | |
280 | tmp[1] |= 0x08; | |
281 | ||
282 | if (lut->m1d[0] & bit) | |
283 | tmp[1] |= 0x10; | |
284 | if (lut->m1d[1] & bit) | |
285 | tmp[1] |= 0x20; | |
286 | if (lut->m1d[2] & bit) | |
287 | tmp[1] |= 0x40; | |
288 | if (lut->m1d[3] & bit) | |
289 | tmp[1] |= 0x80; | |
290 | ||
291 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), | |
292 | devc); | |
293 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); | |
294 | } | |
295 | ||
296 | /* Send the parameters */ | |
297 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
298 | sizeof(lut->params), devc); | |
299 | ||
300 | return SR_OK; | |
301 | } | |
302 | ||
303 | /* Generate the bitbang stream for programming the FPGA. */ | |
304 | static int bin2bitbang(const char *filename, | |
305 | unsigned char **buf, size_t *buf_size) | |
306 | { | |
307 | FILE *f; | |
308 | unsigned long file_size; | |
309 | unsigned long offset = 0; | |
310 | unsigned char *p; | |
311 | uint8_t *firmware; | |
312 | unsigned long fwsize = 0; | |
313 | const int buffer_size = 65536; | |
314 | size_t i; | |
315 | int c, bit, v; | |
316 | uint32_t imm = 0x3f6df2ab; | |
317 | ||
318 | f = g_fopen(filename, "rb"); | |
319 | if (!f) { | |
320 | sr_err("g_fopen(\"%s\", \"rb\")", filename); | |
321 | return SR_ERR; | |
322 | } | |
323 | ||
324 | if (-1 == fseek(f, 0, SEEK_END)) { | |
325 | sr_err("fseek on %s failed", filename); | |
326 | fclose(f); | |
327 | return SR_ERR; | |
328 | } | |
329 | ||
330 | file_size = ftell(f); | |
331 | ||
332 | fseek(f, 0, SEEK_SET); | |
333 | ||
334 | if (!(firmware = g_try_malloc(buffer_size))) { | |
335 | sr_err("%s: firmware malloc failed", __func__); | |
336 | fclose(f); | |
337 | return SR_ERR_MALLOC; | |
338 | } | |
339 | ||
340 | while ((c = getc(f)) != EOF) { | |
341 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
342 | firmware[fwsize++] = c ^ imm; | |
343 | } | |
344 | fclose(f); | |
345 | ||
346 | if(fwsize != file_size) { | |
347 | sr_err("%s: Error reading firmware", filename); | |
348 | fclose(f); | |
349 | g_free(firmware); | |
350 | return SR_ERR; | |
351 | } | |
352 | ||
353 | *buf_size = fwsize * 2 * 8; | |
354 | ||
355 | *buf = p = (unsigned char *)g_try_malloc(*buf_size); | |
356 | if (!p) { | |
357 | sr_err("%s: buf/p malloc failed", __func__); | |
358 | g_free(firmware); | |
359 | return SR_ERR_MALLOC; | |
360 | } | |
361 | ||
362 | for (i = 0; i < fwsize; ++i) { | |
363 | for (bit = 7; bit >= 0; --bit) { | |
364 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; | |
365 | p[offset++] = v | 0x01; | |
366 | p[offset++] = v; | |
367 | } | |
368 | } | |
369 | ||
370 | g_free(firmware); | |
371 | ||
372 | if (offset != *buf_size) { | |
373 | g_free(*buf); | |
374 | sr_err("Error reading firmware %s " | |
375 | "offset=%ld, file_size=%ld, buf_size=%zd.", | |
376 | filename, offset, file_size, *buf_size); | |
377 | ||
378 | return SR_ERR; | |
379 | } | |
380 | ||
381 | return SR_OK; | |
382 | } | |
383 | ||
384 | static void clear_helper(void *priv) | |
385 | { | |
386 | struct dev_context *devc; | |
387 | ||
388 | devc = priv; | |
389 | ||
390 | ftdi_deinit(&devc->ftdic); | |
391 | } | |
392 | ||
393 | static int dev_clear(void) | |
394 | { | |
395 | return std_dev_clear(di, clear_helper); | |
396 | } | |
397 | ||
398 | static int init(struct sr_context *sr_ctx) | |
399 | { | |
400 | return std_init(sr_ctx, di, LOG_PREFIX); | |
401 | } | |
402 | ||
403 | static GSList *scan(GSList *options) | |
404 | { | |
405 | struct sr_dev_inst *sdi; | |
406 | struct sr_channel *ch; | |
407 | struct drv_context *drvc; | |
408 | struct dev_context *devc; | |
409 | GSList *devices; | |
410 | struct ftdi_device_list *devlist; | |
411 | char serial_txt[10]; | |
412 | uint32_t serial; | |
413 | int ret, i; | |
414 | ||
415 | (void)options; | |
416 | ||
417 | drvc = di->priv; | |
418 | ||
419 | devices = NULL; | |
420 | ||
421 | if (!(devc = g_try_malloc(sizeof(struct dev_context)))) { | |
422 | sr_err("%s: devc malloc failed", __func__); | |
423 | return NULL; | |
424 | } | |
425 | ||
426 | ftdi_init(&devc->ftdic); | |
427 | ||
428 | /* Look for SIGMAs. */ | |
429 | ||
430 | if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist, | |
431 | USB_VENDOR, USB_PRODUCT)) <= 0) { | |
432 | if (ret < 0) | |
433 | sr_err("ftdi_usb_find_all(): %d", ret); | |
434 | goto free; | |
435 | } | |
436 | ||
437 | /* Make sure it's a version 1 or 2 SIGMA. */ | |
438 | ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0, | |
439 | serial_txt, sizeof(serial_txt)); | |
440 | sscanf(serial_txt, "%x", &serial); | |
441 | ||
442 | if (serial < 0xa6010000 || serial > 0xa602ffff) { | |
443 | sr_err("Only SIGMA and SIGMA2 are supported " | |
444 | "in this version of libsigrok."); | |
445 | goto free; | |
446 | } | |
447 | ||
448 | sr_info("Found ASIX SIGMA - Serial: %s", serial_txt); | |
449 | ||
450 | devc->cur_samplerate = 0; | |
451 | devc->period_ps = 0; | |
452 | devc->limit_msec = 0; | |
453 | devc->cur_firmware = -1; | |
454 | devc->num_channels = 0; | |
455 | devc->samples_per_event = 0; | |
456 | devc->capture_ratio = 50; | |
457 | devc->use_triggers = 0; | |
458 | ||
459 | /* Register SIGMA device. */ | |
460 | if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME, | |
461 | USB_MODEL_NAME, NULL))) { | |
462 | sr_err("%s: sdi was NULL", __func__); | |
463 | goto free; | |
464 | } | |
465 | sdi->driver = di; | |
466 | ||
467 | for (i = 0; channel_names[i]; i++) { | |
468 | if (!(ch = sr_channel_new(i, SR_CHANNEL_LOGIC, TRUE, | |
469 | channel_names[i]))) | |
470 | return NULL; | |
471 | sdi->channels = g_slist_append(sdi->channels, ch); | |
472 | } | |
473 | ||
474 | devices = g_slist_append(devices, sdi); | |
475 | drvc->instances = g_slist_append(drvc->instances, sdi); | |
476 | sdi->priv = devc; | |
477 | ||
478 | /* We will open the device again when we need it. */ | |
479 | ftdi_list_free(&devlist); | |
480 | ||
481 | return devices; | |
482 | ||
483 | free: | |
484 | ftdi_deinit(&devc->ftdic); | |
485 | g_free(devc); | |
486 | return NULL; | |
487 | } | |
488 | ||
489 | static GSList *dev_list(void) | |
490 | { | |
491 | return ((struct drv_context *)(di->priv))->instances; | |
492 | } | |
493 | ||
494 | static int upload_firmware(int firmware_idx, struct dev_context *devc) | |
495 | { | |
496 | int ret; | |
497 | unsigned char *buf; | |
498 | unsigned char pins; | |
499 | size_t buf_size; | |
500 | unsigned char result[32]; | |
501 | char firmware_path[128]; | |
502 | ||
503 | /* Make sure it's an ASIX SIGMA. */ | |
504 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, | |
505 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { | |
506 | sr_err("ftdi_usb_open failed: %s", | |
507 | ftdi_get_error_string(&devc->ftdic)); | |
508 | return 0; | |
509 | } | |
510 | ||
511 | if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) { | |
512 | sr_err("ftdi_set_bitmode failed: %s", | |
513 | ftdi_get_error_string(&devc->ftdic)); | |
514 | return 0; | |
515 | } | |
516 | ||
517 | /* Four times the speed of sigmalogan - Works well. */ | |
518 | if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) { | |
519 | sr_err("ftdi_set_baudrate failed: %s", | |
520 | ftdi_get_error_string(&devc->ftdic)); | |
521 | return 0; | |
522 | } | |
523 | ||
524 | /* Force the FPGA to reboot. */ | |
525 | sigma_write(suicide, sizeof(suicide), devc); | |
526 | sigma_write(suicide, sizeof(suicide), devc); | |
527 | sigma_write(suicide, sizeof(suicide), devc); | |
528 | sigma_write(suicide, sizeof(suicide), devc); | |
529 | ||
530 | /* Prepare to upload firmware (FPGA specific). */ | |
531 | sigma_write(init_array, sizeof(init_array), devc); | |
532 | ||
533 | ftdi_usb_purge_buffers(&devc->ftdic); | |
534 | ||
535 | /* Wait until the FPGA asserts INIT_B. */ | |
536 | while (1) { | |
537 | ret = sigma_read(result, 1, devc); | |
538 | if (result[0] & 0x20) | |
539 | break; | |
540 | } | |
541 | ||
542 | /* Prepare firmware. */ | |
543 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, | |
544 | firmware_files[firmware_idx]); | |
545 | ||
546 | if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) { | |
547 | sr_err("An error occured while reading the firmware: %s", | |
548 | firmware_path); | |
549 | return ret; | |
550 | } | |
551 | ||
552 | /* Upload firmare. */ | |
553 | sr_info("Uploading firmware file '%s'.", firmware_files[firmware_idx]); | |
554 | sigma_write(buf, buf_size, devc); | |
555 | ||
556 | g_free(buf); | |
557 | ||
558 | if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) { | |
559 | sr_err("ftdi_set_bitmode failed: %s", | |
560 | ftdi_get_error_string(&devc->ftdic)); | |
561 | return SR_ERR; | |
562 | } | |
563 | ||
564 | ftdi_usb_purge_buffers(&devc->ftdic); | |
565 | ||
566 | /* Discard garbage. */ | |
567 | while (1 == sigma_read(&pins, 1, devc)) | |
568 | ; | |
569 | ||
570 | /* Initialize the logic analyzer mode. */ | |
571 | sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); | |
572 | ||
573 | /* Expect a 3 byte reply. */ | |
574 | ret = sigma_read(result, 3, devc); | |
575 | if (ret != 3 || | |
576 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
577 | sr_err("Configuration failed. Invalid reply received."); | |
578 | return SR_ERR; | |
579 | } | |
580 | ||
581 | devc->cur_firmware = firmware_idx; | |
582 | ||
583 | sr_info("Firmware uploaded."); | |
584 | ||
585 | return SR_OK; | |
586 | } | |
587 | ||
588 | static int dev_open(struct sr_dev_inst *sdi) | |
589 | { | |
590 | struct dev_context *devc; | |
591 | int ret; | |
592 | ||
593 | devc = sdi->priv; | |
594 | ||
595 | /* Make sure it's an ASIX SIGMA. */ | |
596 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, | |
597 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { | |
598 | ||
599 | sr_err("ftdi_usb_open failed: %s", | |
600 | ftdi_get_error_string(&devc->ftdic)); | |
601 | ||
602 | return 0; | |
603 | } | |
604 | ||
605 | sdi->status = SR_ST_ACTIVE; | |
606 | ||
607 | return SR_OK; | |
608 | } | |
609 | ||
610 | static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) | |
611 | { | |
612 | struct dev_context *devc; | |
613 | unsigned int i; | |
614 | int ret; | |
615 | ||
616 | devc = sdi->priv; | |
617 | ret = SR_OK; | |
618 | ||
619 | for (i = 0; i < ARRAY_SIZE(samplerates); i++) { | |
620 | if (samplerates[i] == samplerate) | |
621 | break; | |
622 | } | |
623 | if (samplerates[i] == 0) | |
624 | return SR_ERR_SAMPLERATE; | |
625 | ||
626 | if (samplerate <= SR_MHZ(50)) { | |
627 | ret = upload_firmware(0, devc); | |
628 | devc->num_channels = 16; | |
629 | } | |
630 | if (samplerate == SR_MHZ(100)) { | |
631 | ret = upload_firmware(1, devc); | |
632 | devc->num_channels = 8; | |
633 | } | |
634 | else if (samplerate == SR_MHZ(200)) { | |
635 | ret = upload_firmware(2, devc); | |
636 | devc->num_channels = 4; | |
637 | } | |
638 | ||
639 | devc->cur_samplerate = samplerate; | |
640 | devc->period_ps = 1000000000000ULL / samplerate; | |
641 | devc->samples_per_event = 16 / devc->num_channels; | |
642 | devc->state.state = SIGMA_IDLE; | |
643 | ||
644 | return ret; | |
645 | } | |
646 | ||
647 | /* | |
648 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
649 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
650 | * in addition to value/mask trigger for any number of channels. | |
651 | * | |
652 | * The Sigma supports complex triggers using boolean expressions, but this | |
653 | * has not been implemented yet. | |
654 | */ | |
655 | static int configure_channels(const struct sr_dev_inst *sdi) | |
656 | { | |
657 | struct dev_context *devc = sdi->priv; | |
658 | const struct sr_channel *ch; | |
659 | const GSList *l; | |
660 | int trigger_set = 0; | |
661 | int channelbit; | |
662 | ||
663 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); | |
664 | ||
665 | for (l = sdi->channels; l; l = l->next) { | |
666 | ch = (struct sr_channel *)l->data; | |
667 | channelbit = 1 << (ch->index); | |
668 | ||
669 | if (!ch->enabled || !ch->trigger) | |
670 | continue; | |
671 | ||
672 | if (devc->cur_samplerate >= SR_MHZ(100)) { | |
673 | /* Fast trigger support. */ | |
674 | if (trigger_set) { | |
675 | sr_err("Only a single pin trigger in 100 and " | |
676 | "200MHz mode is supported."); | |
677 | return SR_ERR; | |
678 | } | |
679 | if (ch->trigger[0] == 'f') | |
680 | devc->trigger.fallingmask |= channelbit; | |
681 | else if (ch->trigger[0] == 'r') | |
682 | devc->trigger.risingmask |= channelbit; | |
683 | else { | |
684 | sr_err("Only rising/falling trigger in 100 " | |
685 | "and 200MHz mode is supported."); | |
686 | return SR_ERR; | |
687 | } | |
688 | ||
689 | ++trigger_set; | |
690 | } else { | |
691 | /* Simple trigger support (event). */ | |
692 | if (ch->trigger[0] == '1') { | |
693 | devc->trigger.simplevalue |= channelbit; | |
694 | devc->trigger.simplemask |= channelbit; | |
695 | } | |
696 | else if (ch->trigger[0] == '0') { | |
697 | devc->trigger.simplevalue &= ~channelbit; | |
698 | devc->trigger.simplemask |= channelbit; | |
699 | } | |
700 | else if (ch->trigger[0] == 'f') { | |
701 | devc->trigger.fallingmask |= channelbit; | |
702 | ++trigger_set; | |
703 | } | |
704 | else if (ch->trigger[0] == 'r') { | |
705 | devc->trigger.risingmask |= channelbit; | |
706 | ++trigger_set; | |
707 | } | |
708 | ||
709 | /* | |
710 | * Actually, Sigma supports 2 rising/falling triggers, | |
711 | * but they are ORed and the current trigger syntax | |
712 | * does not permit ORed triggers. | |
713 | */ | |
714 | if (trigger_set > 1) { | |
715 | sr_err("Only 1 rising/falling trigger " | |
716 | "is supported."); | |
717 | return SR_ERR; | |
718 | } | |
719 | } | |
720 | ||
721 | if (trigger_set) | |
722 | devc->use_triggers = 1; | |
723 | } | |
724 | ||
725 | return SR_OK; | |
726 | } | |
727 | ||
728 | static int dev_close(struct sr_dev_inst *sdi) | |
729 | { | |
730 | struct dev_context *devc; | |
731 | ||
732 | devc = sdi->priv; | |
733 | ||
734 | /* TODO */ | |
735 | if (sdi->status == SR_ST_ACTIVE) | |
736 | ftdi_usb_close(&devc->ftdic); | |
737 | ||
738 | sdi->status = SR_ST_INACTIVE; | |
739 | ||
740 | return SR_OK; | |
741 | } | |
742 | ||
743 | static int cleanup(void) | |
744 | { | |
745 | return dev_clear(); | |
746 | } | |
747 | ||
748 | static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi, | |
749 | const struct sr_channel_group *cg) | |
750 | { | |
751 | struct dev_context *devc; | |
752 | ||
753 | (void)cg; | |
754 | ||
755 | switch (id) { | |
756 | case SR_CONF_SAMPLERATE: | |
757 | if (sdi) { | |
758 | devc = sdi->priv; | |
759 | *data = g_variant_new_uint64(devc->cur_samplerate); | |
760 | } else | |
761 | return SR_ERR; | |
762 | break; | |
763 | default: | |
764 | return SR_ERR_NA; | |
765 | } | |
766 | ||
767 | return SR_OK; | |
768 | } | |
769 | ||
770 | static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi, | |
771 | const struct sr_channel_group *cg) | |
772 | { | |
773 | struct dev_context *devc; | |
774 | uint64_t num_samples; | |
775 | int ret; | |
776 | ||
777 | (void)cg; | |
778 | ||
779 | if (sdi->status != SR_ST_ACTIVE) | |
780 | return SR_ERR_DEV_CLOSED; | |
781 | ||
782 | devc = sdi->priv; | |
783 | ||
784 | switch (id) { | |
785 | case SR_CONF_SAMPLERATE: | |
786 | ret = set_samplerate(sdi, g_variant_get_uint64(data)); | |
787 | break; | |
788 | case SR_CONF_LIMIT_MSEC: | |
789 | devc->limit_msec = g_variant_get_uint64(data); | |
790 | if (devc->limit_msec > 0) | |
791 | ret = SR_OK; | |
792 | else | |
793 | ret = SR_ERR; | |
794 | break; | |
795 | case SR_CONF_LIMIT_SAMPLES: | |
796 | num_samples = g_variant_get_uint64(data); | |
797 | devc->limit_msec = num_samples * 1000 / devc->cur_samplerate; | |
798 | break; | |
799 | case SR_CONF_CAPTURE_RATIO: | |
800 | devc->capture_ratio = g_variant_get_uint64(data); | |
801 | if (devc->capture_ratio < 0 || devc->capture_ratio > 100) | |
802 | ret = SR_ERR; | |
803 | else | |
804 | ret = SR_OK; | |
805 | break; | |
806 | default: | |
807 | ret = SR_ERR_NA; | |
808 | } | |
809 | ||
810 | return ret; | |
811 | } | |
812 | ||
813 | static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi, | |
814 | const struct sr_channel_group *cg) | |
815 | { | |
816 | GVariant *gvar; | |
817 | GVariantBuilder gvb; | |
818 | ||
819 | (void)sdi; | |
820 | (void)cg; | |
821 | ||
822 | switch (key) { | |
823 | case SR_CONF_DEVICE_OPTIONS: | |
824 | *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32, | |
825 | hwcaps, ARRAY_SIZE(hwcaps), sizeof(int32_t)); | |
826 | break; | |
827 | case SR_CONF_SAMPLERATE: | |
828 | g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}")); | |
829 | gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates, | |
830 | ARRAY_SIZE(samplerates), sizeof(uint64_t)); | |
831 | g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar); | |
832 | *data = g_variant_builder_end(&gvb); | |
833 | break; | |
834 | case SR_CONF_TRIGGER_TYPE: | |
835 | *data = g_variant_new_string(TRIGGER_TYPE); | |
836 | break; | |
837 | default: | |
838 | return SR_ERR_NA; | |
839 | } | |
840 | ||
841 | return SR_OK; | |
842 | } | |
843 | ||
844 | /* Software trigger to determine exact trigger position. */ | |
845 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
846 | struct sigma_trigger *t) | |
847 | { | |
848 | int i; | |
849 | ||
850 | for (i = 0; i < 8; ++i) { | |
851 | if (i > 0) | |
852 | last_sample = samples[i-1]; | |
853 | ||
854 | /* Simple triggers. */ | |
855 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
856 | continue; | |
857 | ||
858 | /* Rising edge. */ | |
859 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
860 | t->risingmask) != t->risingmask) | |
861 | continue; | |
862 | ||
863 | /* Falling edge. */ | |
864 | if ((last_sample & t->fallingmask) != t->fallingmask || | |
865 | (samples[i] & t->fallingmask) != 0) | |
866 | continue; | |
867 | ||
868 | break; | |
869 | } | |
870 | ||
871 | /* If we did not match, return original trigger pos. */ | |
872 | return i & 0x7; | |
873 | } | |
874 | ||
875 | /* | |
876 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. | |
877 | * Each event is 20ns apart, and can contain multiple samples. | |
878 | * | |
879 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
880 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
881 | * For 50 MHz and below, events contain one sample for each channel, | |
882 | * spread 20 ns apart. | |
883 | */ | |
884 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
885 | uint16_t *lastsample, int triggerpos, | |
886 | uint16_t limit_chunk, void *cb_data) | |
887 | { | |
888 | struct sr_dev_inst *sdi = cb_data; | |
889 | struct dev_context *devc = sdi->priv; | |
890 | uint16_t tsdiff, ts; | |
891 | uint16_t samples[65536 * devc->samples_per_event]; | |
892 | struct sr_datafeed_packet packet; | |
893 | struct sr_datafeed_logic logic; | |
894 | int i, j, k, l, numpad, tosend; | |
895 | size_t n = 0, sent = 0; | |
896 | int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event; | |
897 | uint16_t *event; | |
898 | uint16_t cur_sample; | |
899 | int triggerts = -1; | |
900 | ||
901 | /* Check if trigger is in this chunk. */ | |
902 | if (triggerpos != -1) { | |
903 | if (devc->cur_samplerate <= SR_MHZ(50)) | |
904 | triggerpos -= EVENTS_PER_CLUSTER - 1; | |
905 | ||
906 | if (triggerpos < 0) | |
907 | triggerpos = 0; | |
908 | ||
909 | /* Find in which cluster the trigger occured. */ | |
910 | triggerts = triggerpos / 7; | |
911 | } | |
912 | ||
913 | /* For each ts. */ | |
914 | for (i = 0; i < 64; ++i) { | |
915 | ts = *(uint16_t *) &buf[i * 16]; | |
916 | tsdiff = ts - *lastts; | |
917 | *lastts = ts; | |
918 | ||
919 | /* Decode partial chunk. */ | |
920 | if (limit_chunk && ts > limit_chunk) | |
921 | return SR_OK; | |
922 | ||
923 | /* Pad last sample up to current point. */ | |
924 | numpad = tsdiff * devc->samples_per_event - clustersize; | |
925 | if (numpad > 0) { | |
926 | for (j = 0; j < numpad; ++j) | |
927 | samples[j] = *lastsample; | |
928 | ||
929 | n = numpad; | |
930 | } | |
931 | ||
932 | /* Send samples between previous and this timestamp to sigrok. */ | |
933 | sent = 0; | |
934 | while (sent < n) { | |
935 | tosend = MIN(2048, n - sent); | |
936 | ||
937 | packet.type = SR_DF_LOGIC; | |
938 | packet.payload = &logic; | |
939 | logic.length = tosend * sizeof(uint16_t); | |
940 | logic.unitsize = 2; | |
941 | logic.data = samples + sent; | |
942 | sr_session_send(devc->cb_data, &packet); | |
943 | ||
944 | sent += tosend; | |
945 | } | |
946 | n = 0; | |
947 | ||
948 | event = (uint16_t *) &buf[i * 16 + 2]; | |
949 | cur_sample = 0; | |
950 | ||
951 | /* For each event in cluster. */ | |
952 | for (j = 0; j < 7; ++j) { | |
953 | ||
954 | /* For each sample in event. */ | |
955 | for (k = 0; k < devc->samples_per_event; ++k) { | |
956 | cur_sample = 0; | |
957 | ||
958 | /* For each channel. */ | |
959 | for (l = 0; l < devc->num_channels; ++l) | |
960 | cur_sample |= (!!(event[j] & (1 << (l * | |
961 | devc->samples_per_event + k)))) << l; | |
962 | ||
963 | samples[n++] = cur_sample; | |
964 | } | |
965 | } | |
966 | ||
967 | /* Send data up to trigger point (if triggered). */ | |
968 | sent = 0; | |
969 | if (i == triggerts) { | |
970 | /* | |
971 | * Trigger is not always accurate to sample because of | |
972 | * pipeline delay. However, it always triggers before | |
973 | * the actual event. We therefore look at the next | |
974 | * samples to pinpoint the exact position of the trigger. | |
975 | */ | |
976 | tosend = get_trigger_offset(samples, *lastsample, | |
977 | &devc->trigger); | |
978 | ||
979 | if (tosend > 0) { | |
980 | packet.type = SR_DF_LOGIC; | |
981 | packet.payload = &logic; | |
982 | logic.length = tosend * sizeof(uint16_t); | |
983 | logic.unitsize = 2; | |
984 | logic.data = samples; | |
985 | sr_session_send(devc->cb_data, &packet); | |
986 | ||
987 | sent += tosend; | |
988 | } | |
989 | ||
990 | /* Only send trigger if explicitly enabled. */ | |
991 | if (devc->use_triggers) { | |
992 | packet.type = SR_DF_TRIGGER; | |
993 | sr_session_send(devc->cb_data, &packet); | |
994 | } | |
995 | } | |
996 | ||
997 | /* Send rest of the chunk to sigrok. */ | |
998 | tosend = n - sent; | |
999 | ||
1000 | if (tosend > 0) { | |
1001 | packet.type = SR_DF_LOGIC; | |
1002 | packet.payload = &logic; | |
1003 | logic.length = tosend * sizeof(uint16_t); | |
1004 | logic.unitsize = 2; | |
1005 | logic.data = samples + sent; | |
1006 | sr_session_send(devc->cb_data, &packet); | |
1007 | } | |
1008 | ||
1009 | *lastsample = samples[n - 1]; | |
1010 | } | |
1011 | ||
1012 | return SR_OK; | |
1013 | } | |
1014 | ||
1015 | static void download_capture(struct sr_dev_inst *sdi) | |
1016 | { | |
1017 | struct dev_context *devc; | |
1018 | const int chunks_per_read = 32; | |
1019 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
1020 | int bufsz, i, numchunks, newchunks; | |
1021 | ||
1022 | sr_info("Downloading sample data."); | |
1023 | ||
1024 | devc = sdi->priv; | |
1025 | devc->state.chunks_downloaded = 0; | |
1026 | numchunks = (devc->state.stoppos + 511) / 512; | |
1027 | newchunks = MIN(chunks_per_read, numchunks - devc->state.chunks_downloaded); | |
1028 | ||
1029 | bufsz = sigma_read_dram(devc->state.chunks_downloaded, newchunks, buf, devc); | |
1030 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ | |
1031 | (void)bufsz; | |
1032 | ||
1033 | /* Find first ts. */ | |
1034 | if (devc->state.chunks_downloaded == 0) { | |
1035 | devc->state.lastts = RL16(buf) - 1; | |
1036 | devc->state.lastsample = 0; | |
1037 | } | |
1038 | ||
1039 | /* Decode chunks and send them to sigrok. */ | |
1040 | for (i = 0; i < newchunks; ++i) { | |
1041 | int limit_chunk = 0; | |
1042 | ||
1043 | /* The last chunk may potentially be only in part. */ | |
1044 | if (devc->state.chunks_downloaded == numchunks - 1) { | |
1045 | /* Find the last valid timestamp */ | |
1046 | limit_chunk = devc->state.stoppos % 512 + devc->state.lastts; | |
1047 | } | |
1048 | ||
1049 | if (devc->state.chunks_downloaded + i == devc->state.triggerchunk) | |
1050 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
1051 | &devc->state.lastts, | |
1052 | &devc->state.lastsample, | |
1053 | devc->state.triggerpos & 0x1ff, | |
1054 | limit_chunk, sdi); | |
1055 | else | |
1056 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
1057 | &devc->state.lastts, | |
1058 | &devc->state.lastsample, | |
1059 | -1, limit_chunk, sdi); | |
1060 | ||
1061 | ++devc->state.chunks_downloaded; | |
1062 | } | |
1063 | ||
1064 | } | |
1065 | ||
1066 | static int receive_data(int fd, int revents, void *cb_data) | |
1067 | { | |
1068 | struct sr_dev_inst *sdi; | |
1069 | struct dev_context *devc; | |
1070 | struct sr_datafeed_packet packet; | |
1071 | uint64_t running_msec; | |
1072 | struct timeval tv; | |
1073 | int numchunks; | |
1074 | uint8_t modestatus; | |
1075 | ||
1076 | (void)fd; | |
1077 | (void)revents; | |
1078 | ||
1079 | sdi = cb_data; | |
1080 | devc = sdi->priv; | |
1081 | ||
1082 | /* Get the current position. */ | |
1083 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); | |
1084 | ||
1085 | if (devc->state.state == SIGMA_IDLE) | |
1086 | return TRUE; | |
1087 | ||
1088 | if (devc->state.state == SIGMA_CAPTURE) { | |
1089 | numchunks = (devc->state.stoppos + 511) / 512; | |
1090 | ||
1091 | /* Check if the timer has expired, or memory is full. */ | |
1092 | gettimeofday(&tv, 0); | |
1093 | running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 + | |
1094 | (tv.tv_usec - devc->start_tv.tv_usec) / 1000; | |
1095 | ||
1096 | if (running_msec < devc->limit_msec && numchunks < 32767) | |
1097 | /* Still capturing. */ | |
1098 | return TRUE; | |
1099 | ||
1100 | /* Stop acquisition. */ | |
1101 | sigma_set_register(WRITE_MODE, 0x11, devc); | |
1102 | ||
1103 | /* Set SDRAM Read Enable. */ | |
1104 | sigma_set_register(WRITE_MODE, 0x02, devc); | |
1105 | ||
1106 | /* Get the current position. */ | |
1107 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); | |
1108 | ||
1109 | /* Check if trigger has fired. */ | |
1110 | modestatus = sigma_get_register(READ_MODE, devc); | |
1111 | if (modestatus & 0x20) | |
1112 | devc->state.triggerchunk = devc->state.triggerpos / 512; | |
1113 | else | |
1114 | devc->state.triggerchunk = -1; | |
1115 | ||
1116 | /* Transfer captured data from device. */ | |
1117 | download_capture(sdi); | |
1118 | ||
1119 | /* All done. */ | |
1120 | packet.type = SR_DF_END; | |
1121 | sr_session_send(sdi, &packet); | |
1122 | ||
1123 | dev_acquisition_stop(sdi, sdi); | |
1124 | } | |
1125 | ||
1126 | return TRUE; | |
1127 | } | |
1128 | ||
1129 | /* Build a LUT entry used by the trigger functions. */ | |
1130 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
1131 | { | |
1132 | int i, j, k, bit; | |
1133 | ||
1134 | /* For each quad channel. */ | |
1135 | for (i = 0; i < 4; ++i) { | |
1136 | entry[i] = 0xffff; | |
1137 | ||
1138 | /* For each bit in LUT. */ | |
1139 | for (j = 0; j < 16; ++j) | |
1140 | ||
1141 | /* For each channel in quad. */ | |
1142 | for (k = 0; k < 4; ++k) { | |
1143 | bit = 1 << (i * 4 + k); | |
1144 | ||
1145 | /* Set bit in entry */ | |
1146 | if ((mask & bit) && | |
1147 | ((!(value & bit)) != | |
1148 | (!(j & (1 << k))))) | |
1149 | entry[i] &= ~(1 << j); | |
1150 | } | |
1151 | } | |
1152 | } | |
1153 | ||
1154 | /* Add a logical function to LUT mask. */ | |
1155 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1156 | int index, int neg, uint16_t *mask) | |
1157 | { | |
1158 | int i, j; | |
1159 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1160 | ||
1161 | memset(x, 0, 4 * sizeof(int)); | |
1162 | ||
1163 | /* Trigger detect condition. */ | |
1164 | switch (oper) { | |
1165 | case OP_LEVEL: | |
1166 | x[0][1] = 1; | |
1167 | x[1][1] = 1; | |
1168 | break; | |
1169 | case OP_NOT: | |
1170 | x[0][0] = 1; | |
1171 | x[1][0] = 1; | |
1172 | break; | |
1173 | case OP_RISE: | |
1174 | x[0][1] = 1; | |
1175 | break; | |
1176 | case OP_FALL: | |
1177 | x[1][0] = 1; | |
1178 | break; | |
1179 | case OP_RISEFALL: | |
1180 | x[0][1] = 1; | |
1181 | x[1][0] = 1; | |
1182 | break; | |
1183 | case OP_NOTRISE: | |
1184 | x[1][1] = 1; | |
1185 | x[0][0] = 1; | |
1186 | x[1][0] = 1; | |
1187 | break; | |
1188 | case OP_NOTFALL: | |
1189 | x[1][1] = 1; | |
1190 | x[0][0] = 1; | |
1191 | x[0][1] = 1; | |
1192 | break; | |
1193 | case OP_NOTRISEFALL: | |
1194 | x[1][1] = 1; | |
1195 | x[0][0] = 1; | |
1196 | break; | |
1197 | } | |
1198 | ||
1199 | /* Transpose if neg is set. */ | |
1200 | if (neg) { | |
1201 | for (i = 0; i < 2; ++i) { | |
1202 | for (j = 0; j < 2; ++j) { | |
1203 | tmp = x[i][j]; | |
1204 | x[i][j] = x[1-i][1-j]; | |
1205 | x[1-i][1-j] = tmp; | |
1206 | } | |
1207 | } | |
1208 | } | |
1209 | ||
1210 | /* Update mask with function. */ | |
1211 | for (i = 0; i < 16; ++i) { | |
1212 | a = (i >> (2 * index + 0)) & 1; | |
1213 | b = (i >> (2 * index + 1)) & 1; | |
1214 | ||
1215 | aset = (*mask >> i) & 1; | |
1216 | bset = x[b][a]; | |
1217 | ||
1218 | if (func == FUNC_AND || func == FUNC_NAND) | |
1219 | rset = aset & bset; | |
1220 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1221 | rset = aset | bset; | |
1222 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1223 | rset = aset ^ bset; | |
1224 | ||
1225 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1226 | rset = !rset; | |
1227 | ||
1228 | *mask &= ~(1 << i); | |
1229 | ||
1230 | if (rset) | |
1231 | *mask |= 1 << i; | |
1232 | } | |
1233 | } | |
1234 | ||
1235 | /* | |
1236 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1237 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1238 | * set at any time, but a full mask and value can be set (0/1). | |
1239 | */ | |
1240 | static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc) | |
1241 | { | |
1242 | int i,j; | |
1243 | uint16_t masks[2] = { 0, 0 }; | |
1244 | ||
1245 | memset(lut, 0, sizeof(struct triggerlut)); | |
1246 | ||
1247 | /* Contant for simple triggers. */ | |
1248 | lut->m4 = 0xa000; | |
1249 | ||
1250 | /* Value/mask trigger support. */ | |
1251 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, | |
1252 | lut->m2d); | |
1253 | ||
1254 | /* Rise/fall trigger support. */ | |
1255 | for (i = 0, j = 0; i < 16; ++i) { | |
1256 | if (devc->trigger.risingmask & (1 << i) || | |
1257 | devc->trigger.fallingmask & (1 << i)) | |
1258 | masks[j++] = 1 << i; | |
1259 | } | |
1260 | ||
1261 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1262 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1263 | ||
1264 | /* Add glue logic */ | |
1265 | if (masks[0] || masks[1]) { | |
1266 | /* Transition trigger. */ | |
1267 | if (masks[0] & devc->trigger.risingmask) | |
1268 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); | |
1269 | if (masks[0] & devc->trigger.fallingmask) | |
1270 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); | |
1271 | if (masks[1] & devc->trigger.risingmask) | |
1272 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); | |
1273 | if (masks[1] & devc->trigger.fallingmask) | |
1274 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); | |
1275 | } else { | |
1276 | /* Only value/mask trigger. */ | |
1277 | lut->m3 = 0xffff; | |
1278 | } | |
1279 | ||
1280 | /* Triggertype: event. */ | |
1281 | lut->params.selres = 3; | |
1282 | ||
1283 | return SR_OK; | |
1284 | } | |
1285 | ||
1286 | static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data) | |
1287 | { | |
1288 | struct dev_context *devc; | |
1289 | struct clockselect_50 clockselect; | |
1290 | int frac, triggerpin, ret; | |
1291 | uint8_t triggerselect = 0; | |
1292 | struct triggerinout triggerinout_conf; | |
1293 | struct triggerlut lut; | |
1294 | ||
1295 | if (sdi->status != SR_ST_ACTIVE) | |
1296 | return SR_ERR_DEV_CLOSED; | |
1297 | ||
1298 | devc = sdi->priv; | |
1299 | ||
1300 | if (configure_channels(sdi) != SR_OK) { | |
1301 | sr_err("Failed to configure channels."); | |
1302 | return SR_ERR; | |
1303 | } | |
1304 | ||
1305 | /* If the samplerate has not been set, default to 200 kHz. */ | |
1306 | if (devc->cur_firmware == -1) { | |
1307 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) | |
1308 | return ret; | |
1309 | } | |
1310 | ||
1311 | /* Enter trigger programming mode. */ | |
1312 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc); | |
1313 | ||
1314 | /* 100 and 200 MHz mode. */ | |
1315 | if (devc->cur_samplerate >= SR_MHZ(100)) { | |
1316 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc); | |
1317 | ||
1318 | /* Find which pin to trigger on from mask. */ | |
1319 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
1320 | if ((devc->trigger.risingmask | devc->trigger.fallingmask) & | |
1321 | (1 << triggerpin)) | |
1322 | break; | |
1323 | ||
1324 | /* Set trigger pin and light LED on trigger. */ | |
1325 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1326 | ||
1327 | /* Default rising edge. */ | |
1328 | if (devc->trigger.fallingmask) | |
1329 | triggerselect |= 1 << 3; | |
1330 | ||
1331 | /* All other modes. */ | |
1332 | } else if (devc->cur_samplerate <= SR_MHZ(50)) { | |
1333 | build_basic_trigger(&lut, devc); | |
1334 | ||
1335 | sigma_write_trigger_lut(&lut, devc); | |
1336 | ||
1337 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1338 | } | |
1339 | ||
1340 | /* Setup trigger in and out pins to default values. */ | |
1341 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); | |
1342 | triggerinout_conf.trgout_bytrigger = 1; | |
1343 | triggerinout_conf.trgout_enable = 1; | |
1344 | ||
1345 | sigma_write_register(WRITE_TRIGGER_OPTION, | |
1346 | (uint8_t *) &triggerinout_conf, | |
1347 | sizeof(struct triggerinout), devc); | |
1348 | ||
1349 | /* Go back to normal mode. */ | |
1350 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc); | |
1351 | ||
1352 | /* Set clock select register. */ | |
1353 | if (devc->cur_samplerate == SR_MHZ(200)) | |
1354 | /* Enable 4 channels. */ | |
1355 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc); | |
1356 | else if (devc->cur_samplerate == SR_MHZ(100)) | |
1357 | /* Enable 8 channels. */ | |
1358 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc); | |
1359 | else { | |
1360 | /* | |
1361 | * 50 MHz mode (or fraction thereof). Any fraction down to | |
1362 | * 50 MHz / 256 can be used, but is not supported by sigrok API. | |
1363 | */ | |
1364 | frac = SR_MHZ(50) / devc->cur_samplerate - 1; | |
1365 | ||
1366 | clockselect.async = 0; | |
1367 | clockselect.fraction = frac; | |
1368 | clockselect.disabled_channels = 0; | |
1369 | ||
1370 | sigma_write_register(WRITE_CLOCK_SELECT, | |
1371 | (uint8_t *) &clockselect, | |
1372 | sizeof(clockselect), devc); | |
1373 | } | |
1374 | ||
1375 | /* Setup maximum post trigger time. */ | |
1376 | sigma_set_register(WRITE_POST_TRIGGER, | |
1377 | (devc->capture_ratio * 255) / 100, devc); | |
1378 | ||
1379 | /* Start acqusition. */ | |
1380 | gettimeofday(&devc->start_tv, 0); | |
1381 | sigma_set_register(WRITE_MODE, 0x0d, devc); | |
1382 | ||
1383 | devc->cb_data = cb_data; | |
1384 | ||
1385 | /* Send header packet to the session bus. */ | |
1386 | std_session_send_df_header(cb_data, LOG_PREFIX); | |
1387 | ||
1388 | /* Add capture source. */ | |
1389 | sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi); | |
1390 | ||
1391 | devc->state.state = SIGMA_CAPTURE; | |
1392 | ||
1393 | return SR_OK; | |
1394 | } | |
1395 | ||
1396 | static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data) | |
1397 | { | |
1398 | struct dev_context *devc; | |
1399 | ||
1400 | (void)cb_data; | |
1401 | ||
1402 | devc = sdi->priv; | |
1403 | devc->state.state = SIGMA_IDLE; | |
1404 | ||
1405 | sr_source_remove(0); | |
1406 | ||
1407 | return SR_OK; | |
1408 | } | |
1409 | ||
1410 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info = { | |
1411 | .name = "asix-sigma", | |
1412 | .longname = "ASIX SIGMA/SIGMA2", | |
1413 | .api_version = 1, | |
1414 | .init = init, | |
1415 | .cleanup = cleanup, | |
1416 | .scan = scan, | |
1417 | .dev_list = dev_list, | |
1418 | .dev_clear = dev_clear, | |
1419 | .config_get = config_get, | |
1420 | .config_set = config_set, | |
1421 | .config_list = config_list, | |
1422 | .dev_open = dev_open, | |
1423 | .dev_close = dev_close, | |
1424 | .dev_acquisition_start = dev_acquisition_start, | |
1425 | .dev_acquisition_stop = dev_acquisition_stop, | |
1426 | .priv = NULL, | |
1427 | }; |