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1 | /* | |
2 | * This file is part of the sigrok project. | |
3 | * | |
4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, | |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
7 | * | |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | /* | |
23 | * ASIX SIGMA/SIGMA2 logic analyzer driver | |
24 | */ | |
25 | ||
26 | #include <glib.h> | |
27 | #include <glib/gstdio.h> | |
28 | #include <ftdi.h> | |
29 | #include <string.h> | |
30 | #include "libsigrok.h" | |
31 | #include "libsigrok-internal.h" | |
32 | #include "asix-sigma.h" | |
33 | ||
34 | #define USB_VENDOR 0xa600 | |
35 | #define USB_PRODUCT 0xa000 | |
36 | #define USB_DESCRIPTION "ASIX SIGMA" | |
37 | #define USB_VENDOR_NAME "ASIX" | |
38 | #define USB_MODEL_NAME "SIGMA" | |
39 | #define USB_MODEL_VERSION "" | |
40 | #define TRIGGER_TYPE "rf10" | |
41 | #define NUM_PROBES 16 | |
42 | ||
43 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info; | |
44 | static struct sr_dev_driver *di = &asix_sigma_driver_info; | |
45 | static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data); | |
46 | ||
47 | static const uint64_t supported_samplerates[] = { | |
48 | SR_KHZ(200), | |
49 | SR_KHZ(250), | |
50 | SR_KHZ(500), | |
51 | SR_MHZ(1), | |
52 | SR_MHZ(5), | |
53 | SR_MHZ(10), | |
54 | SR_MHZ(25), | |
55 | SR_MHZ(50), | |
56 | SR_MHZ(100), | |
57 | SR_MHZ(200), | |
58 | 0, | |
59 | }; | |
60 | ||
61 | /* | |
62 | * Probe numbers seem to go from 1-16, according to this image: | |
63 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg | |
64 | * (the cable has two additional GND pins, and a TI and TO pin) | |
65 | */ | |
66 | static const char *probe_names[NUM_PROBES + 1] = { | |
67 | "1", "2", "3", "4", "5", "6", "7", "8", | |
68 | "9", "10", "11", "12", "13", "14", "15", "16", | |
69 | NULL, | |
70 | }; | |
71 | ||
72 | static const struct sr_samplerates samplerates = { | |
73 | .low = 0, | |
74 | .high = 0, | |
75 | .step = 0, | |
76 | .list = supported_samplerates, | |
77 | }; | |
78 | ||
79 | static const int hwcaps[] = { | |
80 | SR_CONF_LOGIC_ANALYZER, | |
81 | SR_CONF_SAMPLERATE, | |
82 | SR_CONF_CAPTURE_RATIO, | |
83 | ||
84 | SR_CONF_LIMIT_MSEC, | |
85 | 0, | |
86 | }; | |
87 | ||
88 | /* Force the FPGA to reboot. */ | |
89 | static uint8_t suicide[] = { | |
90 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
91 | }; | |
92 | ||
93 | /* Prepare to upload firmware (FPGA specific). */ | |
94 | static uint8_t init[] = { | |
95 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, | |
96 | }; | |
97 | ||
98 | /* Initialize the logic analyzer mode. */ | |
99 | static uint8_t logic_mode_start[] = { | |
100 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
101 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
102 | }; | |
103 | ||
104 | static const char *firmware_files[] = { | |
105 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ | |
106 | "asix-sigma-100.fw", /* 100 MHz */ | |
107 | "asix-sigma-200.fw", /* 200 MHz */ | |
108 | "asix-sigma-50sync.fw", /* Synchronous clock from pin */ | |
109 | "asix-sigma-phasor.fw", /* Frequency counter */ | |
110 | }; | |
111 | ||
112 | static int sigma_read(void *buf, size_t size, struct dev_context *devc) | |
113 | { | |
114 | int ret; | |
115 | ||
116 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); | |
117 | if (ret < 0) { | |
118 | sr_err("ftdi_read_data failed: %s", | |
119 | ftdi_get_error_string(&devc->ftdic)); | |
120 | } | |
121 | ||
122 | return ret; | |
123 | } | |
124 | ||
125 | static int sigma_write(void *buf, size_t size, struct dev_context *devc) | |
126 | { | |
127 | int ret; | |
128 | ||
129 | ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); | |
130 | if (ret < 0) { | |
131 | sr_err("ftdi_write_data failed: %s", | |
132 | ftdi_get_error_string(&devc->ftdic)); | |
133 | } else if ((size_t) ret != size) { | |
134 | sr_err("ftdi_write_data did not complete write."); | |
135 | } | |
136 | ||
137 | return ret; | |
138 | } | |
139 | ||
140 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, | |
141 | struct dev_context *devc) | |
142 | { | |
143 | size_t i; | |
144 | uint8_t buf[len + 2]; | |
145 | int idx = 0; | |
146 | ||
147 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
148 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
149 | ||
150 | for (i = 0; i < len; ++i) { | |
151 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); | |
152 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
153 | } | |
154 | ||
155 | return sigma_write(buf, idx, devc); | |
156 | } | |
157 | ||
158 | static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc) | |
159 | { | |
160 | return sigma_write_register(reg, &value, 1, devc); | |
161 | } | |
162 | ||
163 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, | |
164 | struct dev_context *devc) | |
165 | { | |
166 | uint8_t buf[3]; | |
167 | ||
168 | buf[0] = REG_ADDR_LOW | (reg & 0xf); | |
169 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
170 | buf[2] = REG_READ_ADDR; | |
171 | ||
172 | sigma_write(buf, sizeof(buf), devc); | |
173 | ||
174 | return sigma_read(data, len, devc); | |
175 | } | |
176 | ||
177 | static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc) | |
178 | { | |
179 | uint8_t value; | |
180 | ||
181 | if (1 != sigma_read_register(reg, &value, 1, devc)) { | |
182 | sr_err("sigma_get_register: 1 byte expected"); | |
183 | return 0; | |
184 | } | |
185 | ||
186 | return value; | |
187 | } | |
188 | ||
189 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, | |
190 | struct dev_context *devc) | |
191 | { | |
192 | uint8_t buf[] = { | |
193 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
194 | ||
195 | REG_READ_ADDR | NEXT_REG, | |
196 | REG_READ_ADDR | NEXT_REG, | |
197 | REG_READ_ADDR | NEXT_REG, | |
198 | REG_READ_ADDR | NEXT_REG, | |
199 | REG_READ_ADDR | NEXT_REG, | |
200 | REG_READ_ADDR | NEXT_REG, | |
201 | }; | |
202 | uint8_t result[6]; | |
203 | ||
204 | sigma_write(buf, sizeof(buf), devc); | |
205 | ||
206 | sigma_read(result, sizeof(result), devc); | |
207 | ||
208 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
209 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
210 | ||
211 | /* Not really sure why this must be done, but according to spec. */ | |
212 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
213 | stoppos -= 64; | |
214 | ||
215 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
216 | triggerpos -= 64; | |
217 | ||
218 | return 1; | |
219 | } | |
220 | ||
221 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, | |
222 | uint8_t *data, struct dev_context *devc) | |
223 | { | |
224 | size_t i; | |
225 | uint8_t buf[4096]; | |
226 | int idx = 0; | |
227 | ||
228 | /* Send the startchunk. Index start with 1. */ | |
229 | buf[0] = startchunk >> 8; | |
230 | buf[1] = startchunk & 0xff; | |
231 | sigma_write_register(WRITE_MEMROW, buf, 2, devc); | |
232 | ||
233 | /* Read the DRAM. */ | |
234 | buf[idx++] = REG_DRAM_BLOCK; | |
235 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
236 | ||
237 | for (i = 0; i < numchunks; ++i) { | |
238 | /* Alternate bit to copy from DRAM to cache. */ | |
239 | if (i != (numchunks - 1)) | |
240 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
241 | ||
242 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
243 | ||
244 | if (i != (numchunks - 1)) | |
245 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
246 | } | |
247 | ||
248 | sigma_write(buf, idx, devc); | |
249 | ||
250 | return sigma_read(data, numchunks * CHUNK_SIZE, devc); | |
251 | } | |
252 | ||
253 | /* Upload trigger look-up tables to Sigma. */ | |
254 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc) | |
255 | { | |
256 | int i; | |
257 | uint8_t tmp[2]; | |
258 | uint16_t bit; | |
259 | ||
260 | /* Transpose the table and send to Sigma. */ | |
261 | for (i = 0; i < 16; ++i) { | |
262 | bit = 1 << i; | |
263 | ||
264 | tmp[0] = tmp[1] = 0; | |
265 | ||
266 | if (lut->m2d[0] & bit) | |
267 | tmp[0] |= 0x01; | |
268 | if (lut->m2d[1] & bit) | |
269 | tmp[0] |= 0x02; | |
270 | if (lut->m2d[2] & bit) | |
271 | tmp[0] |= 0x04; | |
272 | if (lut->m2d[3] & bit) | |
273 | tmp[0] |= 0x08; | |
274 | ||
275 | if (lut->m3 & bit) | |
276 | tmp[0] |= 0x10; | |
277 | if (lut->m3s & bit) | |
278 | tmp[0] |= 0x20; | |
279 | if (lut->m4 & bit) | |
280 | tmp[0] |= 0x40; | |
281 | ||
282 | if (lut->m0d[0] & bit) | |
283 | tmp[1] |= 0x01; | |
284 | if (lut->m0d[1] & bit) | |
285 | tmp[1] |= 0x02; | |
286 | if (lut->m0d[2] & bit) | |
287 | tmp[1] |= 0x04; | |
288 | if (lut->m0d[3] & bit) | |
289 | tmp[1] |= 0x08; | |
290 | ||
291 | if (lut->m1d[0] & bit) | |
292 | tmp[1] |= 0x10; | |
293 | if (lut->m1d[1] & bit) | |
294 | tmp[1] |= 0x20; | |
295 | if (lut->m1d[2] & bit) | |
296 | tmp[1] |= 0x40; | |
297 | if (lut->m1d[3] & bit) | |
298 | tmp[1] |= 0x80; | |
299 | ||
300 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), | |
301 | devc); | |
302 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); | |
303 | } | |
304 | ||
305 | /* Send the parameters */ | |
306 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
307 | sizeof(lut->params), devc); | |
308 | ||
309 | return SR_OK; | |
310 | } | |
311 | ||
312 | /* Generate the bitbang stream for programming the FPGA. */ | |
313 | static int bin2bitbang(const char *filename, | |
314 | unsigned char **buf, size_t *buf_size) | |
315 | { | |
316 | FILE *f; | |
317 | unsigned long file_size; | |
318 | unsigned long offset = 0; | |
319 | unsigned char *p; | |
320 | uint8_t *firmware; | |
321 | unsigned long fwsize = 0; | |
322 | const int buffer_size = 65536; | |
323 | size_t i; | |
324 | int c, bit, v; | |
325 | uint32_t imm = 0x3f6df2ab; | |
326 | ||
327 | f = g_fopen(filename, "rb"); | |
328 | if (!f) { | |
329 | sr_err("g_fopen(\"%s\", \"rb\")", filename); | |
330 | return SR_ERR; | |
331 | } | |
332 | ||
333 | if (-1 == fseek(f, 0, SEEK_END)) { | |
334 | sr_err("fseek on %s failed", filename); | |
335 | fclose(f); | |
336 | return SR_ERR; | |
337 | } | |
338 | ||
339 | file_size = ftell(f); | |
340 | ||
341 | fseek(f, 0, SEEK_SET); | |
342 | ||
343 | if (!(firmware = g_try_malloc(buffer_size))) { | |
344 | sr_err("%s: firmware malloc failed", __func__); | |
345 | fclose(f); | |
346 | return SR_ERR_MALLOC; | |
347 | } | |
348 | ||
349 | while ((c = getc(f)) != EOF) { | |
350 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
351 | firmware[fwsize++] = c ^ imm; | |
352 | } | |
353 | fclose(f); | |
354 | ||
355 | if(fwsize != file_size) { | |
356 | sr_err("%s: Error reading firmware", filename); | |
357 | fclose(f); | |
358 | g_free(firmware); | |
359 | return SR_ERR; | |
360 | } | |
361 | ||
362 | *buf_size = fwsize * 2 * 8; | |
363 | ||
364 | *buf = p = (unsigned char *)g_try_malloc(*buf_size); | |
365 | if (!p) { | |
366 | sr_err("%s: buf/p malloc failed", __func__); | |
367 | g_free(firmware); | |
368 | return SR_ERR_MALLOC; | |
369 | } | |
370 | ||
371 | for (i = 0; i < fwsize; ++i) { | |
372 | for (bit = 7; bit >= 0; --bit) { | |
373 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; | |
374 | p[offset++] = v | 0x01; | |
375 | p[offset++] = v; | |
376 | } | |
377 | } | |
378 | ||
379 | g_free(firmware); | |
380 | ||
381 | if (offset != *buf_size) { | |
382 | g_free(*buf); | |
383 | sr_err("Error reading firmware %s " | |
384 | "offset=%ld, file_size=%ld, buf_size=%zd.", | |
385 | filename, offset, file_size, *buf_size); | |
386 | ||
387 | return SR_ERR; | |
388 | } | |
389 | ||
390 | return SR_OK; | |
391 | } | |
392 | ||
393 | static int clear_instances(void) | |
394 | { | |
395 | GSList *l; | |
396 | struct sr_dev_inst *sdi; | |
397 | struct drv_context *drvc; | |
398 | struct dev_context *devc; | |
399 | ||
400 | drvc = di->priv; | |
401 | ||
402 | /* Properly close all devices. */ | |
403 | for (l = drvc->instances; l; l = l->next) { | |
404 | if (!(sdi = l->data)) { | |
405 | /* Log error, but continue cleaning up the rest. */ | |
406 | sr_err("%s: sdi was NULL, continuing", __func__); | |
407 | continue; | |
408 | } | |
409 | if (sdi->priv) { | |
410 | devc = sdi->priv; | |
411 | ftdi_free(&devc->ftdic); | |
412 | } | |
413 | sr_dev_inst_free(sdi); | |
414 | } | |
415 | g_slist_free(drvc->instances); | |
416 | drvc->instances = NULL; | |
417 | ||
418 | return SR_OK; | |
419 | } | |
420 | ||
421 | static int hw_init(struct sr_context *sr_ctx) | |
422 | { | |
423 | return std_hw_init(sr_ctx, di, DRIVER_LOG_DOMAIN); | |
424 | } | |
425 | ||
426 | static GSList *hw_scan(GSList *options) | |
427 | { | |
428 | struct sr_dev_inst *sdi; | |
429 | struct sr_probe *probe; | |
430 | struct drv_context *drvc; | |
431 | struct dev_context *devc; | |
432 | GSList *devices; | |
433 | struct ftdi_device_list *devlist; | |
434 | char serial_txt[10]; | |
435 | uint32_t serial; | |
436 | int ret, i; | |
437 | ||
438 | (void)options; | |
439 | ||
440 | drvc = di->priv; | |
441 | ||
442 | devices = NULL; | |
443 | ||
444 | clear_instances(); | |
445 | ||
446 | if (!(devc = g_try_malloc(sizeof(struct dev_context)))) { | |
447 | sr_err("%s: devc malloc failed", __func__); | |
448 | return NULL; | |
449 | } | |
450 | ||
451 | ftdi_init(&devc->ftdic); | |
452 | ||
453 | /* Look for SIGMAs. */ | |
454 | ||
455 | if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist, | |
456 | USB_VENDOR, USB_PRODUCT)) <= 0) { | |
457 | if (ret < 0) | |
458 | sr_err("ftdi_usb_find_all(): %d", ret); | |
459 | goto free; | |
460 | } | |
461 | ||
462 | /* Make sure it's a version 1 or 2 SIGMA. */ | |
463 | ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0, | |
464 | serial_txt, sizeof(serial_txt)); | |
465 | sscanf(serial_txt, "%x", &serial); | |
466 | ||
467 | if (serial < 0xa6010000 || serial > 0xa602ffff) { | |
468 | sr_err("Only SIGMA and SIGMA2 are supported " | |
469 | "in this version of libsigrok."); | |
470 | goto free; | |
471 | } | |
472 | ||
473 | sr_info("Found ASIX SIGMA - Serial: %s", serial_txt); | |
474 | ||
475 | devc->cur_samplerate = 0; | |
476 | devc->period_ps = 0; | |
477 | devc->limit_msec = 0; | |
478 | devc->cur_firmware = -1; | |
479 | devc->num_probes = 0; | |
480 | devc->samples_per_event = 0; | |
481 | devc->capture_ratio = 50; | |
482 | devc->use_triggers = 0; | |
483 | ||
484 | /* Register SIGMA device. */ | |
485 | if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME, | |
486 | USB_MODEL_NAME, USB_MODEL_VERSION))) { | |
487 | sr_err("%s: sdi was NULL", __func__); | |
488 | goto free; | |
489 | } | |
490 | sdi->driver = di; | |
491 | ||
492 | for (i = 0; probe_names[i]; i++) { | |
493 | if (!(probe = sr_probe_new(i, SR_PROBE_LOGIC, TRUE, | |
494 | probe_names[i]))) | |
495 | return NULL; | |
496 | sdi->probes = g_slist_append(sdi->probes, probe); | |
497 | } | |
498 | ||
499 | devices = g_slist_append(devices, sdi); | |
500 | drvc->instances = g_slist_append(drvc->instances, sdi); | |
501 | sdi->priv = devc; | |
502 | ||
503 | /* We will open the device again when we need it. */ | |
504 | ftdi_list_free(&devlist); | |
505 | ||
506 | return devices; | |
507 | ||
508 | free: | |
509 | ftdi_deinit(&devc->ftdic); | |
510 | g_free(devc); | |
511 | return NULL; | |
512 | } | |
513 | ||
514 | static GSList *hw_dev_list(void) | |
515 | { | |
516 | return ((struct drv_context *)(di->priv))->instances; | |
517 | } | |
518 | ||
519 | static int upload_firmware(int firmware_idx, struct dev_context *devc) | |
520 | { | |
521 | int ret; | |
522 | unsigned char *buf; | |
523 | unsigned char pins; | |
524 | size_t buf_size; | |
525 | unsigned char result[32]; | |
526 | char firmware_path[128]; | |
527 | ||
528 | /* Make sure it's an ASIX SIGMA. */ | |
529 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, | |
530 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { | |
531 | sr_err("ftdi_usb_open failed: %s", | |
532 | ftdi_get_error_string(&devc->ftdic)); | |
533 | return 0; | |
534 | } | |
535 | ||
536 | if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) { | |
537 | sr_err("ftdi_set_bitmode failed: %s", | |
538 | ftdi_get_error_string(&devc->ftdic)); | |
539 | return 0; | |
540 | } | |
541 | ||
542 | /* Four times the speed of sigmalogan - Works well. */ | |
543 | if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) { | |
544 | sr_err("ftdi_set_baudrate failed: %s", | |
545 | ftdi_get_error_string(&devc->ftdic)); | |
546 | return 0; | |
547 | } | |
548 | ||
549 | /* Force the FPGA to reboot. */ | |
550 | sigma_write(suicide, sizeof(suicide), devc); | |
551 | sigma_write(suicide, sizeof(suicide), devc); | |
552 | sigma_write(suicide, sizeof(suicide), devc); | |
553 | sigma_write(suicide, sizeof(suicide), devc); | |
554 | ||
555 | /* Prepare to upload firmware (FPGA specific). */ | |
556 | sigma_write(init, sizeof(init), devc); | |
557 | ||
558 | ftdi_usb_purge_buffers(&devc->ftdic); | |
559 | ||
560 | /* Wait until the FPGA asserts INIT_B. */ | |
561 | while (1) { | |
562 | ret = sigma_read(result, 1, devc); | |
563 | if (result[0] & 0x20) | |
564 | break; | |
565 | } | |
566 | ||
567 | /* Prepare firmware. */ | |
568 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, | |
569 | firmware_files[firmware_idx]); | |
570 | ||
571 | if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) { | |
572 | sr_err("An error occured while reading the firmware: %s", | |
573 | firmware_path); | |
574 | return ret; | |
575 | } | |
576 | ||
577 | /* Upload firmare. */ | |
578 | sr_info("Uploading firmware file '%s'.", firmware_files[firmware_idx]); | |
579 | sigma_write(buf, buf_size, devc); | |
580 | ||
581 | g_free(buf); | |
582 | ||
583 | if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) { | |
584 | sr_err("ftdi_set_bitmode failed: %s", | |
585 | ftdi_get_error_string(&devc->ftdic)); | |
586 | return SR_ERR; | |
587 | } | |
588 | ||
589 | ftdi_usb_purge_buffers(&devc->ftdic); | |
590 | ||
591 | /* Discard garbage. */ | |
592 | while (1 == sigma_read(&pins, 1, devc)) | |
593 | ; | |
594 | ||
595 | /* Initialize the logic analyzer mode. */ | |
596 | sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); | |
597 | ||
598 | /* Expect a 3 byte reply. */ | |
599 | ret = sigma_read(result, 3, devc); | |
600 | if (ret != 3 || | |
601 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
602 | sr_err("Configuration failed. Invalid reply received."); | |
603 | return SR_ERR; | |
604 | } | |
605 | ||
606 | devc->cur_firmware = firmware_idx; | |
607 | ||
608 | sr_info("Firmware uploaded."); | |
609 | ||
610 | return SR_OK; | |
611 | } | |
612 | ||
613 | static int hw_dev_open(struct sr_dev_inst *sdi) | |
614 | { | |
615 | struct dev_context *devc; | |
616 | int ret; | |
617 | ||
618 | devc = sdi->priv; | |
619 | ||
620 | /* Make sure it's an ASIX SIGMA. */ | |
621 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, | |
622 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { | |
623 | ||
624 | sr_err("ftdi_usb_open failed: %s", | |
625 | ftdi_get_error_string(&devc->ftdic)); | |
626 | ||
627 | return 0; | |
628 | } | |
629 | ||
630 | sdi->status = SR_ST_ACTIVE; | |
631 | ||
632 | return SR_OK; | |
633 | } | |
634 | ||
635 | static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) | |
636 | { | |
637 | int i, ret; | |
638 | struct dev_context *devc = sdi->priv; | |
639 | ||
640 | ret = SR_OK; | |
641 | ||
642 | for (i = 0; supported_samplerates[i]; i++) { | |
643 | if (supported_samplerates[i] == samplerate) | |
644 | break; | |
645 | } | |
646 | if (supported_samplerates[i] == 0) | |
647 | return SR_ERR_SAMPLERATE; | |
648 | ||
649 | if (samplerate <= SR_MHZ(50)) { | |
650 | ret = upload_firmware(0, devc); | |
651 | devc->num_probes = 16; | |
652 | } | |
653 | if (samplerate == SR_MHZ(100)) { | |
654 | ret = upload_firmware(1, devc); | |
655 | devc->num_probes = 8; | |
656 | } | |
657 | else if (samplerate == SR_MHZ(200)) { | |
658 | ret = upload_firmware(2, devc); | |
659 | devc->num_probes = 4; | |
660 | } | |
661 | ||
662 | devc->cur_samplerate = samplerate; | |
663 | devc->period_ps = 1000000000000ULL / samplerate; | |
664 | devc->samples_per_event = 16 / devc->num_probes; | |
665 | devc->state.state = SIGMA_IDLE; | |
666 | ||
667 | return ret; | |
668 | } | |
669 | ||
670 | /* | |
671 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
672 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
673 | * in addition to value/mask trigger for any number of probes. | |
674 | * | |
675 | * The Sigma supports complex triggers using boolean expressions, but this | |
676 | * has not been implemented yet. | |
677 | */ | |
678 | static int configure_probes(const struct sr_dev_inst *sdi) | |
679 | { | |
680 | struct dev_context *devc = sdi->priv; | |
681 | const struct sr_probe *probe; | |
682 | const GSList *l; | |
683 | int trigger_set = 0; | |
684 | int probebit; | |
685 | ||
686 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); | |
687 | ||
688 | for (l = sdi->probes; l; l = l->next) { | |
689 | probe = (struct sr_probe *)l->data; | |
690 | probebit = 1 << (probe->index); | |
691 | ||
692 | if (!probe->enabled || !probe->trigger) | |
693 | continue; | |
694 | ||
695 | if (devc->cur_samplerate >= SR_MHZ(100)) { | |
696 | /* Fast trigger support. */ | |
697 | if (trigger_set) { | |
698 | sr_err("Only a single pin trigger in 100 and " | |
699 | "200MHz mode is supported."); | |
700 | return SR_ERR; | |
701 | } | |
702 | if (probe->trigger[0] == 'f') | |
703 | devc->trigger.fallingmask |= probebit; | |
704 | else if (probe->trigger[0] == 'r') | |
705 | devc->trigger.risingmask |= probebit; | |
706 | else { | |
707 | sr_err("Only rising/falling trigger in 100 " | |
708 | "and 200MHz mode is supported."); | |
709 | return SR_ERR; | |
710 | } | |
711 | ||
712 | ++trigger_set; | |
713 | } else { | |
714 | /* Simple trigger support (event). */ | |
715 | if (probe->trigger[0] == '1') { | |
716 | devc->trigger.simplevalue |= probebit; | |
717 | devc->trigger.simplemask |= probebit; | |
718 | } | |
719 | else if (probe->trigger[0] == '0') { | |
720 | devc->trigger.simplevalue &= ~probebit; | |
721 | devc->trigger.simplemask |= probebit; | |
722 | } | |
723 | else if (probe->trigger[0] == 'f') { | |
724 | devc->trigger.fallingmask |= probebit; | |
725 | ++trigger_set; | |
726 | } | |
727 | else if (probe->trigger[0] == 'r') { | |
728 | devc->trigger.risingmask |= probebit; | |
729 | ++trigger_set; | |
730 | } | |
731 | ||
732 | /* | |
733 | * Actually, Sigma supports 2 rising/falling triggers, | |
734 | * but they are ORed and the current trigger syntax | |
735 | * does not permit ORed triggers. | |
736 | */ | |
737 | if (trigger_set > 1) { | |
738 | sr_err("Only 1 rising/falling trigger " | |
739 | "is supported."); | |
740 | return SR_ERR; | |
741 | } | |
742 | } | |
743 | ||
744 | if (trigger_set) | |
745 | devc->use_triggers = 1; | |
746 | } | |
747 | ||
748 | return SR_OK; | |
749 | } | |
750 | ||
751 | static int hw_dev_close(struct sr_dev_inst *sdi) | |
752 | { | |
753 | struct dev_context *devc; | |
754 | ||
755 | devc = sdi->priv; | |
756 | ||
757 | /* TODO */ | |
758 | if (sdi->status == SR_ST_ACTIVE) | |
759 | ftdi_usb_close(&devc->ftdic); | |
760 | ||
761 | sdi->status = SR_ST_INACTIVE; | |
762 | ||
763 | return SR_OK; | |
764 | } | |
765 | ||
766 | static int hw_cleanup(void) | |
767 | { | |
768 | if (!di->priv) | |
769 | return SR_OK; | |
770 | ||
771 | clear_instances(); | |
772 | ||
773 | return SR_OK; | |
774 | } | |
775 | ||
776 | static int config_get(int id, const void **data, const struct sr_dev_inst *sdi) | |
777 | { | |
778 | struct dev_context *devc; | |
779 | ||
780 | switch (id) { | |
781 | case SR_CONF_SAMPLERATE: | |
782 | if (sdi) { | |
783 | devc = sdi->priv; | |
784 | *data = &devc->cur_samplerate; | |
785 | } else | |
786 | return SR_ERR; | |
787 | break; | |
788 | default: | |
789 | return SR_ERR_ARG; | |
790 | } | |
791 | ||
792 | return SR_OK; | |
793 | } | |
794 | ||
795 | static int config_set(int id, const void *value, const struct sr_dev_inst *sdi) | |
796 | { | |
797 | struct dev_context *devc; | |
798 | int ret; | |
799 | ||
800 | devc = sdi->priv; | |
801 | ||
802 | if (id == SR_CONF_SAMPLERATE) { | |
803 | ret = set_samplerate(sdi, *(const uint64_t *)value); | |
804 | } else if (id == SR_CONF_LIMIT_MSEC) { | |
805 | devc->limit_msec = *(const uint64_t *)value; | |
806 | if (devc->limit_msec > 0) | |
807 | ret = SR_OK; | |
808 | else | |
809 | ret = SR_ERR; | |
810 | } else if (id == SR_CONF_CAPTURE_RATIO) { | |
811 | devc->capture_ratio = *(const uint64_t *)value; | |
812 | if (devc->capture_ratio < 0 || devc->capture_ratio > 100) | |
813 | ret = SR_ERR; | |
814 | else | |
815 | ret = SR_OK; | |
816 | } else { | |
817 | ret = SR_ERR; | |
818 | } | |
819 | ||
820 | return ret; | |
821 | } | |
822 | ||
823 | static int config_list(int key, const void **data, const struct sr_dev_inst *sdi) | |
824 | { | |
825 | ||
826 | (void)sdi; | |
827 | ||
828 | switch (key) { | |
829 | case SR_CONF_DEVICE_OPTIONS: | |
830 | *data = hwcaps; | |
831 | break; | |
832 | case SR_CONF_SAMPLERATE: | |
833 | *data = &samplerates; | |
834 | break; | |
835 | case SR_CONF_TRIGGER_TYPE: | |
836 | *data = (char *)TRIGGER_TYPE; | |
837 | break; | |
838 | default: | |
839 | return SR_ERR_ARG; | |
840 | } | |
841 | ||
842 | return SR_OK; | |
843 | } | |
844 | ||
845 | /* Software trigger to determine exact trigger position. */ | |
846 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
847 | struct sigma_trigger *t) | |
848 | { | |
849 | int i; | |
850 | ||
851 | for (i = 0; i < 8; ++i) { | |
852 | if (i > 0) | |
853 | last_sample = samples[i-1]; | |
854 | ||
855 | /* Simple triggers. */ | |
856 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
857 | continue; | |
858 | ||
859 | /* Rising edge. */ | |
860 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
861 | t->risingmask) != t->risingmask) | |
862 | continue; | |
863 | ||
864 | /* Falling edge. */ | |
865 | if ((last_sample & t->fallingmask) != t->fallingmask || | |
866 | (samples[i] & t->fallingmask) != 0) | |
867 | continue; | |
868 | ||
869 | break; | |
870 | } | |
871 | ||
872 | /* If we did not match, return original trigger pos. */ | |
873 | return i & 0x7; | |
874 | } | |
875 | ||
876 | /* | |
877 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. | |
878 | * Each event is 20ns apart, and can contain multiple samples. | |
879 | * | |
880 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
881 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
882 | * For 50 MHz and below, events contain one sample for each channel, | |
883 | * spread 20 ns apart. | |
884 | */ | |
885 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
886 | uint16_t *lastsample, int triggerpos, | |
887 | uint16_t limit_chunk, void *cb_data) | |
888 | { | |
889 | struct sr_dev_inst *sdi = cb_data; | |
890 | struct dev_context *devc = sdi->priv; | |
891 | uint16_t tsdiff, ts; | |
892 | uint16_t samples[65536 * devc->samples_per_event]; | |
893 | struct sr_datafeed_packet packet; | |
894 | struct sr_datafeed_logic logic; | |
895 | int i, j, k, l, numpad, tosend; | |
896 | size_t n = 0, sent = 0; | |
897 | int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event; | |
898 | uint16_t *event; | |
899 | uint16_t cur_sample; | |
900 | int triggerts = -1; | |
901 | ||
902 | /* Check if trigger is in this chunk. */ | |
903 | if (triggerpos != -1) { | |
904 | if (devc->cur_samplerate <= SR_MHZ(50)) | |
905 | triggerpos -= EVENTS_PER_CLUSTER - 1; | |
906 | ||
907 | if (triggerpos < 0) | |
908 | triggerpos = 0; | |
909 | ||
910 | /* Find in which cluster the trigger occured. */ | |
911 | triggerts = triggerpos / 7; | |
912 | } | |
913 | ||
914 | /* For each ts. */ | |
915 | for (i = 0; i < 64; ++i) { | |
916 | ts = *(uint16_t *) &buf[i * 16]; | |
917 | tsdiff = ts - *lastts; | |
918 | *lastts = ts; | |
919 | ||
920 | /* Decode partial chunk. */ | |
921 | if (limit_chunk && ts > limit_chunk) | |
922 | return SR_OK; | |
923 | ||
924 | /* Pad last sample up to current point. */ | |
925 | numpad = tsdiff * devc->samples_per_event - clustersize; | |
926 | if (numpad > 0) { | |
927 | for (j = 0; j < numpad; ++j) | |
928 | samples[j] = *lastsample; | |
929 | ||
930 | n = numpad; | |
931 | } | |
932 | ||
933 | /* Send samples between previous and this timestamp to sigrok. */ | |
934 | sent = 0; | |
935 | while (sent < n) { | |
936 | tosend = MIN(2048, n - sent); | |
937 | ||
938 | packet.type = SR_DF_LOGIC; | |
939 | packet.payload = &logic; | |
940 | logic.length = tosend * sizeof(uint16_t); | |
941 | logic.unitsize = 2; | |
942 | logic.data = samples + sent; | |
943 | sr_session_send(devc->session_dev_id, &packet); | |
944 | ||
945 | sent += tosend; | |
946 | } | |
947 | n = 0; | |
948 | ||
949 | event = (uint16_t *) &buf[i * 16 + 2]; | |
950 | cur_sample = 0; | |
951 | ||
952 | /* For each event in cluster. */ | |
953 | for (j = 0; j < 7; ++j) { | |
954 | ||
955 | /* For each sample in event. */ | |
956 | for (k = 0; k < devc->samples_per_event; ++k) { | |
957 | cur_sample = 0; | |
958 | ||
959 | /* For each probe. */ | |
960 | for (l = 0; l < devc->num_probes; ++l) | |
961 | cur_sample |= (!!(event[j] & (1 << (l * | |
962 | devc->samples_per_event + k)))) << l; | |
963 | ||
964 | samples[n++] = cur_sample; | |
965 | } | |
966 | } | |
967 | ||
968 | /* Send data up to trigger point (if triggered). */ | |
969 | sent = 0; | |
970 | if (i == triggerts) { | |
971 | /* | |
972 | * Trigger is not always accurate to sample because of | |
973 | * pipeline delay. However, it always triggers before | |
974 | * the actual event. We therefore look at the next | |
975 | * samples to pinpoint the exact position of the trigger. | |
976 | */ | |
977 | tosend = get_trigger_offset(samples, *lastsample, | |
978 | &devc->trigger); | |
979 | ||
980 | if (tosend > 0) { | |
981 | packet.type = SR_DF_LOGIC; | |
982 | packet.payload = &logic; | |
983 | logic.length = tosend * sizeof(uint16_t); | |
984 | logic.unitsize = 2; | |
985 | logic.data = samples; | |
986 | sr_session_send(devc->session_dev_id, &packet); | |
987 | ||
988 | sent += tosend; | |
989 | } | |
990 | ||
991 | /* Only send trigger if explicitly enabled. */ | |
992 | if (devc->use_triggers) { | |
993 | packet.type = SR_DF_TRIGGER; | |
994 | sr_session_send(devc->session_dev_id, &packet); | |
995 | } | |
996 | } | |
997 | ||
998 | /* Send rest of the chunk to sigrok. */ | |
999 | tosend = n - sent; | |
1000 | ||
1001 | if (tosend > 0) { | |
1002 | packet.type = SR_DF_LOGIC; | |
1003 | packet.payload = &logic; | |
1004 | logic.length = tosend * sizeof(uint16_t); | |
1005 | logic.unitsize = 2; | |
1006 | logic.data = samples + sent; | |
1007 | sr_session_send(devc->session_dev_id, &packet); | |
1008 | } | |
1009 | ||
1010 | *lastsample = samples[n - 1]; | |
1011 | } | |
1012 | ||
1013 | return SR_OK; | |
1014 | } | |
1015 | ||
1016 | static int receive_data(int fd, int revents, void *cb_data) | |
1017 | { | |
1018 | struct sr_dev_inst *sdi = cb_data; | |
1019 | struct dev_context *devc = sdi->priv; | |
1020 | struct sr_datafeed_packet packet; | |
1021 | const int chunks_per_read = 32; | |
1022 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
1023 | int bufsz, numchunks, i, newchunks; | |
1024 | uint64_t running_msec; | |
1025 | struct timeval tv; | |
1026 | ||
1027 | (void)fd; | |
1028 | (void)revents; | |
1029 | ||
1030 | /* Get the current position. */ | |
1031 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); | |
1032 | ||
1033 | numchunks = (devc->state.stoppos + 511) / 512; | |
1034 | ||
1035 | if (devc->state.state == SIGMA_IDLE) | |
1036 | return TRUE; | |
1037 | ||
1038 | if (devc->state.state == SIGMA_CAPTURE) { | |
1039 | /* Check if the timer has expired, or memory is full. */ | |
1040 | gettimeofday(&tv, 0); | |
1041 | running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 + | |
1042 | (tv.tv_usec - devc->start_tv.tv_usec) / 1000; | |
1043 | ||
1044 | if (running_msec < devc->limit_msec && numchunks < 32767) | |
1045 | return TRUE; /* While capturing... */ | |
1046 | else | |
1047 | hw_dev_acquisition_stop(sdi, sdi); | |
1048 | ||
1049 | } | |
1050 | ||
1051 | if (devc->state.state == SIGMA_DOWNLOAD) { | |
1052 | if (devc->state.chunks_downloaded >= numchunks) { | |
1053 | /* End of samples. */ | |
1054 | packet.type = SR_DF_END; | |
1055 | sr_session_send(devc->session_dev_id, &packet); | |
1056 | ||
1057 | devc->state.state = SIGMA_IDLE; | |
1058 | ||
1059 | return TRUE; | |
1060 | } | |
1061 | ||
1062 | newchunks = MIN(chunks_per_read, | |
1063 | numchunks - devc->state.chunks_downloaded); | |
1064 | ||
1065 | sr_info("Downloading sample data: %.0f %%.", | |
1066 | 100.0 * devc->state.chunks_downloaded / numchunks); | |
1067 | ||
1068 | bufsz = sigma_read_dram(devc->state.chunks_downloaded, | |
1069 | newchunks, buf, devc); | |
1070 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ | |
1071 | (void)bufsz; | |
1072 | ||
1073 | /* Find first ts. */ | |
1074 | if (devc->state.chunks_downloaded == 0) { | |
1075 | devc->state.lastts = *(uint16_t *) buf - 1; | |
1076 | devc->state.lastsample = 0; | |
1077 | } | |
1078 | ||
1079 | /* Decode chunks and send them to sigrok. */ | |
1080 | for (i = 0; i < newchunks; ++i) { | |
1081 | int limit_chunk = 0; | |
1082 | ||
1083 | /* The last chunk may potentially be only in part. */ | |
1084 | if (devc->state.chunks_downloaded == numchunks - 1) { | |
1085 | /* Find the last valid timestamp */ | |
1086 | limit_chunk = devc->state.stoppos % 512 + devc->state.lastts; | |
1087 | } | |
1088 | ||
1089 | if (devc->state.chunks_downloaded + i == devc->state.triggerchunk) | |
1090 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
1091 | &devc->state.lastts, | |
1092 | &devc->state.lastsample, | |
1093 | devc->state.triggerpos & 0x1ff, | |
1094 | limit_chunk, sdi); | |
1095 | else | |
1096 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
1097 | &devc->state.lastts, | |
1098 | &devc->state.lastsample, | |
1099 | -1, limit_chunk, sdi); | |
1100 | ||
1101 | ++devc->state.chunks_downloaded; | |
1102 | } | |
1103 | } | |
1104 | ||
1105 | return TRUE; | |
1106 | } | |
1107 | ||
1108 | /* Build a LUT entry used by the trigger functions. */ | |
1109 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
1110 | { | |
1111 | int i, j, k, bit; | |
1112 | ||
1113 | /* For each quad probe. */ | |
1114 | for (i = 0; i < 4; ++i) { | |
1115 | entry[i] = 0xffff; | |
1116 | ||
1117 | /* For each bit in LUT. */ | |
1118 | for (j = 0; j < 16; ++j) | |
1119 | ||
1120 | /* For each probe in quad. */ | |
1121 | for (k = 0; k < 4; ++k) { | |
1122 | bit = 1 << (i * 4 + k); | |
1123 | ||
1124 | /* Set bit in entry */ | |
1125 | if ((mask & bit) && | |
1126 | ((!(value & bit)) != | |
1127 | (!(j & (1 << k))))) | |
1128 | entry[i] &= ~(1 << j); | |
1129 | } | |
1130 | } | |
1131 | } | |
1132 | ||
1133 | /* Add a logical function to LUT mask. */ | |
1134 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1135 | int index, int neg, uint16_t *mask) | |
1136 | { | |
1137 | int i, j; | |
1138 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1139 | ||
1140 | memset(x, 0, 4 * sizeof(int)); | |
1141 | ||
1142 | /* Trigger detect condition. */ | |
1143 | switch (oper) { | |
1144 | case OP_LEVEL: | |
1145 | x[0][1] = 1; | |
1146 | x[1][1] = 1; | |
1147 | break; | |
1148 | case OP_NOT: | |
1149 | x[0][0] = 1; | |
1150 | x[1][0] = 1; | |
1151 | break; | |
1152 | case OP_RISE: | |
1153 | x[0][1] = 1; | |
1154 | break; | |
1155 | case OP_FALL: | |
1156 | x[1][0] = 1; | |
1157 | break; | |
1158 | case OP_RISEFALL: | |
1159 | x[0][1] = 1; | |
1160 | x[1][0] = 1; | |
1161 | break; | |
1162 | case OP_NOTRISE: | |
1163 | x[1][1] = 1; | |
1164 | x[0][0] = 1; | |
1165 | x[1][0] = 1; | |
1166 | break; | |
1167 | case OP_NOTFALL: | |
1168 | x[1][1] = 1; | |
1169 | x[0][0] = 1; | |
1170 | x[0][1] = 1; | |
1171 | break; | |
1172 | case OP_NOTRISEFALL: | |
1173 | x[1][1] = 1; | |
1174 | x[0][0] = 1; | |
1175 | break; | |
1176 | } | |
1177 | ||
1178 | /* Transpose if neg is set. */ | |
1179 | if (neg) { | |
1180 | for (i = 0; i < 2; ++i) { | |
1181 | for (j = 0; j < 2; ++j) { | |
1182 | tmp = x[i][j]; | |
1183 | x[i][j] = x[1-i][1-j]; | |
1184 | x[1-i][1-j] = tmp; | |
1185 | } | |
1186 | } | |
1187 | } | |
1188 | ||
1189 | /* Update mask with function. */ | |
1190 | for (i = 0; i < 16; ++i) { | |
1191 | a = (i >> (2 * index + 0)) & 1; | |
1192 | b = (i >> (2 * index + 1)) & 1; | |
1193 | ||
1194 | aset = (*mask >> i) & 1; | |
1195 | bset = x[b][a]; | |
1196 | ||
1197 | if (func == FUNC_AND || func == FUNC_NAND) | |
1198 | rset = aset & bset; | |
1199 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1200 | rset = aset | bset; | |
1201 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1202 | rset = aset ^ bset; | |
1203 | ||
1204 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1205 | rset = !rset; | |
1206 | ||
1207 | *mask &= ~(1 << i); | |
1208 | ||
1209 | if (rset) | |
1210 | *mask |= 1 << i; | |
1211 | } | |
1212 | } | |
1213 | ||
1214 | /* | |
1215 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1216 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1217 | * set at any time, but a full mask and value can be set (0/1). | |
1218 | */ | |
1219 | static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc) | |
1220 | { | |
1221 | int i,j; | |
1222 | uint16_t masks[2] = { 0, 0 }; | |
1223 | ||
1224 | memset(lut, 0, sizeof(struct triggerlut)); | |
1225 | ||
1226 | /* Contant for simple triggers. */ | |
1227 | lut->m4 = 0xa000; | |
1228 | ||
1229 | /* Value/mask trigger support. */ | |
1230 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, | |
1231 | lut->m2d); | |
1232 | ||
1233 | /* Rise/fall trigger support. */ | |
1234 | for (i = 0, j = 0; i < 16; ++i) { | |
1235 | if (devc->trigger.risingmask & (1 << i) || | |
1236 | devc->trigger.fallingmask & (1 << i)) | |
1237 | masks[j++] = 1 << i; | |
1238 | } | |
1239 | ||
1240 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1241 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1242 | ||
1243 | /* Add glue logic */ | |
1244 | if (masks[0] || masks[1]) { | |
1245 | /* Transition trigger. */ | |
1246 | if (masks[0] & devc->trigger.risingmask) | |
1247 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); | |
1248 | if (masks[0] & devc->trigger.fallingmask) | |
1249 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); | |
1250 | if (masks[1] & devc->trigger.risingmask) | |
1251 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); | |
1252 | if (masks[1] & devc->trigger.fallingmask) | |
1253 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); | |
1254 | } else { | |
1255 | /* Only value/mask trigger. */ | |
1256 | lut->m3 = 0xffff; | |
1257 | } | |
1258 | ||
1259 | /* Triggertype: event. */ | |
1260 | lut->params.selres = 3; | |
1261 | ||
1262 | return SR_OK; | |
1263 | } | |
1264 | ||
1265 | static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi, | |
1266 | void *cb_data) | |
1267 | { | |
1268 | struct dev_context *devc; | |
1269 | struct clockselect_50 clockselect; | |
1270 | int frac, triggerpin, ret; | |
1271 | uint8_t triggerselect = 0; | |
1272 | struct triggerinout triggerinout_conf; | |
1273 | struct triggerlut lut; | |
1274 | ||
1275 | devc = sdi->priv; | |
1276 | ||
1277 | if (configure_probes(sdi) != SR_OK) { | |
1278 | sr_err("Failed to configure probes."); | |
1279 | return SR_ERR; | |
1280 | } | |
1281 | ||
1282 | /* If the samplerate has not been set, default to 200 kHz. */ | |
1283 | if (devc->cur_firmware == -1) { | |
1284 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) | |
1285 | return ret; | |
1286 | } | |
1287 | ||
1288 | /* Enter trigger programming mode. */ | |
1289 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc); | |
1290 | ||
1291 | /* 100 and 200 MHz mode. */ | |
1292 | if (devc->cur_samplerate >= SR_MHZ(100)) { | |
1293 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc); | |
1294 | ||
1295 | /* Find which pin to trigger on from mask. */ | |
1296 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
1297 | if ((devc->trigger.risingmask | devc->trigger.fallingmask) & | |
1298 | (1 << triggerpin)) | |
1299 | break; | |
1300 | ||
1301 | /* Set trigger pin and light LED on trigger. */ | |
1302 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1303 | ||
1304 | /* Default rising edge. */ | |
1305 | if (devc->trigger.fallingmask) | |
1306 | triggerselect |= 1 << 3; | |
1307 | ||
1308 | /* All other modes. */ | |
1309 | } else if (devc->cur_samplerate <= SR_MHZ(50)) { | |
1310 | build_basic_trigger(&lut, devc); | |
1311 | ||
1312 | sigma_write_trigger_lut(&lut, devc); | |
1313 | ||
1314 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1315 | } | |
1316 | ||
1317 | /* Setup trigger in and out pins to default values. */ | |
1318 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); | |
1319 | triggerinout_conf.trgout_bytrigger = 1; | |
1320 | triggerinout_conf.trgout_enable = 1; | |
1321 | ||
1322 | sigma_write_register(WRITE_TRIGGER_OPTION, | |
1323 | (uint8_t *) &triggerinout_conf, | |
1324 | sizeof(struct triggerinout), devc); | |
1325 | ||
1326 | /* Go back to normal mode. */ | |
1327 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc); | |
1328 | ||
1329 | /* Set clock select register. */ | |
1330 | if (devc->cur_samplerate == SR_MHZ(200)) | |
1331 | /* Enable 4 probes. */ | |
1332 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc); | |
1333 | else if (devc->cur_samplerate == SR_MHZ(100)) | |
1334 | /* Enable 8 probes. */ | |
1335 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc); | |
1336 | else { | |
1337 | /* | |
1338 | * 50 MHz mode (or fraction thereof). Any fraction down to | |
1339 | * 50 MHz / 256 can be used, but is not supported by sigrok API. | |
1340 | */ | |
1341 | frac = SR_MHZ(50) / devc->cur_samplerate - 1; | |
1342 | ||
1343 | clockselect.async = 0; | |
1344 | clockselect.fraction = frac; | |
1345 | clockselect.disabled_probes = 0; | |
1346 | ||
1347 | sigma_write_register(WRITE_CLOCK_SELECT, | |
1348 | (uint8_t *) &clockselect, | |
1349 | sizeof(clockselect), devc); | |
1350 | } | |
1351 | ||
1352 | /* Setup maximum post trigger time. */ | |
1353 | sigma_set_register(WRITE_POST_TRIGGER, | |
1354 | (devc->capture_ratio * 255) / 100, devc); | |
1355 | ||
1356 | /* Start acqusition. */ | |
1357 | gettimeofday(&devc->start_tv, 0); | |
1358 | sigma_set_register(WRITE_MODE, 0x0d, devc); | |
1359 | ||
1360 | devc->session_dev_id = cb_data; | |
1361 | ||
1362 | /* Send header packet to the session bus. */ | |
1363 | std_session_send_df_header(cb_data, DRIVER_LOG_DOMAIN); | |
1364 | ||
1365 | /* Add capture source. */ | |
1366 | sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi); | |
1367 | ||
1368 | devc->state.state = SIGMA_CAPTURE; | |
1369 | ||
1370 | return SR_OK; | |
1371 | } | |
1372 | ||
1373 | static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data) | |
1374 | { | |
1375 | struct dev_context *devc; | |
1376 | uint8_t modestatus; | |
1377 | ||
1378 | (void)cb_data; | |
1379 | ||
1380 | sr_source_remove(0); | |
1381 | ||
1382 | if (!(devc = sdi->priv)) { | |
1383 | sr_err("%s: sdi->priv was NULL", __func__); | |
1384 | return SR_ERR_BUG; | |
1385 | } | |
1386 | ||
1387 | /* Stop acquisition. */ | |
1388 | sigma_set_register(WRITE_MODE, 0x11, devc); | |
1389 | ||
1390 | /* Set SDRAM Read Enable. */ | |
1391 | sigma_set_register(WRITE_MODE, 0x02, devc); | |
1392 | ||
1393 | /* Get the current position. */ | |
1394 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); | |
1395 | ||
1396 | /* Check if trigger has fired. */ | |
1397 | modestatus = sigma_get_register(READ_MODE, devc); | |
1398 | if (modestatus & 0x20) | |
1399 | devc->state.triggerchunk = devc->state.triggerpos / 512; | |
1400 | else | |
1401 | devc->state.triggerchunk = -1; | |
1402 | ||
1403 | devc->state.chunks_downloaded = 0; | |
1404 | ||
1405 | devc->state.state = SIGMA_DOWNLOAD; | |
1406 | ||
1407 | return SR_OK; | |
1408 | } | |
1409 | ||
1410 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info = { | |
1411 | .name = "asix-sigma", | |
1412 | .longname = "ASIX SIGMA/SIGMA2", | |
1413 | .api_version = 1, | |
1414 | .init = hw_init, | |
1415 | .cleanup = hw_cleanup, | |
1416 | .scan = hw_scan, | |
1417 | .dev_list = hw_dev_list, | |
1418 | .dev_clear = clear_instances, | |
1419 | .config_get = config_get, | |
1420 | .config_set = config_set, | |
1421 | .config_list = config_list, | |
1422 | .dev_open = hw_dev_open, | |
1423 | .dev_close = hw_dev_close, | |
1424 | .dev_acquisition_start = hw_dev_acquisition_start, | |
1425 | .dev_acquisition_stop = hw_dev_acquisition_stop, | |
1426 | .priv = NULL, | |
1427 | }; |